AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
 All Classes Variables
DAQ_LINK.vhd
1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 10:14:48 04/20/2014
6 -- Design Name:
7 -- Module Name: DAQ_LINK - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 library IEEE;
21 use IEEE.STD_LOGIC_1164.ALL;
22 use IEEE.STD_LOGIC_ARITH.ALL;
23 use IEEE.STD_LOGIC_UNSIGNED.ALL;
24 use IEEE.std_logic_misc.all;
25 
26 -- Uncomment the following library declaration if using
27 -- arithmetic functions with Signed or Unsigned values
28 --use IEEE.NUMERIC_STD.ALL;
29 
30 -- Uncomment the following library declaration if instantiating
31 -- any Xilinx primitives in this code.
32 library UNISIM;
33 use UNISIM.VComponents.all;
34 Library UNIMACRO;
35 use UNIMACRO.vcomponents.all;
36 
37 entity DAQ_LINK is
38  Generic (
39 -- REFCLK frequency, select one among 100, 125, 200 and 250
40 -- If your REFCLK frequency is not in the list, please contact wusx@bu.edu
41  F_REFCLK : integer := 250;
42  DRPclk_period : integer := 20; -- unit is ns
43 -- If you do not use the trigger port, set it to false
44 -- USE_TRIGGER_PORT : boolean := true;
45  simulation : boolean := false);
46  Port ( sysclk : in STD_LOGIC;
47  DRPclk : in STD_LOGIC;
48  fake_clk : in STD_LOGIC;
49  EventDataClk : in STD_LOGIC;
50  reset : in STD_LOGIC;
51  USE_TRIGGER_PORT : boolean;
52  test : in STD_LOGIC;
53  ovfl_warning : IN std_logic;
54  ForceError : in STD_LOGIC_VECTOR (3 downto 0);
55  fake_lengthA : in STD_LOGIC_VECTOR (17 downto 0);
56  fake_lengthB : in STD_LOGIC_VECTOR (17 downto 0);
57  fake_seed : in STD_LOGIC_VECTOR (16 downto 0);
58  event_number_avl : in std_logic;
59  event_number : in std_logic_vector(59 downto 0);
60  board_ID : in std_logic_vector(15 downto 0);
61  status : out std_logic_vector(31 downto 0);
62  AMC_REFCLK_N : in STD_LOGIC;
63  AMC_REFCLK_P : in STD_LOGIC;
64  AMC_RXN : in STD_LOGIC;
65  AMC_RXP : in STD_LOGIC;
66  AMC_TXN : out STD_LOGIC;
67  AMC_TXP : out STD_LOGIC;
68 -- TRIGGER port
69  TTCclk : in STD_LOGIC;
70 -- TTS port
71  TTSclk : in STD_LOGIC; -- clock source which clocks TTS signals
72  TTS : in STD_LOGIC_VECTOR (3 downto 0)
73  );
74 end DAQ_LINK;
75 
76 architecture Behavioral of DAQ_LINK is
77 COMPONENT DAQ_Link_7S
78  Generic (
79  simulation : boolean := false);
80  PORT(
81  reset : IN std_logic;
82  USE_TRIGGER_PORT : boolean;
83  UsrClk : IN std_logic;
84  cplllock : IN std_logic;
85  RxResetDone : IN std_logic;
86  txfsmresetdone : IN std_logic;
87  RXNOTINTABLE : IN std_logic_vector(1 downto 0);
88  RXCHARISCOMMA : IN std_logic_vector(1 downto 0);
89  RXCHARISK : IN std_logic_vector(1 downto 0);
90  RXDATA : IN std_logic_vector(15 downto 0);
91  TTCclk : IN std_logic;
92  BcntRes : IN std_logic;
93  trig : IN std_logic_vector(7 downto 0);
94  TTSclk : IN std_logic;
95  TTS : IN std_logic_vector(3 downto 0);
96  EventDataClk : IN std_logic;
97  EventData_valid : IN std_logic;
98  EventData_header : IN std_logic;
99  EventData_trailer : IN std_logic;
100  EventData : IN std_logic_vector(63 downto 0);
101  TXCHARISK : OUT std_logic_vector(1 downto 0);
102  TXDATA : OUT std_logic_vector(15 downto 0);
103  AlmostFull : OUT std_logic;
104  Ready : OUT std_logic;
105  sysclk : in STD_LOGIC;
106  L1A_DATA_we : out STD_LOGIC; -- last data word
107  L1A_DATA : out STD_LOGIC_VECTOR (15 downto 0)
108  );
109 end COMPONENT;
110 COMPONENT DAQLINK_7S_init
111 generic
112 (
113  EXAMPLE_SIM_GTRESET_SPEEDUP : string := "TRUE"; -- simulation setting for GT SecureIP model
114  EXAMPLE_SIMULATION : integer := 0; -- Set to 1 for simulation
115  STABLE_CLOCK_PERIOD : integer := 16; --Period of the stable clock driving this state-machine, unit is [ns]
116  EXAMPLE_USE_CHIPSCOPE : integer := 0; -- Set to 1 to use Chipscope to drive resets
117  -- REFCLK frequency, select one among 100, 125, 200 and 250 If your REFCLK frequency is not in the list, please contact wusx@bu.edu
118  F_REFCLK : integer := 125
119 
120 );
121  PORT(
122  SYSCLK_IN : IN std_logic;
123  SOFT_RESET_IN : IN std_logic;
124  DONT_RESET_ON_DATA_ERROR_IN : IN std_logic;
125  GT0_DATA_VALID_IN : IN std_logic;
126  GT0_CPLLLOCKDETCLK_IN : IN std_logic;
127  GT0_CPLLRESET_IN : IN std_logic;
128  GT0_GTREFCLK0_IN : IN std_logic;
129  GT0_DRPADDR_IN : IN std_logic_vector(8 downto 0);
130  GT0_DRPCLK_IN : IN std_logic;
131  GT0_DRPDI_IN : IN std_logic_vector(15 downto 0);
132  GT0_DRPEN_IN : IN std_logic;
133  GT0_DRPWE_IN : IN std_logic;
134  GT0_LOOPBACK_IN : IN std_logic_vector(2 downto 0);
135  GT0_RXUSERRDY_IN : IN std_logic;
136  GT0_RXUSRCLK_IN : IN std_logic;
137  GT0_RXUSRCLK2_IN : IN std_logic;
138  GT0_RXPRBSSEL_IN : IN std_logic_vector(2 downto 0);
139  GT0_RXPRBSCNTRESET_IN : IN std_logic;
140  GT0_GTXRXP_IN : IN std_logic;
141  GT0_GTXRXN_IN : IN std_logic;
142  GT0_RXMCOMMAALIGNEN_IN : IN std_logic;
143  GT0_RXPCOMMAALIGNEN_IN : IN std_logic;
144  GT0_GTRXRESET_IN : IN std_logic;
145  GT0_RXPMARESET_IN : IN std_logic;
146  GT0_GTTXRESET_IN : IN std_logic;
147  GT0_TXUSERRDY_IN : IN std_logic;
148  GT0_TXUSRCLK_IN : IN std_logic;
149  GT0_TXUSRCLK2_IN : IN std_logic;
150  GT0_TXDIFFCTRL_IN : IN std_logic_vector(3 downto 0);
151  GT0_TXDATA_IN : IN std_logic_vector(15 downto 0);
152  GT0_TXCHARISK_IN : IN std_logic_vector(1 downto 0);
153  GT0_TXPRBSSEL_IN : IN std_logic_vector(2 downto 0);
154  GT0_GTREFCLK0_COMMON_IN : IN std_logic;
155  GT0_QPLLLOCKDETCLK_IN : IN std_logic;
156  GT0_QPLLRESET_IN : IN std_logic;
157  GT0_TX_FSM_RESET_DONE_OUT : OUT std_logic;
158  GT0_RX_FSM_RESET_DONE_OUT : OUT std_logic;
159  GT0_CPLLFBCLKLOST_OUT : OUT std_logic;
160  GT0_CPLLLOCK_OUT : OUT std_logic;
161  GT0_DRPDO_OUT : OUT std_logic_vector(15 downto 0);
162  GT0_DRPRDY_OUT : OUT std_logic;
163  GT0_EYESCANDATAERROR_OUT : OUT std_logic;
164  GT0_RXCDRLOCK_OUT : OUT std_logic;
165  GT0_RXCLKCORCNT_OUT : OUT std_logic_vector(1 downto 0);
166  GT0_RXDATA_OUT : OUT std_logic_vector(15 downto 0);
167  GT0_RXPRBSERR_OUT : OUT std_logic;
168  GT0_RXDISPERR_OUT : OUT std_logic_vector(1 downto 0);
169  GT0_RXNOTINTABLE_OUT : OUT std_logic_vector(1 downto 0);
170  GT0_RXCHARISCOMMA_OUT : OUT std_logic_vector(1 downto 0);
171  GT0_RXCHARISK_OUT : OUT std_logic_vector(1 downto 0);
172  GT0_RXRESETDONE_OUT : OUT std_logic;
173  GT0_GTXTXN_OUT : OUT std_logic;
174  GT0_GTXTXP_OUT : OUT std_logic;
175  GT0_TXOUTCLK_OUT : OUT std_logic;
176  GT0_TXOUTCLKFABRIC_OUT : OUT std_logic;
177  GT0_TXOUTCLKPCS_OUT : OUT std_logic;
178  GT0_TXRESETDONE_OUT : OUT std_logic;
179  GT0_QPLLLOCK_OUT : OUT std_logic
180  );
181 END COMPONENT;
182 COMPONENT fake_event
183  PORT(
184  sysclk : IN std_logic;
185  UsrClk : IN std_logic;
186  reset : IN std_logic;
187  fifo_rst : IN std_logic;
188  fifo_en : IN std_logic;
189  fake_en : IN std_logic;
190  sync : IN std_logic;
191  ovfl_warning : IN std_logic;
192  fake_length : IN std_logic_vector(17 downto 0);
193  LinkFull : IN std_logic;
194  board_ID : in std_logic_vector(15 downto 0);
195  L1A_DATA : IN std_logic_vector(15 downto 0);
196  L1A_WrEn : IN std_logic;
197  fake_header : OUT std_logic;
198  fake_CRC : OUT std_logic;
199  empty_event_flag : OUT std_logic;
200  fake_DATA : OUT std_logic_vector(15 downto 0);
201  fake_WrEn : OUT std_logic
202  );
203 END COMPONENT;
204 COMPONENT FIFO_RESET_7S
205  PORT(
206  reset : IN std_logic;
207  clk : IN std_logic;
208  fifo_rst : OUT std_logic;
209  fifo_en : OUT std_logic
210  );
211 END COMPONENT;
212 function GTXRESET_SPEEDUP(is_sim : boolean) return string is
213  begin
214  if(is_sim)then
215  return "TRUE";
216  else
217  return "FALSE";
218  end if;
219  end function;
220 signal UsrClk : std_logic := '0';
221 signal cplllock : std_logic := '0';
222 signal TXOUTCLK : std_logic := '0';
223 signal RxResetDone : std_logic := '0';
224 signal txfsmresetdone : std_logic := '0';
225 signal LoopBack : std_logic_vector(2 downto 0) := (others => '0');
226 signal K_Cntr : std_logic_vector(7 downto 0) := (others => '0');
227 signal reset_SyncRegs : std_logic_vector(3 downto 0) := (others => '0');
228 signal RxResetDoneSyncRegs : std_logic_vector(2 downto 0) := (others => '0');
229 signal DATA_VALID : std_logic := '0';
230 signal RXNOTINTABLE : std_logic_vector(1 downto 0) := (others => '0');
231 signal RXCHARISCOMMA : std_logic_vector(1 downto 0) := (others => '0');
232 signal RXCHARISK : std_logic_vector(1 downto 0) := (others => '0');
233 signal RXDATA : std_logic_vector(15 downto 0) := (others => '0');
234 signal TXDIFFCTRL : std_logic_vector(3 downto 0) := x"b"; -- 790mV drive
235 signal TXCHARISK : std_logic_vector(1 downto 0) := (others => '0');
236 signal TXDATA : std_logic_vector(15 downto 0) := (others => '0');
237 signal EventData_valid : std_logic := '0';
238 signal EventData_header : std_logic := '0';
239 signal EventData_trailer : std_logic := '0';
240 signal EventData : std_logic_vector(63 downto 0) := (others => '0');
241 signal EventDatap : std_logic_vector(63 downto 0) := (others => '0');
242 signal AlmostFull : std_logic;
243 signal fakereset : std_logic;
244 signal Ready : std_logic;
245 signal AMC_REFCLK : std_logic := '0';
246 signal toggle : std_logic := '0';
247 signal toggle_r : std_logic_vector(4 downto 0) := (others => '0');
248 signal fake_header : std_logic;
249 signal fake_header_q : std_logic;
250 signal fake_CRC : std_logic;
251 signal fake_length : std_logic_vector(17 downto 0);
252 signal fake_DATA : std_logic_vector(15 downto 0);
253 signal fake_WrEn : std_logic;
254 signal sync : std_logic := '1';
255 signal LinkFull : std_logic := '0';
256 signal L1A_DATA : std_logic_vector(15 downto 0) := (others => '0');
257 signal L1A_DATAp : std_logic_vector(15 downto 0) := (others => '0');
258 signal L1A_DATA_wa : std_logic_vector(3 downto 0) := (others => '0');
259 signal L1A_DATA_we : std_logic := '0';
260 signal L1A_WrEn : std_logic := '0';
261 signal ec_byte_cnt : std_logic := '0';
262 signal byte_cnt : std_logic_vector(1 downto 0) := (others => '0');
263 signal ld_data : std_logic := '1';
264 signal fake_CRC_q : std_logic_vector(1 downto 0) := (others => '0');
265 signal fifo_rst : std_logic := '0';
266 signal fifo_en : std_logic := '0';
267 signal BcntRes : std_logic := '0';
268 signal trig : std_logic_vector(7 downto 0) := (others => '0');
269 signal bcnt : std_logic_vector(11 downto 0) := (others => '0');
270 signal ec_FIFO_RA : std_logic := '0';
271 signal FIFO_DI : std_logic_vector(17 downto 0) := (others => '0');
272 signal FIFO_DO : std_logic_vector(71 downto 0) := (others => '0');
273 signal FIFO_WA : std_logic_vector(10 downto 0) := (others => '0');
274 signal FIFO_RA : std_logic_vector(8 downto 0) := (others => '0');
275 signal FIFO_WC : std_logic_vector(8 downto 0) := (others => '0');
276 signal A : std_logic_vector(29 downto 0) := (others => '0');
277 signal C : std_logic_vector(47 downto 0) := (others => '0');
278 signal D : std_logic_vector(24 downto 0) := (others => '0');
279 signal P : std_logic_vector(47 downto 0) := (others => '0');
280 signal lfsr : std_logic_vector(17 downto 0) := (others => '0');
281 begin
282 i_DAQ_Link_7S : DAQ_Link_7S
283  generic map(simulation => simulation)
284  PORT MAP (
285  reset => reset,
286  USE_TRIGGER_PORT => USE_TRIGGER_PORT,
287  UsrClk => UsrClk,
288  cplllock => cplllock,
289  RxResetDone => RxResetDone,
290  txfsmresetdone => txfsmresetdone,
291  RXNOTINTABLE => RXNOTINTABLE,
292  RXCHARISCOMMA => RXCHARISCOMMA,
293  RXCHARISK => RXCHARISK,
294  RXDATA => RXDATA,
295  TXCHARISK => TXCHARISK,
296  TXDATA => TXDATA,
297  TTCclk => TTCclk ,
298  BcntRes => BcntRes,
299  trig => trig,
300  TTSclk => TTSclk ,
301  TTS => TTS,
302  EventDataClk => EventDataClk,
303  EventData_valid => EventData_valid,
304  EventData_header => EventData_header,
305  EventData_trailer => EventData_trailer,
306  EventData => EventData,
307  AlmostFull => AlmostFull,
308  Ready => Ready,
309  sysclk => sysclk,
310  L1A_DATA => L1A_DATA,
311  L1A_DATA_we => L1A_DATA_we
312  );
313 status(31) <= Ready;
314 status(30) <= test;
315 status(29) <= AlmostFull;
316 status(28 downto 24) <= (others => '0');
317 status(23 downto 20) <= TTS;
318 status(19 downto 18) <= (others => '0');
319 status(17 downto 0) <= fake_length;
320 process(TTCclk)
321 begin
322  if(TTCclk'event and TTCclk = '1')then
323  if(BcntRes = '1')then
324  Bcnt <= (others => '0');
325  else
326  Bcnt <= Bcnt + 1;
327  end if;
328  if(Bcnt = x"dea")then
329  BcntRes <= '1';
330  else
331  BcntRes <= '0';
332  end if;
333  Trig <= Trig + 1;
334  end if;
335 end process;
336 i_fakeFIFO : BRAM_SDP_MACRO
337  generic map (
338  BRAM_SIZE => "36Kb", -- Target BRAM, "18Kb" or "36Kb"
339  DEVICE => "7SERIES", -- Target device: "VIRTEX5", "VIRTEX6", "SPARTAN6"
340  WRITE_WIDTH => 18, -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
341  READ_WIDTH => 72) -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
342  port map (
343  DO => FIFO_DO, -- Output read data port, width defined by READ_WIDTH parameter
344  DI => FIFO_DI, -- Input write data port, width defined by WRITE_WIDTH parameter
345  RDADDR => FIFO_RA, -- Input read address, width defined by read port depth
346  RDCLK => EventDataClk, -- 1-bit input read clock
347  RDEN => '1', -- 1-bit input read port enable
348  REGCE => '1', -- 1-bit input read output register enable
349  RST => '0', -- 1-bit input reset
350  WE => "11", -- Input write enable, width defined by write port depth
351  WRADDR => FIFO_WA, -- Input write address, width defined by write port depth
352  WRCLK => fake_clk, -- 1-bit input write clock
353  WREN => fake_WrEn -- 1-bit input write port enable
354  );
355 FIFO_DI <= fake_crc & fake_header & fake_data;
356 EventData_trailer <= FIFO_DO(69);
357 EventData_header <= FIFO_DO(70);
358 EventData <= FIFO_DO(63 downto 0);
359 process(fake_clk,reset,ready)
360 begin
361  if(reset = '1' or ready = '0')then
362  FIFO_WA <= (others => '0');
363  FIFO_WC <= (others => '0');
364  linkfull <= '0';
365  elsif(fake_clk'event and fake_clk = '1')then
366  if(fake_WrEn = '1')then
367  FIFO_WA <= FIFO_WA + 1;
368  end if;
369  FIFO_WC <= FIFO_WA(10 downto 2) - FIFO_RA;
370  linkfull <= and_reduce(FIFO_WC(8 downto 4));
371  end if;
372 end process;
373 process(EventDataClk,reset,Ready)
374 begin
375  if(reset = '1' or ready = '0')then
376  FIFO_RA <= (others => '0');
377  ec_FIFO_RA <= '0';
378  EventData_valid <= '0';
379  elsif(EventDataClk'event and EventDataClk = '1')then
380  if(ec_FIFO_RA = '1')then
381  FIFO_RA <= FIFO_RA + 1;
382  end if;
383  if(almostfull = '1' or (FIFO_WC(8 downto 1) = x"00" and (FIFO_WC(0) = '0' or ec_FIFO_RA = '1')))then
384  ec_FIFO_RA <= '0';
385  else
386  ec_FIFO_RA <= '1';
387  end if;
388  EventData_valid <= ec_FIFO_RA;
389  end if;
390 end process;
391 process(sysclk,reset)
392 begin
393  if(reset = '1')then
394  L1A_DATA_wa <= x"0";
395  L1A_WrEn <= '0';
396  elsif(sysclk'event and sysclk = '1')then
397  if(L1A_DATA_we = '1')then
398  L1A_DATA_wa <= L1A_DATA_wa + 1;
399  end if;
400  L1A_WrEn <= L1A_DATA_we;
401  end if;
402 end process;
403 process(sysclk)
404 begin
405  if(sysclk'event and sysclk = '1')then
406  if(ForceError(2 downto 0) /= "000")then
407  case L1A_DATA_wa is
408  when x"0" => L1A_DATAp(7) <= L1A_DATA(7) xor ForceError(0);
409  when x"5" => L1A_DATAp(7) <= L1A_DATA(7) xor ForceError(1);
410  when x"a" => L1A_DATAp(7) <= L1A_DATA(7) xor ForceError(1);
411  when x"f" => L1A_DATAp(7) <= L1A_DATA(7) xor ForceError(2);
412  when others => L1A_DATAp(7) <= L1A_DATA(7);
413  end case;
414  L1A_DATAp(6 downto 0) <= L1A_DATA(6 downto 0);
415  L1A_DATAp(15 downto 8) <= L1A_DATA(15 downto 8);
416  else
417  L1A_DATAp <= L1A_DATA;
418  end if;
419  end if;
420 end process;
421 i_fake_event : fake_event PORT MAP (
422  sysclk => sysclk ,
423  UsrClk => fake_clk,
424  reset => fakereset,
425  fifo_rst => fifo_rst,
426  fifo_en => fifo_en,
427  fake_en => test,
428  sync => '1',
429  ovfl_warning => ovfl_warning,
430  fake_length => fake_length,
431  LinkFull => LinkFull,
432  board_ID => board_ID,
433  L1A_DATA => L1A_DATAp,
434  L1A_WrEn => L1A_WrEn,
435  fake_header => fake_header,
436  fake_CRC => fake_CRC,
437  empty_event_flag => open,
438  fake_DATA => fake_DATA,
439  fake_WrEn => fake_WrEn
440  );
441 i_FIFO_RESET_7S: FIFO_RESET_7S PORT MAP(
442  reset => fakereset,
443  clk => sysclk ,
444  fifo_rst => fifo_rst,
445  fifo_en => fifo_en
446  );
447 i_AMC_refclk: IBUFDS_GTE2
448  port map
449  (
450  O => AMC_REFCLK,
451  ODIV2 => open,
452  CEB => '0',
453  I => AMC_REFCLK_P, -- Connect to package pin AB6
454  IB => AMC_REFCLK_N -- Connect to package pin AB5
455  );
456 fakereset <= reset or not ready;
457 process(fake_clk,reset)
458 begin
459  if(reset = '1')then
460  lfsr(16 downto 0) <= fake_seed;
461  elsif(fake_clk'event and fake_clk = '1')then
462  if(and_reduce(lfsr(16 downto 0)) = '1')then
463  lfsr(16 downto 0) <= (others => '0');
464  elsif(and_reduce(fake_seed) = '1' or (fake_header = '1' and fake_WrEn = '1'))then
465  lfsr(16 downto 0) <= lfsr(15 downto 0) & (lfsr(16) xnor lfsr(13));
466  end if;
467  end if;
468 end process;
469 process(fake_lengthA,fake_lengthB)
470 begin
471  if(fake_lengthA > fake_lengthB)then
472  A(17 downto 0) <= fake_lengthB;
473  C(34 downto 17) <= fake_lengthB;
474  D(17 downto 0) <= fake_lengthA;
475  else
476  A(17 downto 0) <= fake_lengthA;
477  C(34 downto 17) <= fake_lengthA;
478  D(17 downto 0) <= fake_lengthB;
479  end if;
480 end process;
481 fake_length <= P(34 downto 17);
482 DSP48E1_inst : DSP48E1
483  generic map (
484  -- Feature Control Attributes: Data Path Selection
485  A_INPUT => "DIRECT", -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port)
486  B_INPUT => "DIRECT", -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port)
487  USE_DPORT => TRUE, -- Select D port usage (TRUE or FALSE)
488  USE_MULT => "MULTIPLY", -- Select multiplier usage ("MULTIPLY", "DYNAMIC", or "NONE")
489  -- Pattern Detector Attributes: Pattern Detection Configuration
490  AUTORESET_PATDET => "NO_RESET", -- "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH"
491  MASK => X"3fffffffffff", -- 48-bit mask value for pattern detect (1=ignore)
492  PATTERN => X"000000000000", -- 48-bit pattern match for pattern detect
493  SEL_MASK => "MASK", -- "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2"
494  SEL_PATTERN => "PATTERN", -- Select pattern value ("PATTERN" or "C")
495  USE_PATTERN_DETECT => "NO_PATDET", -- Enable pattern detect ("PATDET" or "NO_PATDET")
496  -- Register Control Attributes: Pipeline Register Configuration
497  ACASCREG => 1, -- Number of pipeline stages between A/ACIN and ACOUT (0, 1 or 2)
498  ADREG => 0, -- Number of pipeline stages for pre-adder (0 or 1)
499  ALUMODEREG => 0, -- Number of pipeline stages for ALUMODE (0 or 1)
500  AREG => 1, -- Number of pipeline stages for A (0, 1 or 2)
501  BCASCREG => 1, -- Number of pipeline stages between B/BCIN and BCOUT (0, 1 or 2)
502  BREG => 1, -- Number of pipeline stages for B (0, 1 or 2)
503  CARRYINREG => 1, -- Number of pipeline stages for CARRYIN (0 or 1)
504  CARRYINSELREG => 1, -- Number of pipeline stages for CARRYINSEL (0 or 1)
505  CREG => 1, -- Number of pipeline stages for C (0 or 1)
506  DREG => 1, -- Number of pipeline stages for D (0 or 1)
507  INMODEREG => 0, -- Number of pipeline stages for INMODE (0 or 1)
508  MREG => 1, -- Number of multiplier pipeline stages (0 or 1)
509  OPMODEREG => 0, -- Number of pipeline stages for OPMODE (0 or 1)
510  PREG => 1, -- Number of pipeline stages for P (0 or 1)
511  USE_SIMD => "ONE48" -- SIMD selection ("ONE48", "TWO24", "FOUR12")
512  )
513  port map (
514  -- Cascade: 30-bit (each) output: Cascade Ports
515  ACOUT => open, -- 30-bit output: A port cascade output
516  BCOUT => open, -- 18-bit output: B port cascade output
517  CARRYCASCOUT => open, -- 1-bit output: Cascade carry output
518  MULTSIGNOUT => open, -- 1-bit output: Multiplier sign cascade output
519  PCOUT => open, -- 48-bit output: Cascade output
520  -- Control: 1-bit (each) output: Control Inputs/Status Bits
521  OVERFLOW => open, -- 1-bit output: Overflow in add/acc output
522  PATTERNBDETECT => open, -- 1-bit output: Pattern bar detect output
523  PATTERNDETECT => open, -- 1-bit output: Pattern detect output
524  UNDERFLOW => open, -- 1-bit output: Underflow in add/acc output
525  -- Data: 4-bit (each) output: Data Ports
526  CARRYOUT => open, -- 4-bit output: Carry output
527  P => P, -- 48-bit output: Primary data output
528  -- Cascade: 30-bit (each) input: Cascade Ports
529  ACIN => (others => '0'), -- 30-bit input: A cascade data input
530  BCIN => (others => '0'), -- 18-bit input: B cascade input
531  CARRYCASCIN => '0', -- 1-bit input: Cascade carry input
532  MULTSIGNIN => '0', -- 1-bit input: Multiplier sign input
533  PCIN => (others => '0'), -- 48-bit input: P cascade input
534  -- Control: 4-bit (each) input: Control Inputs/Status Bits
535  ALUMODE => x"0", -- 4-bit input: ALU control input
536  CARRYINSEL => (others => '0'), -- 3-bit input: Carry select input
537  CEINMODE => '1', -- 1-bit input: Clock enable input for INMODEREG
538  CLK => fake_clk, -- 1-bit input: Clock input
539  INMODE => "11101", -- 5-bit input: INMODE control input
540  OPMODE => "0110101", -- 7-bit input: Operation mode input
541  RSTINMODE => '0', -- 1-bit input: Reset input for INMODEREG
542  -- Data: 30-bit (each) input: Data Ports
543  A => A, -- 30-bit input: A data input
544  B => lfsr, -- 18-bit input: B data input
545  C => C, -- 48-bit input: C data input
546  CARRYIN => '0', -- 1-bit input: Carry input signal
547  D => D, -- 25-bit input: D data input
548  -- Reset/Clock Enable: 1-bit (each) input: Reset/Clock Enable Inputs
549  CEA1 => '1', -- 1-bit input: Clock enable input for 1st stage AREG
550  CEA2 => '1', -- 1-bit input: Clock enable input for 2nd stage AREG
551  CEAD => '1', -- 1-bit input: Clock enable input for ADREG
552  CEALUMODE => '1', -- 1-bit input: Clock enable input for ALUMODERE
553  CEB1 => fake_header, -- 1-bit input: Clock enable input for 1st stage BREG
554  CEB2 => '1', -- 1-bit input: Clock enable input for 2nd stage BREG
555  CEC => '1', -- 1-bit input: Clock enable input for CREG
556  CECARRYIN => '1', -- 1-bit input: Clock enable input for CARRYINREG
557  CECTRL => '1', -- 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
558  CED => '1', -- 1-bit input: Clock enable input for DREG
559  CEM => '1', -- 1-bit input: Clock enable input for MREG
560  CEP => '1', -- 1-bit input: Clock enable input for PREG
561  RSTA => '0', -- 1-bit input: Reset input for AREG
562  RSTALLCARRYIN => '0', -- 1-bit input: Reset input for CARRYINREG
563  RSTALUMODE => '0', -- 1-bit input: Reset input for ALUMODEREG
564  RSTB => '0', -- 1-bit input: Reset input for BREG
565  RSTC => '0', -- 1-bit input: Reset input for CREG
566  RSTCTRL => '0', -- 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
567  RSTD => '0', -- 1-bit input: Reset input for DREG and ADREG
568  RSTM => '0', -- 1-bit input: Reset input for MREG
569  RSTP => '0' -- 1-bit input: Reset input for PREG
570  );
571 
572 process(UsrClk,RxResetDone)
573 begin
574  if(RxResetDone = '0')then
575  RxResetDoneSyncRegs <= (others => '0');
576  elsif(UsrClk'event and UsrClk = '1')then
577  RxResetDoneSyncRegs <= RxResetDoneSyncRegs(1 downto 0) & '1';
578  end if;
579 end process;
580 process(UsrClk,reset,RxResetDone,txfsmresetdone,cplllock)
581 begin
582  if(reset = '1' or RXRESETDONE = '0' or txfsmresetdone = '0' or cplllock = '0')then
583  reset_SyncRegs <= (others => '1');
584  elsif(UsrClk'event and UsrClk = '1')then
585  reset_SyncRegs <= reset_SyncRegs(2 downto 0) & '0';
586  end if;
587 end process;
588 process(UsrClk)
589 begin
590  if(UsrClk'event and UsrClk = '1')then
591  if(RXCHARISK = "11" and RXDATA = x"3cbc")then
592  DATA_VALID <= '1';
593  elsif(RxResetDoneSyncRegs(2) = '0' or or_reduce(RXNOTINTABLE) = '1' or K_Cntr(7) = '1')then
594  DATA_VALID <= '0';
595  end if;
596  if((RXCHARISK = "11" and RXDATA = x"3cbc"))then
597  K_Cntr <= (others => '0');
598  else
599  K_Cntr <= K_Cntr + 1;
600  end if;
601  end if;
602 end process;
603 i_DAQLINK_7S_init : DAQLINK_7S_init
604  generic map
605  (
606  EXAMPLE_SIM_GTRESET_SPEEDUP => GTXRESET_SPEEDUP(simulation),
607  EXAMPLE_SIMULATION => 0,
608  STABLE_CLOCK_PERIOD => DRPclk_period,
609  EXAMPLE_USE_CHIPSCOPE => 0,
610  F_REFCLK => F_REFCLK
611  )
612  port map
613  (
614  SYSCLK_IN => DRPclk,
615  SOFT_RESET_IN => '0',
616  DONT_RESET_ON_DATA_ERROR_IN => '0',
617  GT0_TX_FSM_RESET_DONE_OUT => txfsmresetdone,
618  GT0_RX_FSM_RESET_DONE_OUT => open,
619  GT0_DATA_VALID_IN => DATA_VALID,
620 
621 
622 
623 
624 
625  --_____________________________________________________________________
626  --_____________________________________________________________________
627  --GT0 (X1Y0)
628 
629  --------------------------------- CPLL Ports -------------------------------
630  GT0_CPLLFBCLKLOST_OUT => open,
631  GT0_CPLLLOCK_OUT => cplllock,
632  GT0_CPLLLOCKDETCLK_IN => DRPclk,
633  GT0_CPLLRESET_IN => reset,
634  -------------------------- Channel - Clocking Ports ------------------------
635  GT0_GTREFCLK0_IN => AMC_REFCLK,
636  ---------------------------- Channel - DRP Ports --------------------------
637  GT0_DRPADDR_IN => (others => '0'),
638  GT0_DRPCLK_IN => DRPclk,
639  GT0_DRPDI_IN => (others => '0'),
640  GT0_DRPDO_OUT => open,
641  GT0_DRPEN_IN => '0',
642  GT0_DRPRDY_OUT => open,
643  GT0_DRPWE_IN => '0',
644  ------------------------------- Loopback Ports -----------------------------
645  GT0_LOOPBACK_IN => LOOPBACK,
646  --------------------- RX Initialization and Reset Ports --------------------
647  GT0_RXUSERRDY_IN => '0',
648  -------------------------- RX Margin Analysis Ports ------------------------
649  GT0_EYESCANDATAERROR_OUT => open,
650  ------------------------- Receive Ports - CDR Ports ------------------------
651  GT0_RXCDRLOCK_OUT => open,
652  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
653  GT0_RXUSRCLK_IN => UsRClk,
654  GT0_RXUSRCLK2_IN => UsRClk,
655  ------------------ Receive Ports - FPGA RX interface Ports -----------------
656  GT0_RXDATA_OUT => RXDATA,
657  ------------------- Receive Ports - Pattern Checker Ports ------------------
658  GT0_RXPRBSERR_OUT => open,
659  GT0_RXPRBSSEL_IN => (others => '0'),
660  ------------------- Receive Ports - Pattern Checker ports ------------------
661  GT0_RXPRBSCNTRESET_IN => '0',
662  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
663  GT0_RXDISPERR_OUT => open,
664  GT0_RXNOTINTABLE_OUT => RXNOTINTABLE,
665  --------------------------- Receive Ports - RX AFE -------------------------
666  GT0_GTXRXP_IN => AMC_RXP,
667  ------------------------ Receive Ports - RX AFE Ports ----------------------
668  GT0_GTXRXN_IN => AMC_RXN,
669  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
670  GT0_RXMCOMMAALIGNEN_IN => reset_SyncRegs(3),
671  GT0_RXPCOMMAALIGNEN_IN => reset_SyncRegs(3),
672  ------------- Receive Ports - RX Initialization and Reset Ports ------------
673  GT0_GTRXRESET_IN => reset,
674  GT0_RXPMARESET_IN => '0',
675  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
676  GT0_RXCHARISCOMMA_OUT => RXCHARISCOMMA,
677  GT0_RXCHARISK_OUT => RXCHARISK,
678  -------------- Receive Ports -RX Initialization and Reset Ports ------------
679  GT0_RXRESETDONE_OUT => RXRESETDONE,
680  --------------------- TX Initialization and Reset Ports --------------------
681  GT0_GTTXRESET_IN => reset,
682  GT0_TXUSERRDY_IN => '0',
683  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
684  GT0_TXUSRCLK_IN => UsRClk,
685  GT0_TXUSRCLK2_IN => UsRClk,
686  --------------- Transmit Ports - TX Configurable Driver Ports --------------
687  GT0_TXDIFFCTRL_IN => TXDIFFCTRL,
688  ------------------ Transmit Ports - TX Data Path interface -----------------
689  GT0_TXDATA_IN => TXDATA,
690  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
691  GT0_GTXTXN_OUT => AMC_TXN,
692  GT0_GTXTXP_OUT => AMC_TXP,
693  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
694  GT0_TXOUTCLK_OUT => TXOUTCLK,
695  GT0_TXOUTCLKFABRIC_OUT => open,
696  GT0_TXOUTCLKPCS_OUT => open,
697  --------------------- Transmit Ports - TX Gearbox Ports --------------------
698  GT0_TXCHARISK_IN => TXCHARISK,
699  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
700  GT0_TXRESETDONE_OUT => open,
701  ------------------ Transmit Ports - pattern Generator Ports ----------------
702  GT0_TXPRBSSEL_IN => "000",
703 
704 
705 
706 
707  --____________________________COMMON PORTS________________________________
708  ---------------------- Common Block - Ref Clock Ports ---------------------
709  GT0_GTREFCLK0_COMMON_IN => '0',
710  ------------------------- Common Block - QPLL Ports ------------------------
711  GT0_QPLLLOCK_OUT => open,
712  GT0_QPLLLOCKDETCLK_IN => '0',
713  GT0_QPLLRESET_IN => '0'
714 
715  );
716 i_UsrClk : BUFG
717  port map (
718  O => UsrClk, -- Clock buffer output
719  I => TXOUTCLK -- Clock buffer input
720  );
721 end Behavioral;
722 
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