RTL Architecture Reference

List of all members.

Functions
integer	CPLL_FBDIV ( F_REFCLK: in integer )
integer	CPLL_REFCLK_DIV ( F_REFCLK: in integer )

Signals
tied_to_ground_i	std_logic
tied_to_ground_vec_i	std_logic_vector ( 63 downto 0 )
tied_to_vcc_i	std_logic
rxdata_i	std_logic_vector ( 63 downto 0 )
rxchariscomma_float_i	std_logic_vector ( 5 downto 0 )
rxcharisk_float_i	std_logic_vector ( 5 downto 0 )
rxdisperr_float_i	std_logic_vector ( 5 downto 0 )
rxnotintable_float_i	std_logic_vector ( 5 downto 0 )
rxrundisp_float_i	std_logic_vector ( 5 downto 0 )
txdata_i	std_logic_vector ( 63 downto 0 )
txkerr_float_i	std_logic_vector ( 5 downto 0 )
txrundisp_float_i	std_logic_vector ( 5 downto 0 )
rxstartofseq_float_i	std_logic

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Detailed Description

Definition at line 178 of file daqlink_7s_gt.vhd.

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The documentation for this class was generated from the following file:

• src/AMC_DAQ_LINK/daqlink_7s_gt.vhd