AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
 All Classes Variables
daqlink_7s_gt.vhd
1 -------------------------------------------------------------------------------
2 -- ____ ____
3 -- / /\/ /
4 -- /___/ \ / Vendor: Xilinx
5 -- \ \ \/ Version : 2.7
6 -- \ \ Application : 7 Series FPGAs Transceivers Wizard
7 -- / / Filename : daqlink_7s_gt.vhd
8 -- /___/ /\
9 -- \ \ / \
10 -- \___\/\___\
11 --
12 --
13 -- Module DAQLINK_7S_GT (a GT Wrapper)
14 -- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
15 --
16 --
17 -- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
18 --
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62 
63 
64 library ieee;
65 use ieee.std_logic_1164.all;
66 use ieee.numeric_std.all;
67 library UNISIM;
68 use UNISIM.VCOMPONENTS.ALL;
69 
70 --***************************** Entity Declaration ****************************
71 
72 entity DAQLINK_7S_GT is
73 generic
74 (
75 -- REFCLK frequency, select one among 100, 125, 200 and 250
76 -- If your REFCLK frequency is not in the list, please contact wusx@bu.edu
77  F_REFCLK : integer := 100;
78  -- Simulation attributes
79  GT_SIM_GTRESET_SPEEDUP : string := "FALSE"; -- Set to "true" to speed up sim reset
80  RX_DFE_KL_CFG2_IN : bit_vector := X"301148AC";
81  PMA_RSV_IN : bit_vector := x"00018480";
82  PCS_RSVD_ATTR_IN : bit_vector := X"000000000000"
83 );
84 port
85 (
86  --------------------------------- CPLL Ports -------------------------------
87  CPLLFBCLKLOST_OUT : out std_logic;
88  CPLLLOCK_OUT : out std_logic;
89  CPLLLOCKDETCLK_IN : in std_logic;
90  CPLLREFCLKLOST_OUT : out std_logic;
91  CPLLRESET_IN : in std_logic;
92  -------------------------- Channel - Clocking Ports ------------------------
93  GTREFCLK0_IN : in std_logic;
94  ---------------------------- Channel - DRP Ports --------------------------
95  DRPADDR_IN : in std_logic_vector(8 downto 0);
96  DRPCLK_IN : in std_logic;
97  DRPDI_IN : in std_logic_vector(15 downto 0);
98  DRPDO_OUT : out std_logic_vector(15 downto 0);
99  DRPEN_IN : in std_logic;
100  DRPRDY_OUT : out std_logic;
101  DRPWE_IN : in std_logic;
102  ------------------------------- Clocking Ports -----------------------------
103  QPLLCLK_IN : in std_logic;
104  QPLLREFCLK_IN : in std_logic;
105  ------------------------------- Loopback Ports -----------------------------
106  LOOPBACK_IN : in std_logic_vector(2 downto 0);
107  --------------------- RX Initialization and Reset Ports --------------------
108  RXUSERRDY_IN : in std_logic;
109  -------------------------- RX Margin Analysis Ports ------------------------
110  EYESCANDATAERROR_OUT : out std_logic;
111  ------------------------- Receive Ports - CDR Ports ------------------------
112  RXCDRLOCK_OUT : out std_logic;
113  ------------------- Receive Ports - Clock Correction Ports -----------------
114  RXCLKCORCNT_OUT : out std_logic_vector(1 downto 0);
115  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
116  RXUSRCLK_IN : in std_logic;
117  RXUSRCLK2_IN : in std_logic;
118  ------------------ Receive Ports - FPGA RX interface Ports -----------------
119  RXDATA_OUT : out std_logic_vector(15 downto 0);
120  ------------------- Receive Ports - Pattern Checker Ports ------------------
121  RXPRBSERR_OUT : out std_logic;
122  RXPRBSSEL_IN : in std_logic_vector(2 downto 0);
123  ------------------- Receive Ports - Pattern Checker ports ------------------
124  RXPRBSCNTRESET_IN : in std_logic;
125  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
126  RXDISPERR_OUT : out std_logic_vector(1 downto 0);
127  RXNOTINTABLE_OUT : out std_logic_vector(1 downto 0);
128  --------------------------- Receive Ports - RX AFE -------------------------
129  GTXRXP_IN : in std_logic;
130  ------------------------ Receive Ports - RX AFE Ports ----------------------
131  GTXRXN_IN : in std_logic;
132  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
133  RXMCOMMAALIGNEN_IN : in std_logic;
134  RXPCOMMAALIGNEN_IN : in std_logic;
135  -------------------- Receive Ports - RX Equailizer Ports -------------------
136  RXLPMHFHOLD_IN : in std_logic;
137  RXLPMLFHOLD_IN : in std_logic;
138  --------------- Receive Ports - RX Fabric Output Control Ports -------------
139  RXOUTCLK_OUT : out std_logic;
140  ------------- Receive Ports - RX Initialization and Reset Ports ------------
141  GTRXRESET_IN : in std_logic;
142  RXPMARESET_IN : in std_logic;
143  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
144  RXCHARISCOMMA_OUT : out std_logic_vector(1 downto 0);
145  RXCHARISK_OUT : out std_logic_vector(1 downto 0);
146  -------------- Receive Ports -RX Initialization and Reset Ports ------------
147  RXRESETDONE_OUT : out std_logic;
148  --------------------- TX Initialization and Reset Ports --------------------
149  GTTXRESET_IN : in std_logic;
150  TXUSERRDY_IN : in std_logic;
151  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
152  TXUSRCLK_IN : in std_logic;
153  TXUSRCLK2_IN : in std_logic;
154  --------------- Transmit Ports - TX Configurable Driver Ports --------------
155  TXDIFFCTRL_IN : in std_logic_vector(3 downto 0);
156  ------------------ Transmit Ports - TX Data Path interface -----------------
157  TXDATA_IN : in std_logic_vector(15 downto 0);
158  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
159  GTXTXN_OUT : out std_logic;
160  GTXTXP_OUT : out std_logic;
161  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
162  TXOUTCLK_OUT : out std_logic;
163  TXOUTCLKFABRIC_OUT : out std_logic;
164  TXOUTCLKPCS_OUT : out std_logic;
165  --------------------- Transmit Ports - TX Gearbox Ports --------------------
166  TXCHARISK_IN : in std_logic_vector(1 downto 0);
167  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
168  TXRESETDONE_OUT : out std_logic;
169  ------------------ Transmit Ports - pattern Generator Ports ----------------
170  TXPRBSSEL_IN : in std_logic_vector(2 downto 0)
171 
172 
173 );
174 
175 
176 end DAQLINK_7S_GT;
177 
178 architecture RTL of DAQLINK_7S_GT is
179 function CPLL_FBDIV(F_REFCLK : integer) return integer is
180 begin
181  if(F_REFCLK = 125)then
182  return 4;
183  elsif(F_REFCLK = 250)then
184  return 2;
185  else
186  return 5;
187  end if;
188 end function;
189 function CPLL_REFCLK_DIV(F_REFCLK : integer) return integer is
190 begin
191  if(F_REFCLK = 200)then
192  return 2;
193  else
194  return 1;
195  end if;
196 end function;
197 
198 --**************************** Signal Declarations ****************************
199 
200  -- ground and tied_to_vcc_i signals
201  signal tied_to_ground_i : std_logic;
202  signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
203  signal tied_to_vcc_i : std_logic;
204 
205 
206 
207  -- RX Datapath signals
208  signal rxdata_i : std_logic_vector(63 downto 0);
209  signal rxchariscomma_float_i : std_logic_vector(5 downto 0);
210  signal rxcharisk_float_i : std_logic_vector(5 downto 0);
211  signal rxdisperr_float_i : std_logic_vector(5 downto 0);
212  signal rxnotintable_float_i : std_logic_vector(5 downto 0);
213  signal rxrundisp_float_i : std_logic_vector(5 downto 0);
214 
215 
216 
217  -- TX Datapath signals
218  signal txdata_i : std_logic_vector(63 downto 0);
219  signal txkerr_float_i : std_logic_vector(5 downto 0);
220  signal txrundisp_float_i : std_logic_vector(5 downto 0);
221  signal rxstartofseq_float_i : std_logic;
222 
223 --******************************** Main Body of Code***************************
224 
225 begin
226 
227  --------------------------- Static signal Assignments ---------------------
228 
229  tied_to_ground_i <= '0';
230  tied_to_ground_vec_i(63 downto 0) <= (others => '0');
231  tied_to_vcc_i <= '1';
232 
233  ------------------- GT Datapath byte mapping -----------------
234 
235  RXDATA_OUT <= rxdata_i(15 downto 0);
236 
237  txdata_i <= (tied_to_ground_vec_i(47 downto 0) & TXDATA_IN);
238 
239 
240 
241  ----------------------------- GTXE2 Instance --------------------------
242 
243  gtxe2_i :GTXE2_CHANNEL
244  generic map
245  (
246 
247  --_______________________ Simulation-Only Attributes ___________________
248 
249  SIM_RECEIVER_DETECT_PASS => ("TRUE"),
250  SIM_RESET_SPEEDUP => (GT_SIM_GTRESET_SPEEDUP),
251  SIM_TX_EIDLE_DRIVE_LEVEL => ("X"),
252  SIM_CPLLREFCLK_SEL => ("001"),
253  SIM_VERSION => ("4.0"),
254 
255 
256  ------------------RX Byte and Word Alignment Attributes---------------
257  ALIGN_COMMA_DOUBLE => ("FALSE"),
258  ALIGN_COMMA_ENABLE => ("1111111111"),
259  ALIGN_COMMA_WORD => (2),
260  ALIGN_MCOMMA_DET => ("TRUE"),
261  ALIGN_MCOMMA_VALUE => ("1010000011"),
262  ALIGN_PCOMMA_DET => ("TRUE"),
263  ALIGN_PCOMMA_VALUE => ("0101111100"),
264  SHOW_REALIGN_COMMA => ("TRUE"),
265  RXSLIDE_AUTO_WAIT => (7),
266  RXSLIDE_MODE => ("OFF"),
267  RX_SIG_VALID_DLY => (10),
268 
269  ------------------RX 8B/10B Decoder Attributes---------------
270  RX_DISPERR_SEQ_MATCH => ("TRUE"),
271  DEC_MCOMMA_DETECT => ("TRUE"),
272  DEC_PCOMMA_DETECT => ("TRUE"),
273  DEC_VALID_COMMA_ONLY => ("TRUE"),
274 
275  ------------------------RX Clock Correction Attributes----------------------
276  CBCC_DATA_SOURCE_SEL => ("DECODED"),
277  CLK_COR_SEQ_2_USE => ("FALSE"),
278  CLK_COR_KEEP_IDLE => ("FALSE"),
279  CLK_COR_MAX_LAT => (15),
280  CLK_COR_MIN_LAT => (12),
281  CLK_COR_PRECEDENCE => ("TRUE"),
282  CLK_COR_REPEAT_WAIT => (0),
283  CLK_COR_SEQ_LEN => (2),
284  CLK_COR_SEQ_1_ENABLE => ("1111"),
285  CLK_COR_SEQ_1_1 => ("0111111011"),
286  CLK_COR_SEQ_1_2 => ("0111011100"),
287  CLK_COR_SEQ_1_3 => ("0000000000"),
288  CLK_COR_SEQ_1_4 => ("0000000000"),
289  CLK_CORRECT_USE => ("TRUE"),
290  CLK_COR_SEQ_2_ENABLE => ("1111"),
291  CLK_COR_SEQ_2_1 => ("0000000000"),
292  CLK_COR_SEQ_2_2 => ("0000000000"),
293  CLK_COR_SEQ_2_3 => ("0000000000"),
294  CLK_COR_SEQ_2_4 => ("0000000000"),
295 
296  ------------------------RX Channel Bonding Attributes----------------------
297  CHAN_BOND_KEEP_ALIGN => ("FALSE"),
298  CHAN_BOND_MAX_SKEW => (1),
299  CHAN_BOND_SEQ_LEN => (1),
300  CHAN_BOND_SEQ_1_1 => ("0000000000"),
301  CHAN_BOND_SEQ_1_2 => ("0000000000"),
302  CHAN_BOND_SEQ_1_3 => ("0000000000"),
303  CHAN_BOND_SEQ_1_4 => ("0000000000"),
304  CHAN_BOND_SEQ_1_ENABLE => ("1111"),
305  CHAN_BOND_SEQ_2_1 => ("0000000000"),
306  CHAN_BOND_SEQ_2_2 => ("0000000000"),
307  CHAN_BOND_SEQ_2_3 => ("0000000000"),
308  CHAN_BOND_SEQ_2_4 => ("0000000000"),
309  CHAN_BOND_SEQ_2_ENABLE => ("1111"),
310  CHAN_BOND_SEQ_2_USE => ("FALSE"),
311  FTS_DESKEW_SEQ_ENABLE => ("1111"),
312  FTS_LANE_DESKEW_CFG => ("1111"),
313  FTS_LANE_DESKEW_EN => ("FALSE"),
314 
315  ---------------------------RX Margin Analysis Attributes----------------------------
316  ES_CONTROL => ("000000"),
317  ES_ERRDET_EN => ("FALSE"),
318  ES_EYE_SCAN_EN => ("TRUE"),
319  ES_HORZ_OFFSET => (x"000"),
320  ES_PMA_CFG => ("0000000000"),
321  ES_PRESCALE => ("00000"),
322  ES_QUALIFIER => (x"00000000000000000000"),
323  ES_QUAL_MASK => (x"00000000000000000000"),
324  ES_SDATA_MASK => (x"00000000000000000000"),
325  ES_VERT_OFFSET => ("000000000"),
326 
327  -------------------------FPGA RX Interface Attributes-------------------------
328  RX_DATA_WIDTH => (20),
329 
330  ---------------------------PMA Attributes----------------------------
331  OUTREFCLK_SEL_INV => ("11"),
332  PMA_RSV => (PMA_RSV_IN),
333  PMA_RSV2 => (x"2040"),
334  PMA_RSV3 => ("00"),
335  PMA_RSV4 => (x"00000000"),
336  RX_BIAS_CFG => ("000000000100"),
337  DMONITOR_CFG => (x"000A00"),
338  RX_CM_SEL => ("00"),
339  RX_CM_TRIM => ("000"),
340  RX_DEBUG_CFG => ("000000000000"),
341  RX_OS_CFG => ("0000010000000"),
342  TERM_RCAL_CFG => ("10000"),
343  TERM_RCAL_OVRD => ('0'),
344  TST_RSV => (x"00000000"),
345  RX_CLK25_DIV => (F_REFCLK/25),
346  TX_CLK25_DIV => (F_REFCLK/25),
347  UCODEER_CLR => ('0'),
348 
349  ---------------------------PCI Express Attributes----------------------------
350  PCS_PCIE_EN => ("FALSE"),
351 
352  ---------------------------PCS Attributes----------------------------
353  PCS_RSVD_ATTR => (PCS_RSVD_ATTR_IN),
354 
355  -------------RX Buffer Attributes------------
356  RXBUF_ADDR_MODE => ("FULL"),
357  RXBUF_EIDLE_HI_CNT => ("1000"),
358  RXBUF_EIDLE_LO_CNT => ("0000"),
359  RXBUF_EN => ("TRUE"),
360  RX_BUFFER_CFG => ("000000"),
361  RXBUF_RESET_ON_CB_CHANGE => ("TRUE"),
362  RXBUF_RESET_ON_COMMAALIGN => ("FALSE"),
363  RXBUF_RESET_ON_EIDLE => ("FALSE"),
364  RXBUF_RESET_ON_RATE_CHANGE => ("TRUE"),
365  RXBUFRESET_TIME => ("00001"),
366  RXBUF_THRESH_OVFLW => (61),
367  RXBUF_THRESH_OVRD => ("FALSE"),
368  RXBUF_THRESH_UNDFLW => (4),
369  RXDLY_CFG => (x"001F"),
370  RXDLY_LCFG => (x"030"),
371  RXDLY_TAP_CFG => (x"0000"),
372  RXPH_CFG => (x"000000"),
373  RXPHDLY_CFG => (x"084020"),
374  RXPH_MONITOR_SEL => ("00000"),
375  RX_XCLK_SEL => ("RXREC"),
376  RX_DDI_SEL => ("000000"),
377  RX_DEFER_RESET_BUF_EN => ("TRUE"),
378 
379  -----------------------CDR Attributes-------------------------
380 
381  --For GTX only: Display Port, HBR/RBR- set RXCDR_CFG=72'h0380008bff40200008
382 
383  --For GTX only: Display Port, HBR2 - set RXCDR_CFG=72'h038C008bff20200010
384  RXCDR_CFG => (x"03000023ff10400020"),
385  RXCDR_FR_RESET_ON_EIDLE => ('0'),
386  RXCDR_HOLD_DURING_EIDLE => ('0'),
387  RXCDR_PH_RESET_ON_EIDLE => ('0'),
388  RXCDR_LOCK_CFG => ("010101"),
389 
390  -------------------RX Initialization and Reset Attributes-------------------
391  RXCDRFREQRESET_TIME => ("00001"),
392  RXCDRPHRESET_TIME => ("00001"),
393  RXISCANRESET_TIME => ("00001"),
394  RXPCSRESET_TIME => ("00001"),
395  RXPMARESET_TIME => ("00011"),
396 
397  -------------------RX OOB Signaling Attributes-------------------
398  RXOOB_CFG => ("0000110"),
399 
400  -------------------------RX Gearbox Attributes---------------------------
401  RXGEARBOX_EN => ("FALSE"),
402  GEARBOX_MODE => ("000"),
403 
404  -------------------------PRBS Detection Attribute-----------------------
405  RXPRBS_ERR_LOOPBACK => ('0'),
406 
407  -------------Power-Down Attributes----------
408  PD_TRANS_TIME_FROM_P2 => (x"03c"),
409  PD_TRANS_TIME_NONE_P2 => (x"3c"),
410  PD_TRANS_TIME_TO_P2 => (x"64"),
411 
412  -------------RX OOB Signaling Attributes----------
413  SAS_MAX_COM => (64),
414  SAS_MIN_COM => (36),
415  SATA_BURST_SEQ_LEN => ("1111"),
416  SATA_BURST_VAL => ("100"),
417  SATA_EIDLE_VAL => ("100"),
418  SATA_MAX_BURST => (8),
419  SATA_MAX_INIT => (21),
420  SATA_MAX_WAKE => (7),
421  SATA_MIN_BURST => (4),
422  SATA_MIN_INIT => (12),
423  SATA_MIN_WAKE => (4),
424 
425  -------------RX Fabric Clock Output Control Attributes----------
426  TRANS_TIME_RATE => (x"0E"),
427 
428  --------------TX Buffer Attributes----------------
429  TXBUF_EN => ("TRUE"),
430  TXBUF_RESET_ON_RATE_CHANGE => ("TRUE"),
431  TXDLY_CFG => (x"001F"),
432  TXDLY_LCFG => (x"030"),
433  TXDLY_TAP_CFG => (x"0000"),
434  TXPH_CFG => (x"0780"),
435  TXPHDLY_CFG => (x"084020"),
436  TXPH_MONITOR_SEL => ("00000"),
437  TX_XCLK_SEL => ("TXOUT"),
438 
439  -------------------------FPGA TX Interface Attributes-------------------------
440  TX_DATA_WIDTH => (20),
441 
442  -------------------------TX Configurable Driver Attributes-------------------------
443  TX_DEEMPH0 => ("00000"),
444  TX_DEEMPH1 => ("00000"),
445  TX_EIDLE_ASSERT_DELAY => ("110"),
446  TX_EIDLE_DEASSERT_DELAY => ("100"),
447  TX_LOOPBACK_DRIVE_HIZ => ("FALSE"),
448  TX_MAINCURSOR_SEL => ('0'),
449  TX_DRIVE_MODE => ("DIRECT"),
450  TX_MARGIN_FULL_0 => ("1001110"),
451  TX_MARGIN_FULL_1 => ("1001001"),
452  TX_MARGIN_FULL_2 => ("1000101"),
453  TX_MARGIN_FULL_3 => ("1000010"),
454  TX_MARGIN_FULL_4 => ("1000000"),
455  TX_MARGIN_LOW_0 => ("1000110"),
456  TX_MARGIN_LOW_1 => ("1000100"),
457  TX_MARGIN_LOW_2 => ("1000010"),
458  TX_MARGIN_LOW_3 => ("1000000"),
459  TX_MARGIN_LOW_4 => ("1000000"),
460 
461  -------------------------TX Gearbox Attributes--------------------------
462  TXGEARBOX_EN => ("FALSE"),
463 
464  -------------------------TX Initialization and Reset Attributes--------------------------
465  TXPCSRESET_TIME => ("00001"),
466  TXPMARESET_TIME => ("00001"),
467 
468  -------------------------TX Receiver Detection Attributes--------------------------
469  TX_RXDETECT_CFG => (x"1832"),
470  TX_RXDETECT_REF => ("100"),
471 
472  ----------------------------CPLL Attributes----------------------------
473  CPLL_CFG => (x"BC07DC"),
474  CPLL_FBDIV => (CPLL_FBDIV(F_REFCLK)),
475  CPLL_FBDIV_45 => (5),
476  CPLL_INIT_CFG => (x"00001E"),
477  CPLL_LOCK_CFG => (x"01E8"),
478  CPLL_REFCLK_DIV => (CPLL_REFCLK_DIV(F_REFCLK)),
479  RXOUT_DIV => (1),
480  TXOUT_DIV => (1),
481  SATA_CPLL_CFG => ("VCO_3000MHZ"),
482 
483  --------------RX Initialization and Reset Attributes-------------
484  RXDFELPMRESET_TIME => ("0001111"),
485 
486  --------------RX Equalizer Attributes-------------
487  RXLPM_HF_CFG => ("00000011110000"),
488  RXLPM_LF_CFG => ("00000011110000"),
489  RX_DFE_GAIN_CFG => (x"020FEA"),
490  RX_DFE_H2_CFG => ("000000000000"),
491  RX_DFE_H3_CFG => ("000001000000"),
492  RX_DFE_H4_CFG => ("00011110000"),
493  RX_DFE_H5_CFG => ("00011100000"),
494  RX_DFE_KL_CFG => ("0000011111110"),
495  RX_DFE_LPM_CFG => (x"0904"),
496  RX_DFE_LPM_HOLD_DURING_EIDLE => ('0'),
497  RX_DFE_UT_CFG => ("10001111000000000"),
498  RX_DFE_VP_CFG => ("00011111100000011"),
499 
500  -------------------------Power-Down Attributes-------------------------
501  RX_CLKMUX_PD => ('1'),
502  TX_CLKMUX_PD => ('1'),
503 
504  -------------------------FPGA RX Interface Attribute-------------------------
505  RX_INT_DATAWIDTH => (0),
506 
507  -------------------------FPGA TX Interface Attribute-------------------------
508  TX_INT_DATAWIDTH => (0),
509 
510  ------------------TX Configurable Driver Attributes---------------
511  TX_QPI_STATUS_EN => ('0'),
512 
513  -------------------------RX Equalizer Attributes--------------------------
514  RX_DFE_KL_CFG2 => (RX_DFE_KL_CFG2_IN),
515  RX_DFE_XYD_CFG => ("0000000000000"),
516 
517  -------------------------TX Configurable Driver Attributes--------------------------
518  TX_PREDRIVER_MODE => ('0')
519 
520 
521  )
522  port map
523  (
524  --------------------------------- CPLL Ports -------------------------------
525  CPLLFBCLKLOST => CPLLFBCLKLOST_OUT,
526  CPLLLOCK => CPLLLOCK_OUT,
527  CPLLLOCKDETCLK => CPLLLOCKDETCLK_IN,
528  CPLLLOCKEN => tied_to_vcc_i,
529  CPLLPD => tied_to_ground_i,
530  CPLLREFCLKLOST => CPLLREFCLKLOST_OUT,
531  CPLLREFCLKSEL => "001",
532  CPLLRESET => CPLLRESET_IN,
533  GTRSVD => "0000000000000000",
534  PCSRSVDIN => "0000000000000000",
535  PCSRSVDIN2 => "00000",
536  PMARSVDIN => "00000",
537  PMARSVDIN2 => "00000",
538  TSTIN => "11111111111111111111" ,
539  TSTOUT => open,
540  ---------------------------------- Channel ---------------------------------
541  CLKRSVD => "0000",
542  -------------------------- Channel - Clocking Ports ------------------------
543  GTGREFCLK => tied_to_ground_i,
544  GTNORTHREFCLK0 => tied_to_ground_i,
545  GTNORTHREFCLK1 => tied_to_ground_i,
546  GTREFCLK0 => GTREFCLK0_IN,
547  GTREFCLK1 => tied_to_ground_i,
548  GTSOUTHREFCLK0 => tied_to_ground_i,
549  GTSOUTHREFCLK1 => tied_to_ground_i,
550  ---------------------------- Channel - DRP Ports --------------------------
551  DRPADDR => DRPADDR_IN,
552  DRPCLK => DRPCLK_IN ,
553  DRPDI => DRPDI_IN,
554  DRPDO => DRPDO_OUT ,
555  DRPEN => DRPEN_IN,
556  DRPRDY => DRPRDY_OUT,
557  DRPWE => DRPWE_IN,
558  ------------------------------- Clocking Ports -----------------------------
559  GTREFCLKMONITOR => open,
560  QPLLCLK => QPLLCLK_IN,
561  QPLLREFCLK => QPLLREFCLK_IN,
562  RXSYSCLKSEL => "00",
563  TXSYSCLKSEL => "00",
564  --------------------------- Digital Monitor Ports --------------------------
565  DMONITOROUT => open,
566  ----------------- FPGA TX Interface Datapath Configuration ----------------
567  TX8B10BEN => tied_to_vcc_i,
568  ------------------------------- Loopback Ports -----------------------------
569  LOOPBACK => LOOPBACK_IN,
570  ----------------------------- PCI Express Ports ----------------------------
571  PHYSTATUS => open,
572  RXRATE => tied_to_ground_vec_i (2 downto 0),
573  RXVALID => open,
574  ------------------------------ Power-Down Ports ----------------------------
575  RXPD => "00",
576  TXPD => "00",
577  -------------------------- RX 8B/10B Decoder Ports -------------------------
578  SETERRSTATUS => tied_to_ground_i,
579  --------------------- RX Initialization and Reset Ports --------------------
580  EYESCANRESET => tied_to_ground_i,
581  RXUSERRDY => RXUSERRDY_IN,
582  -------------------------- RX Margin Analysis Ports ------------------------
583  EYESCANDATAERROR => EYESCANDATAERROR_OUT ,
584  EYESCANMODE => tied_to_ground_i,
585  EYESCANTRIGGER => tied_to_ground_i,
586  ------------------------- Receive Ports - CDR Ports ------------------------
587  RXCDRFREQRESET => tied_to_ground_i,
588  RXCDRHOLD => tied_to_ground_i,
589  RXCDRLOCK => RXCDRLOCK_OUT,
590  RXCDROVRDEN => tied_to_ground_i,
591  RXCDRRESET => tied_to_ground_i,
592  RXCDRRESETRSV => tied_to_ground_i,
593  ------------------- Receive Ports - Clock Correction Ports -----------------
594  RXCLKCORCNT => RXCLKCORCNT_OUT,
595  ---------- Receive Ports - FPGA RX Interface Datapath Configuration --------
596  RX8B10BEN => tied_to_vcc_i,
597  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
598  RXUSRCLK => RXUSRCLK_IN,
599  RXUSRCLK2 => RXUSRCLK2_IN,
600  ------------------ Receive Ports - FPGA RX interface Ports -----------------
601  RXDATA => rxdata_i,
602  ------------------- Receive Ports - Pattern Checker Ports ------------------
603  RXPRBSERR => RXPRBSERR_OUT,
604  RXPRBSSEL => RXPRBSSEL_IN,
605  ------------------- Receive Ports - Pattern Checker ports ------------------
606  RXPRBSCNTRESET => RXPRBSCNTRESET_IN,
607  -------------------- Receive Ports - RX Equalizer Ports -------------------
608  RXDFEXYDEN => tied_to_vcc_i,
609  RXDFEXYDHOLD => tied_to_ground_i,
610  RXDFEXYDOVRDEN => tied_to_ground_i,
611  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
612  RXDISPERR(7 downto 2) => rxdisperr_float_i,
613  RXDISPERR(1 downto 0) => RXDISPERR_OUT,
614  RXNOTINTABLE(7 downto 2) => rxnotintable_float_i,
615  RXNOTINTABLE(1 downto 0) => RXNOTINTABLE_OUT,
616  --------------------------- Receive Ports - RX AFE -------------------------
617  GTXRXP => GTXRXP_IN ,
618  ------------------------ Receive Ports - RX AFE Ports ----------------------
619  GTXRXN => GTXRXN_IN ,
620  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
621  RXBUFRESET => tied_to_ground_i,
622  RXBUFSTATUS => open,
623  RXDDIEN => tied_to_ground_i,
624  RXDLYBYPASS => tied_to_vcc_i,
625  RXDLYEN => tied_to_ground_i,
626  RXDLYOVRDEN => tied_to_ground_i,
627  RXDLYSRESET => tied_to_ground_i,
628  RXDLYSRESETDONE => open,
629  RXPHALIGN => tied_to_ground_i,
630  RXPHALIGNDONE => open,
631  RXPHALIGNEN => tied_to_ground_i,
632  RXPHDLYPD => tied_to_ground_i,
633  RXPHDLYRESET => tied_to_ground_i,
634  RXPHMONITOR => open,
635  RXPHOVRDEN => tied_to_ground_i,
636  RXPHSLIPMONITOR => open,
637  RXSTATUS => open,
638  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
639  RXBYTEISALIGNED => open,
640  RXBYTEREALIGN => open,
641  RXCOMMADET => open,
642  RXCOMMADETEN => tied_to_vcc_i,
643  RXMCOMMAALIGNEN => RXMCOMMAALIGNEN_IN,
644  RXPCOMMAALIGNEN => RXPCOMMAALIGNEN_IN,
645  ------------------ Receive Ports - RX Channel Bonding Ports ----------------
646  RXCHANBONDSEQ => open,
647  RXCHBONDEN => tied_to_ground_i,
648  RXCHBONDLEVEL => tied_to_ground_vec_i (2 downto 0),
649  RXCHBONDMASTER => tied_to_ground_i,
650  RXCHBONDO => open,
651  RXCHBONDSLAVE => tied_to_ground_i,
652  ----------------- Receive Ports - RX Channel Bonding Ports ----------------
653  RXCHANISALIGNED => open,
654  RXCHANREALIGN => open,
655  -------------------- Receive Ports - RX Equailizer Ports -------------------
656  RXLPMHFHOLD => RXLPMHFHOLD_IN,
657  RXLPMHFOVRDEN => tied_to_ground_i,
658  RXLPMLFHOLD => RXLPMLFHOLD_IN,
659  --------------------- Receive Ports - RX Equalizer Ports -------------------
660  RXDFEAGCHOLD => tied_to_ground_i,
661  RXDFEAGCOVRDEN => tied_to_ground_i,
662  RXDFECM1EN => tied_to_ground_i,
663  RXDFELFHOLD => tied_to_ground_i,
664  RXDFELFOVRDEN => tied_to_ground_i,
665  RXDFELPMRESET => tied_to_ground_i,
666  RXDFETAP2HOLD => tied_to_ground_i,
667  RXDFETAP2OVRDEN => tied_to_ground_i,
668  RXDFETAP3HOLD => tied_to_ground_i,
669  RXDFETAP3OVRDEN => tied_to_ground_i,
670  RXDFETAP4HOLD => tied_to_ground_i,
671  RXDFETAP4OVRDEN => tied_to_ground_i,
672  RXDFETAP5HOLD => tied_to_ground_i,
673  RXDFETAP5OVRDEN => tied_to_ground_i,
674  RXDFEUTHOLD => tied_to_ground_i,
675  RXDFEUTOVRDEN => tied_to_ground_i,
676  RXDFEVPHOLD => tied_to_ground_i,
677  RXDFEVPOVRDEN => tied_to_ground_i,
678  RXDFEVSEN => tied_to_ground_i,
679  RXLPMLFKLOVRDEN => tied_to_ground_i,
680  RXMONITOROUT => open,
681  RXMONITORSEL => "00",
682  RXOSHOLD => tied_to_ground_i,
683  RXOSOVRDEN => tied_to_ground_i,
684  ------------ Receive Ports - RX Fabric ClocK Output Control Ports ----------
685  RXRATEDONE => open,
686  --------------- Receive Ports - RX Fabric Output Control Ports -------------
687  RXOUTCLK => RXOUTCLK_OUT,
688  RXOUTCLKFABRIC => open,
689  RXOUTCLKPCS => open,
690  RXOUTCLKSEL => "010",
691  ---------------------- Receive Ports - RX Gearbox Ports --------------------
692  RXDATAVALID => open,
693  RXHEADER => open,
694  RXHEADERVALID => open,
695  RXSTARTOFSEQ => open,
696  --------------------- Receive Ports - RX Gearbox Ports --------------------
697  RXGEARBOXSLIP => tied_to_ground_i,
698  ------------- Receive Ports - RX Initialization and Reset Ports ------------
699  GTRXRESET => GTRXRESET_IN,
700  RXOOBRESET => tied_to_ground_i,
701  RXPCSRESET => tied_to_ground_i,
702  RXPMARESET => RXPMARESET_IN,
703  ------------------ Receive Ports - RX Margin Analysis ports ----------------
704  RXLPMEN => tied_to_vcc_i,
705  ------------------- Receive Ports - RX OOB Signaling ports -----------------
706  RXCOMSASDET => open,
707  RXCOMWAKEDET => open,
708  ------------------ Receive Ports - RX OOB Signaling ports -----------------
709  RXCOMINITDET => open,
710  ------------------ Receive Ports - RX OOB signalling Ports -----------------
711  RXELECIDLE => open,
712  RXELECIDLEMODE => "11",
713  ----------------- Receive Ports - RX Polarity Control Ports ----------------
714  RXPOLARITY => tied_to_ground_i,
715  ---------------------- Receive Ports - RX gearbox ports --------------------
716  RXSLIDE => tied_to_ground_i,
717  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
718  RXCHARISCOMMA(7 downto 2) => rxchariscomma_float_i ,
719  RXCHARISCOMMA(1 downto 0) => RXCHARISCOMMA_OUT,
720  RXCHARISK(7 downto 2) => rxcharisk_float_i,
721  RXCHARISK(1 downto 0) => RXCHARISK_OUT,
722  ------------------ Receive Ports - Rx Channel Bonding Ports ----------------
723  RXCHBONDI => "00000",
724  -------------- Receive Ports -RX Initialization and Reset Ports ------------
725  RXRESETDONE => RXRESETDONE_OUT,
726  -------------------------------- Rx AFE Ports ------------------------------
727  RXQPIEN => tied_to_ground_i,
728  RXQPISENN => open,
729  RXQPISENP => open,
730  --------------------------- TX Buffer Bypass Ports -------------------------
731  TXPHDLYTSTCLK => tied_to_ground_i,
732  ------------------------ TX Configurable Driver Ports ----------------------
733  TXPOSTCURSOR => "00000",
734  TXPOSTCURSORINV => tied_to_ground_i,
735  TXPRECURSOR => tied_to_ground_vec_i (4 downto 0),
736  TXPRECURSORINV => tied_to_ground_i,
737  TXQPIBIASEN => tied_to_ground_i,
738  TXQPISTRONGPDOWN => tied_to_ground_i,
739  TXQPIWEAKPUP => tied_to_ground_i,
740  --------------------- TX Initialization and Reset Ports --------------------
741  CFGRESET => tied_to_ground_i,
742  GTTXRESET => GTTXRESET_IN,
743  PCSRSVDOUT => open,
744  TXUSERRDY => TXUSERRDY_IN,
745  ---------------------- Transceiver Reset Mode Operation --------------------
746  GTRESETSEL => tied_to_ground_i,
747  RESETOVRD => tied_to_ground_i,
748  ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
749  TXCHARDISPMODE => tied_to_ground_vec_i (7 downto 0),
750  TXCHARDISPVAL => tied_to_ground_vec_i (7 downto 0),
751  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
752  TXUSRCLK => TXUSRCLK_IN,
753  TXUSRCLK2 => TXUSRCLK2_IN,
754  --------------------- Transmit Ports - PCI Express Ports -------------------
755  TXELECIDLE => tied_to_ground_i,
756  TXMARGIN => tied_to_ground_vec_i (2 downto 0),
757  TXRATE => tied_to_ground_vec_i (2 downto 0),
758  TXSWING => tied_to_ground_i,
759  ------------------ Transmit Ports - Pattern Generator Ports ----------------
760  TXPRBSFORCEERR => tied_to_ground_i,
761  ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
762  TXDLYBYPASS => tied_to_vcc_i,
763  TXDLYEN => tied_to_ground_i,
764  TXDLYHOLD => tied_to_ground_i,
765  TXDLYOVRDEN => tied_to_ground_i,
766  TXDLYSRESET => tied_to_ground_i,
767  TXDLYSRESETDONE => open,
768  TXDLYUPDOWN => tied_to_ground_i,
769  TXPHALIGN => tied_to_ground_i,
770  TXPHALIGNDONE => open,
771  TXPHALIGNEN => tied_to_ground_i,
772  TXPHDLYPD => tied_to_ground_i,
773  TXPHDLYRESET => tied_to_ground_i,
774  TXPHINIT => tied_to_ground_i,
775  TXPHINITDONE => open,
776  TXPHOVRDEN => tied_to_ground_i,
777  ---------------------- Transmit Ports - TX Buffer Ports --------------------
778  TXBUFSTATUS => open,
779  --------------- Transmit Ports - TX Configurable Driver Ports --------------
780  TXBUFDIFFCTRL => "100",
781  TXDEEMPH => tied_to_ground_i,
782  TXDIFFCTRL => TXDIFFCTRL_IN,
783  TXDIFFPD => tied_to_ground_i,
784  TXINHIBIT => tied_to_ground_i,
785  TXMAINCURSOR => "0000000" ,
786  TXPISOPD => tied_to_ground_i,
787  ------------------ Transmit Ports - TX Data Path interface -----------------
788  TXDATA => txdata_i,
789  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
790  GTXTXN => GTXTXN_OUT,
791  GTXTXP => GTXTXP_OUT,
792  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
793  TXOUTCLK => TXOUTCLK_OUT,
794  TXOUTCLKFABRIC => TXOUTCLKFABRIC_OUT ,
795  TXOUTCLKPCS => TXOUTCLKPCS_OUT,
796  TXOUTCLKSEL => "010",
797  TXRATEDONE => open,
798  --------------------- Transmit Ports - TX Gearbox Ports --------------------
799  TXCHARISK(7 downto 2) => tied_to_ground_vec_i (5 downto 0),
800  TXCHARISK(1 downto 0) => TXCHARISK_IN,
801  TXGEARBOXREADY => open,
802  TXHEADER => tied_to_ground_vec_i (2 downto 0),
803  TXSEQUENCE => tied_to_ground_vec_i (6 downto 0),
804  TXSTARTSEQ => tied_to_ground_i,
805  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
806  TXPCSRESET => tied_to_ground_i,
807  TXPMARESET => tied_to_ground_i,
808  TXRESETDONE => TXRESETDONE_OUT,
809  ------------------ Transmit Ports - TX OOB signalling Ports ----------------
810  TXCOMFINISH => open,
811  TXCOMINIT => tied_to_ground_i,
812  TXCOMSAS => tied_to_ground_i,
813  TXCOMWAKE => tied_to_ground_i,
814  TXPDELECIDLEMODE => tied_to_ground_i,
815  ----------------- Transmit Ports - TX Polarity Control Ports ---------------
816  TXPOLARITY => tied_to_ground_i,
817  --------------- Transmit Ports - TX Receiver Detection Ports --------------
818  TXDETECTRX => tied_to_ground_i,
819  ------------------ Transmit Ports - TX8b/10b Encoder Ports -----------------
820  TX8B10BBYPASS => tied_to_ground_vec_i (7 downto 0),
821  ------------------ Transmit Ports - pattern Generator Ports ----------------
822  TXPRBSSEL => TXPRBSSEL_IN,
823  ----------------------- Tx Configurable Driver Ports ----------------------
824  TXQPISENN => open,
825  TXQPISENP => open
826 
827  );
828 
829  end RTL;
830 
831 
832 
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