Behavioral Architecture Reference

List of all members.

Processes
PROCESS_302	( sysclk ,reset )
PROCESS_303	( sysclk )
PROCESS_304	( sysclk )
PROCESS_305	( sysclk )
PROCESS_306	( sysclk )
PROCESS_307	( sysclk ,ThreeSFP ,TwoSFP ,sel_AMC )
PROCESS_308	( sysclk )
PROCESS_309	( sysclk )
PROCESS_310	( UsrClk )
PROCESS_311	( UsrClk ,reset )
PROCESS_312	( UsrClk )
PROCESS_313	( UsrClk ,reset )
PROCESS_314	( sysclk )
PROCESS_315	( UsrClk )
PROCESS_316	( clk125 ,RstAMC_link )
PROCESS_317	( UsrClk ,reset )
PROCESS_318	( TTC_status ,AMC_en )
PROCESS_319	( ipb_clk )
PROCESS_320	( ipb_addr )
PROCESS_321	( UsrClk )
PROCESS_322	( sysclk )
PROCESS_323	( sysclk )
PROCESS_324	( sysclk )

Components
fake_event	<Entity fake_event>
AMC_Link	<Entity AMC_Link>
AMC_wrapper	<Entity AMC_wrapper>
evt_bldr	<Entity evt_bldr>
AMC_cntr	<Entity AMC_cntr>
cmsCRC64	<Entity cmsCRC64>
FIFO_RESET_7S	<Entity FIFO_RESET_7S>
RAM32x6Db	<Entity RAM32x6Db>
RAM32x8	<Entity RAM32x8>
icon2
ila128x4096
chipscope1

Constants
AMC_ID	array12x4 := ( x " 0 " , x " 1 " , x " 2 " , x " 3 " , x " 4 " , x " 5 " , x " 6 " , x " 7 " , x " 8 " , x " 9 " , x " a " , x " b " )
AMC_txdiffctrl	array12x4 := ( others = >x " b " )
uFOV	std_logic_vector ( 3 downto 0 ) := x " 1 "

Types
array_x12y256	array ( 11 downto 0 ) of std_logic_vector ( 255 downto 0 )
array_x12y16	array ( 11 downto 0 ) of std_logic_vector ( 15 downto 0 )
array_x12y32	array ( 11 downto 0 ) of std_logic_vector ( 31 downto 0 )
array_x12y8	array ( 11 downto 0 ) of std_logic_vector ( 7 downto 0 )
array_x12y5	array ( 11 downto 0 ) of std_logic_vector ( 4 downto 0 )
array_x12y128	array ( 11 downto 0 ) of std_logic_vector ( 127 downto 0 )
array3X12	array ( 0 to 2 ) of std_logic_vector ( 11 downto 0 )
array3X4	array ( 0 to 2 ) of std_logic_vector ( 3 downto 0 )

Signals
kAMC	array2x4 := ( others = > ( others = > ' 0 ' ) )
mAMC	array3x4 := ( others = > ( others = > ' 0 ' ) )
nAMC	array3x4 := ( others = > ( others = > ' 0 ' ) )
EventInfo	array_x12y32 := ( others = > ( others = > ' 0 ' ) )
AMCinfo	array12X16 := ( others = > ( others = > ' 0 ' ) )
AMC_DATA	array12X64 := ( others = > ( others = > ' 0 ' ) )
AMC_DATA1	array12X64 := ( others = > ( others = > ' 0 ' ) )
AMC_DATA2	array12X64 := ( others = > ( others = > ' 0 ' ) )
Cntr_DATA	array12x16 := ( others = > ( others = > ' 0 ' ) )
AMCCRC_bad	array3X12 := ( others = > ( others = > ' 0 ' ) )
AMC_TTS	array_x12y8 := ( others = > ( others = > ' 0 ' ) )
AMC_TTS_RQST	array12X3 := ( others = > ( others = > ' 0 ' ) )
AMC_debug	array_x12y256 := ( others = > ( others = > ' 0 ' ) )
TTC_status	array_x12y128 := ( others = > ( others = > ' 0 ' ) )
badEventCRC_cntr	array12X16 := ( others = > ( others = > ' 0 ' ) )
ReSyncFakeEvent_cntr	array12X16 := ( others = > ( others = > ' 0 ' ) )
EventInfo_dav	std_logic_vector ( 11 downto 0 )
EventInfoRdDone	std_logic_vector ( 12 downto 0 ) := ( others = > ' 0 ' )
AMC_DATA_RdEn	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
Cntr_ADDR	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
AMC_if_ADDR	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
ipb_strobe_q	std_logic := ' 0 '
UsrClk	std_logic := ' 0 '
UsrClk_out	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
resetCntr_SyncRegs	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
resetSyncRegs	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
CntrRst	std_logic := ' 0 '
rst_AMC_cntr	std_logic := ' 0 '
evn_out	std_logic_vector ( 59 downto 0 ) := ( others = > ' 0 ' )
evn_wa	std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )
evn_ra	std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )
evt_cnt	array3x8 := ( others = > ( others = > ' 0 ' ) )
evn	std_logic_vector ( 23 downto 0 ) := ( others = > ' 0 ' )
CDF_in	std_logic_vector ( 71 downto 0 ) := ( others = > ' 0 ' )
CDF_out	std_logic_vector ( 71 downto 0 ) := ( others = > ' 0 ' )
CDF_wa	std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )
CDF_ra	std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )
CDF_cnt	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
empty_event_flag	std_logic := ' 0 '
evn_buf_full_i	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
ovfl_warning_i	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
ovfl_warning_p	std_logic := ' 0 '
header	std_logic := ' 0 '
init_bldr	std_logic := ' 0 '
CDF_header	std_logic := ' 0 '
CDF_empty	std_logic := ' 0 '
BlockHeader	std_logic := ' 0 '
ec_sel_AMC	std_logic := ' 0 '
sel_AMC	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
LastBlock	std_logic := ' 0 '
FirstBlock	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
sel_CDF	std_logic := ' 0 '
evn_empty	std_logic := ' 0 '
sel_evn	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
L1A_WrEn	std_logic := ' 0 '
L1A_DATA	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
EvtTy	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
CalTy	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
EventInfo_avl	std_logic := ' 0 '
rst_init_bldr	std_logic := ' 0 '
Builder_busy	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
ec_CDF_ra	std_logic := ' 0 '
summary	std_logic_vector ( 63 downto 0 ) := ( others = > ' 0 ' )
AMC_TTC_status	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
fake_en	std_logic := ' 0 '
fake_DATA	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
fake_header	std_logic := ' 0 '
fake_CRC	std_logic := ' 0 '
fake_WrEn	std_logic := ' 0 '
fake_word_cnt	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
fake_evt_cnt	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
empty_evt_cnt	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
fake_header_cnt	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
EventBuilt	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
badEventCRCToggle	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
ReSyncFakeEventToggle	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
EventBuiltToggle	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
badEventCRCToggleSyncRegs	array12x4 := ( others = > ( others = > ' 0 ' ) )
ReSyncFakeEventToggleSyncRegs	array12x4 := ( others = > ( others = > ' 0 ' ) )
EventBuiltToggleSyncRegs	array3x4 := ( others = > ( others = > ' 0 ' ) )
EventBuiltCnt	array3x16 := ( others = > ( others = > ' 0 ' ) )
next_bldr	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
AMC_wcp	array12x13 := ( others = > ( others = > ' 0 ' ) )
AMC_wc	std_logic_vector ( 17 downto 0 ) := ( others = > ' 0 ' )
AMC_wc_we	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
en_block_wc	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
block_wc_we	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
AMC_wc_mask	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
AMC_header	array3x66 := ( others = > ( others = > ' 0 ' ) )
AMC_header_we	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
bldr_fifo_full	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
AMC_DATA_re	array3X12 := ( others = > ( others = > ' 0 ' ) )
AMC_hasData	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
Mbit_word	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
AMC_REFCLK	std_logic := ' 0 '
AMC_TTS_OR	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
AMC_TTS_RQST_OR	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
AMC_qpll_lock	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
AMC_rxprbserr	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
AMC_rxcommaalignen	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
AMC_rxresetdone	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
AMC_txfsmresetdone	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
AMC_rxfsmresetdone	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
AMC_data_valid	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
AMC_RXDATA	array12x16 := ( others = > ( others = > ' 0 ' ) )
AMC_TXDATA	array12x16 := ( others = > ( others = > ' 0 ' ) )
AMC_RXNOTINTABLE	array12x2 := ( others = > ( others = > ' 0 ' ) )
AMC_rxchariscomma	array12x2 := ( others = > ( others = > ' 0 ' ) )
AMC_rxcharisk	array12x2 := ( others = > ( others = > ' 0 ' ) )
AMC_txcharisk	array12x2 := ( others = > ( others = > ' 0 ' ) )
AMC_rxprbssel	array12x3 := ( others = > ( others = > ' 0 ' ) )
AMC_txprbssel	array12x3 := ( others = > ( others = > ' 0 ' ) )
channel	array3X4 := ( others = > ( others = > ' 0 ' ) )
mon_wc	array3X16 := ( others = > ( others = > ' 0 ' ) )
mon_evt_wcp	std_logic_vector ( 47 downto 0 ) := ( others = > ' 0 ' )
zero_wc	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
more_wc	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
mon_en	std_logic := ' 0 '
scale_cntr	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
ce_scale	std_logic := ' 0 '
ld_scale	std_logic := ' 0 '
rst_mon_wc	std_logic := ' 0 '
ce_wc_reg_wa	std_logic := ' 0 '
wc_reg_wa	std_logic_vector ( 9 downto 0 ) := ( others = > ' 0 ' )
down_count	std_logic := ' 0 '
mon_mask	std_logic_vector ( 19 downto 0 ) := ( others = > ' 0 ' )
sample_event	std_logic := ' 0 '
scale	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
pending	std_logic := ' 0 '
AMC_Ready_i	std_logic_vector ( 11 downto 0 )
AMC_OK	std_logic_vector ( 11 downto 0 )
block_num	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
resetFIFO	std_logic := ' 0 '
fifo_rst	std_logic := ' 0 '
fifo_en	std_logic := ' 0 '
resetFIFO_AMC	std_logic := ' 0 '
fifo_rst_AMC	std_logic := ' 0 '
fifo_en_AMC	std_logic := ' 0 '
OneSFP	std_logic := ' 0 '
TwoSFP	std_logic := ' 0 '
ThreeSFP	std_logic := ' 0 '
fake_full	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
LinkFull	std_logic := ' 0 '
EventInSlink	array3x4 := ( others = > ( others = > ' 0 ' ) )
TTS_FIFO_do	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
TTS_FIFO_di	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
TTS_FIFO_wa	std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
TTS_FIFO_ra	std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
TTS_FIFO_waSyncRegs	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
TTS_FIFO_waSyncRegs2	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
TTS_FIFO_waSyncRegs3	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
evt_bldr_debug	STD_LOGIC_VECTOR ( 255 downto 0 )
stop_mon	std_logic := ' 0 '
errors	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
err_TTS	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
AMC_wc_sum_we	std_logic := ' 0 '
rst_AMC_wc_sum	std_logic := ' 0 '
wr_AMC_wc_sum	std_logic := ' 0 '
sel_AMC_q	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
AMC_wc_sum_di	std_logic_vector ( 5 downto 0 ) := ( others = > ' 0 ' )
AMC_wc_sum_do	std_logic_vector ( 5 downto 0 ) := ( others = > ' 0 ' )
AMC_wc_sum_a	std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
enRstAMC_link	std_logic := ' 0 '
RstAMC_link	std_logic := ' 0 '
RstAMC_link_dl	std_logic := ' 0 '
RstAMC_linkSync	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
AllEventBuilt_i	std_logic := ' 0 '
event_number_avl_q	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
bcnt	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
event_cnt	std_logic_vector ( 23 downto 0 ) := ( others = > ' 0 ' )
event_status	std_logic_vector ( 19 downto 0 ) := ( others = > ' 0 ' )
L1A_buf_we	std_logic := ' 0 '
L1A_buf_do	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
L1A_buf_di	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
L1A_buf_wa	std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )
RxBufUdfErr	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
RxBufOvfErr	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
RxBufOvf	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
RxBufUdf	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
RxClkCntr	std_logic_vector ( 19 downto 0 ) := ( others = > ' 0 ' )
RxClkCntr19_q	std_logic := ' 0 '
updateRatio	std_logic := ' 0 '
RxClkRatio	array12x21 := ( others = > ( others = > ' 0 ' ) )
AMC_if_RdEn	std_logic := ' 0 '
AMC_if_data	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
AMC_cntr_data	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
strobe2ms	std_logic := ' 0 '
Cntr2ms	std_logic_vector ( 18 downto 0 ) := ( others = > ' 0 ' )
CONTROL0	STD_LOGIC_VECTOR ( 35 downto 0 )
CONTROL1	STD_LOGIC_VECTOR ( 35 downto 0 )
DATA0	STD_LOGIC_VECTOR ( 143 downto 0 )
TRIG0	STD_LOGIC_VECTOR ( 7 downto 0 )
TRIG1	STD_LOGIC_VECTOR ( 7 downto 0 )
TRIG2	STD_LOGIC_VECTOR ( 7 downto 0 )
DATA1	STD_LOGIC_VECTOR ( 143 downto 0 )
TRIG0b	STD_LOGIC_VECTOR ( 7 downto 0 )
TRIG1b	STD_LOGIC_VECTOR ( 7 downto 0 )
TRIG2b	STD_LOGIC_VECTOR ( 7 downto 0 )
CS	STD_LOGIC_VECTOR ( 303 downto 0 ) := ( others = > ' 0 ' )

Instantiations
i_evt_bldr0	evt_bldr <Entity evt_bldr>
i_evt_bldr1	evt_bldr <Entity evt_bldr>
i_evt_bldr2	evt_bldr <Entity evt_bldr>
i_FIFO_RESET_AMC	FIFO_RESET_7S <Entity FIFO_RESET_7S>
i_AMC_Link	AMC_Link <Entity AMC_Link>
i_AMC_wrapper	AMC_wrapper <Entity AMC_wrapper>
i_fake_event	fake_event <Entity fake_event>
i_TTS_FIFO	RAM32x8 <Entity RAM32x8>
i_AMC_cntr	AMC_cntr <Entity AMC_cntr>
i_FIFO_RESET_7S	FIFO_RESET_7S <Entity FIFO_RESET_7S>
i_AMC_wc_sum	RAM32x6Db <Entity RAM32x6Db>

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Detailed Description

Definition at line 107 of file AMC_if.vhd.

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The documentation for this class was generated from the following files:

• src/common/AMC_if/AMC_if.vhd