AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
 All Classes Variables
AMC_if.vhd
1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 15:55:15 07/09/2010
6 -- Design Name:
7 -- Module Name: AMC_if - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 ----------------------------------------------------------------------------------
19 library IEEE;
20 use IEEE.STD_LOGIC_1164.ALL;
21 use IEEE.STD_LOGIC_ARITH.ALL;
22 use IEEE.STD_LOGIC_UNSIGNED.ALL;
23 use IEEE.std_logic_misc.all;
24 use work.amc13_pack.all;
25 
26 -- Uncomment the following library declaration if using
27 -- arithmetic functions with Signed or Unsigned values
28 --use IEEE.NUMERIC_STD.ALL;
29 
30 -- Uncomment the following library declaration if instantiating
31 -- any Xilinx primitives in this code.
32 library UNISIM;
33 use UNISIM.VComponents.all;
34 Library UNIMACRO;
35 use UNIMACRO.vcomponents.all;
36 
37 entity AMC_if is
38  Generic (simulation : boolean := false);
39  Port ( sysclk : in STD_LOGIC;
40  ipb_clk : in std_logic;
41  clk125 : in std_logic;
42  DRPclk : in std_logic;
43  GTXreset : in STD_LOGIC;
44  reset : in STD_LOGIC;
45  DB_cmd : IN std_logic;
46  ReSync : IN std_logic;
47  resetCntr : in STD_LOGIC;
48  run : in STD_LOGIC;
49  en_inject_err : in STD_LOGIC;
50  AllEventBuilt : out STD_LOGIC;
51  Dis_pd : in STD_LOGIC;
52  enSFP : IN std_logic_vector(3 downto 0);
53  en_localL1A : IN std_logic;
54  test : in STD_LOGIC;
55  NoReSyncFake : in STD_LOGIC;
56  WaitMonBuf : in STD_LOGIC;
57  fake_length : in std_logic_vector(19 downto 0);
58  T1_version : in STD_LOGIC_VECTOR(7 downto 0);
59  Source_ID : in array3x12;
60  AMC_en : in STD_LOGIC_VECTOR(11 downto 0);
61  AMC_Ready : out STD_LOGIC_VECTOR(11 downto 0);
62  BC0_lock : out STD_LOGIC_VECTOR(11 downto 0);
63  TTC_lock : out STD_LOGIC;
64  AMC_REFCLK_P : in STD_LOGIC;
65  AMC_REFCLK_N : in STD_LOGIC;
66  AMC_RXN : in STD_LOGIC_VECTOR(12 downto 1);
67  AMC_RXP : in STD_LOGIC_VECTOR(12 downto 1);
68  AMC_TXN : out STD_LOGIC_VECTOR(12 downto 1);
69  AMC_TXP : out STD_LOGIC_VECTOR(12 downto 1);
70  AMC_status : out STD_LOGIC_VECTOR(31 downto 0);
71  evt_data : out array3X67;-- bit 66 is TCP/mon space, bit 65 is end_of_event and bit 64 is end_of_block
72  evt_data_re : in std_logic_vector(2 downto 0);
73  evt_buf_full : in std_logic_vector(2 downto 0);
74  evt_data_we : out std_logic_vector(2 downto 0);
75  evt_data_rdy : out std_logic_vector(2 downto 0);
76  ddr_pa : in STD_LOGIC_VECTOR(9 downto 0);
77  MonBuf_empty : in STD_LOGIC;
78  mon_evt_wc : out STD_LOGIC_VECTOR (47 downto 0);
79  mon_ctrl : out STD_LOGIC_VECTOR (31 downto 0);
80 -- buffer control
81  mon_buf_avl : in STD_LOGIC; --
82  TCPbuf_avl : in STD_LOGIC; --
83  buf_rqst : out STD_LOGIC_VECTOR (3 downto 0);
84 -- ipbus signals
85  ipb_write : in STD_LOGIC;
86  ipb_strobe : in STD_LOGIC;
87  ipb_addr : in STD_LOGIC_VECTOR(31 downto 0);
88  ipb_wdata : in STD_LOGIC_VECTOR(31 downto 0);
89  ipb_rdata : out STD_LOGIC_VECTOR(31 downto 0);
90  ipb_ack : out STD_LOGIC;
91 -- TTC & TTS signals
92  TTC_clk : in std_logic;
93  TTC_LOS : in std_logic;
94  BC0 : in std_logic;
95  TTS_disable : in std_logic_vector(11 downto 0);
96  ttc_evcnt_reset : in std_logic;
97  event_number_avl : in std_logic;
98  event_number : in std_logic_vector(59 downto 0);
99  evn_buf_full : out std_logic;
100  ovfl_warning : out std_logic;
101  TrigData : out array12x8;
102  TTS_RQST : out std_logic_vector(2 downto 0);
103  TTS_coded : out std_logic_vector(4 downto 0)
104  );
105 end AMC_if;
106 
107 architecture Behavioral of AMC_if is
108 COMPONENT fake_event
109  PORT(
110  sysclk : IN std_logic;
111  UsrClk : IN std_logic;
112  reset : IN std_logic;
113  fifo_rst : IN std_logic;
114  fifo_en : IN std_logic;
115  sync : IN std_logic;
116  LinkFull : in STD_LOGIC;
117  fake_en : IN std_logic;
118  ovfl_warning : in STD_LOGIC;
119  fake_length : in std_logic_vector(19 downto 0);
120  L1A_DATA : IN std_logic_vector(15 downto 0);
121  L1A_WrEn : IN std_logic;
122  fake_header : OUT std_logic;
123  fake_CRC : OUT std_logic;
124  empty_event_flag : out STD_LOGIC;
125  fake_DATA : OUT std_logic_vector(15 downto 0);
126  fake_WrEn : OUT std_logic
127  );
128 END COMPONENT;
129 COMPONENT AMC_Link
130  generic(N : integer := 14; simulation : boolean := false); -- M controls FIFO size, N controls timeout
131  PORT(
132  sysclk : IN std_logic;
133  reset : IN std_logic;
134  resetCntr : IN std_logic;
135  fifo_rst : in std_logic;
136  fifo_en : in std_logic;
137  test : IN std_logic;
138  strobe2ms : in std_logic;
139  NoReSyncFake : IN std_logic;
140  UsrClk : IN std_logic;
141  AMC_ID : IN std_logic_vector(3 downto 0);
142  txfsmresetdone : in std_logic;
143  RxResetDone : in std_logic;
144  qpll_lock : in std_logic;
145  rxcommaalignen : out std_logic;
146  DATA_VALID : out std_logic;
147  RXDATA : in std_logic_vector(15 downto 0);
148  RXCHARISCOMMA : in std_logic_vector(1 downto 0);
149  RXCHARISK : in std_logic_vector(1 downto 0);
150  RXNOTINTABLE : in std_logic_vector(1 downto 0);
151  TXDATA : out std_logic_vector(15 downto 0);
152  TXCHARISK : out std_logic_vector(1 downto 0);
153  AMC_en : IN std_logic;
154  TTS_disable : IN std_logic;
155  AMC_DATA_RdEn : IN std_logic;
156  EventInfoRdDone : IN std_logic;
157  L1A_DATA : IN std_logic_vector(15 downto 0);
158  L1A_WrEn : IN std_logic;
159  fake_header : IN std_logic;
160  fake_CRC : IN std_logic;
161  fake_DATA : IN std_logic_vector(15 downto 0);
162  fake_WrEn : IN std_logic;
163  fake_full : OUT std_logic;
164  Cntr_ADDR : IN std_logic_vector(11 downto 0);
165  TTCclk : IN std_logic;
166  BC0 : IN std_logic;
167  TTC_LOS : IN std_logic;
168  Ready : OUT std_logic;
169  AMCinfo : OUT std_logic_vector(15 downto 0);
170  EventInfo : OUT std_logic_vector(31 downto 0);
171  EventInfo_dav : OUT std_logic;
172  AMC_DATA : OUT std_logic_vector(63 downto 0);
173  bad_AMC : OUT std_logic;
174  AMC_OK : OUT std_logic;
175  Cntr_DATA : OUT std_logic_vector(15 downto 0);
176  debug_out : OUT std_logic_vector(255 downto 0);
177  TTC_status : OUT std_logic_vector(127 downto 0);
178  TrigData : OUT std_logic_vector(7 downto 0);
179  TTS_RQST : OUT std_logic_vector(2 downto 0);
180  TTS_coded : OUT std_logic_vector(4 downto 0)
181  );
182 END COMPONENT;
183 COMPONENT AMC_wrapper
184  Port ( DRPclk : in STD_LOGIC;
185  SOFT_RESET : in STD_LOGIC;
186  UsrClk : in STD_LOGIC;
187  test : in STD_LOGIC;
188  Dis_pd : in STD_LOGIC;
189  AMC_en : in STD_LOGIC_VECTOR(11 downto 0);
190  RXDATA : out array12X16;
191  RxBufOvf : out STD_LOGIC_VECTOR(11 downto 0);
192  RxBufUdf : out STD_LOGIC_VECTOR(11 downto 0);
193  sampleRatio : in STD_LOGIC;
194  updateRatio : in STD_LOGIC;
195  RxClkRatio : out array12x21;
196  rxprbserr : out STD_LOGIC_VECTOR(11 downto 0);
197  rxprbssel : in array12X3;
198  RXNOTINTABLE : out array12X2;
199  rxcommaalignen : in STD_LOGIC_VECTOR(11 downto 0);
200  rxchariscomma : out array12X2;
201  rxcharisk : out array12X2;
202  rxresetdone : out STD_LOGIC_VECTOR(11 downto 0);
203  txdiffctrl : in array12X4;
204  TXDATA : in array12X16;
205  txoutclk : out STD_LOGIC_VECTOR(11 downto 0);
206  txcharisk : in array12X2;
207  txresetdone : out STD_LOGIC_VECTOR(11 downto 0);
208  txprbssel : in array12X3;
209  qpll_lock : out STD_LOGIC_VECTOR(2 downto 0);
210  txfsmresetdone : out STD_LOGIC_VECTOR(11 downto 0);
211  rxfsmresetdone : out STD_LOGIC_VECTOR(11 downto 0);
212  data_valid : in STD_LOGIC_VECTOR(11 downto 0);
213  AMC_REFCLK : in STD_LOGIC;
214  RXN : in STD_LOGIC_VECTOR(11 downto 0);
215  RXP : in STD_LOGIC_VECTOR(11 downto 0);
216  TXN : out STD_LOGIC_VECTOR(11 downto 0);
217  TXP : out STD_LOGIC_VECTOR(11 downto 0)
218  );
219 END COMPONENT;
220 COMPONENT evt_bldr
221  PORT(
222  clk : IN std_logic;
223  reset : IN std_logic;
224  fifo_rst : IN std_logic;
225  fifo_en : IN std_logic;
226  en_inject_err : IN std_logic;
227  OneSFP : IN std_logic;
228  Source_ID : IN std_logic_vector(7 downto 0);
229  block_wc : in STD_LOGIC_VECTOR (15 downto 0);
230  block_wc_we : in STD_LOGIC;
231  AMC_wc : IN std_logic_vector(17 downto 0);
232  AMC_wc_we : IN std_logic;
233  AMC_wc_end : IN std_logic;
234  AMC_header : IN std_logic_vector(65 downto 0);
235  AMC_header_we : IN std_logic;
236  AMC_DATA : IN array12X64;
237  evt_buf_full : IN std_logic;
238  evt_data_re : IN std_logic;
239  bldr_fifo_full : OUT std_logic;
240  AMC_DATA_re : OUT std_logic_vector(11 downto 0);
241  AMCCRC_bad : OUT std_logic_vector(11 downto 0);
242  evt_data : OUT std_logic_vector(66 downto 0);
243  evt_data_we : OUT std_logic;
244  evt_data_rdy : OUT std_logic;
245  debug : out STD_LOGIC_VECTOR (255 downto 0);
246  EventBuilt : OUT std_logic
247  );
248 END COMPONENT;
249 COMPONENT AMC_cntr
250 PORT(
251  UsrClk : IN std_logic;
252  clk125 : IN std_logic;
253  sysclk : IN std_logic;
254  ipb_clk : IN std_logic;
255  resetCntr : IN std_logic;
256  DB_cmd : IN std_logic;
257  AMC_if_data : IN std_logic_vector(15 downto 0);
258  Cntr_DATA : IN array12x16;
259  Cntr_ADDR : OUT std_logic_vector(11 downto 0);
260  ipb_addr : IN std_logic_vector(15 downto 0);
261  ipb_rdata : OUT std_logic_vector(31 downto 0)
262  );
263 END COMPONENT;
264 COMPONENT cmsCRC64
265  PORT(
266  clk : IN std_logic;
267  reset : IN std_logic;
268  data_in : IN std_logic_vector(63 downto 0);
269  ctrl_in : IN std_logic;
270  we_in : IN std_logic;
271  crc : OUT std_logic_vector(15 downto 0);
272  crc_err : OUT std_logic;
273  data_out : OUT std_logic_vector(63 downto 0);
274  ctrl_out : OUT std_logic;
275  we_out : OUT std_logic
276  );
277 END COMPONENT;
278 COMPONENT FIFO_RESET_7S
279  PORT(
280  reset : IN std_logic;
281  clk : IN std_logic;
282  fifo_rst : OUT std_logic;
283  fifo_en : OUT std_logic
284  );
285 END COMPONENT;
286 COMPONENT RAM32x6Db
287  PORT(
288  wclk : IN std_logic;
289  di : IN std_logic_vector(5 downto 0);
290  we : IN std_logic;
291  wa : IN std_logic_vector(4 downto 0);
292  ra : IN std_logic_vector(4 downto 0);
293  do : OUT std_logic_vector(5 downto 0)
294  );
295 END COMPONENT;
296 COMPONENT RAM32x8
297  PORT(
298  wclk : IN std_logic;
299  di : IN std_logic_vector(7 downto 0);
300  we : IN std_logic;
301  wa : IN std_logic_vector(4 downto 0);
302  ra : IN std_logic_vector(4 downto 0);
303  do : OUT std_logic_vector(7 downto 0)
304  );
305 END COMPONENT;
306 type array_x12y256 is array(11 downto 0) of std_logic_vector(255 downto 0);
307 type array_x12y16 is array(11 downto 0) of std_logic_vector(15 downto 0);
308 type array_x12y32 is array(11 downto 0) of std_logic_vector(31 downto 0);
309 type array_x12y8 is array(11 downto 0) of std_logic_vector(7 downto 0);
310 type array_x12y5 is array(11 downto 0) of std_logic_vector(4 downto 0);
311 type array_x12y128 is array(11 downto 0) of std_logic_vector(127 downto 0);
312 constant AMC_ID : array12x4 := (x"0",x"1",x"2",x"3",x"4",x"5",x"6",x"7",x"8",x"9",x"a",x"b");
313 constant AMC_txdiffctrl : array12x4 := (others => x"b");
314 constant uFOV : std_logic_vector(3 downto 0) := x"1";
315 signal kAMC : array2x4 := (others => (others => '0'));
316 signal mAMC : array3x4 := (others => (others => '0'));
317 signal nAMC : array3x4 := (others => (others => '0'));
318 signal EventInfo : array_x12y32 := (others => (others => '0'));
319 signal AMCinfo : array12X16 := (others => (others => '0'));
320 signal AMC_DATA : array12X64 := (others => (others => '0'));
321 signal AMC_DATA1 : array12X64 := (others => (others => '0'));
322 signal AMC_DATA2 : array12X64 := (others => (others => '0'));
323 signal Cntr_DATA : array12x16 := (others => (others => '0'));
324 signal AMCCRC_bad : array3X12 := (others => (others => '0'));
325 signal AMC_TTS : array_x12y8 := (others => (others => '0'));
326 signal AMC_TTS_RQST : array12X3 := (others => (others => '0'));
327 signal AMC_debug : array_x12y256 := (others => (others => '0'));
328 signal TTC_status : array_x12y128 := (others => (others => '0'));
329 signal badEventCRC_cntr : array12X16 := (others => (others => '0'));
330 signal ReSyncFakeEvent_cntr : array12X16 := (others => (others => '0'));
331 signal EventInfo_dav : std_logic_vector(11 downto 0);
332 --signal EventInfo_dav_n : std_logic_vector(11 downto 0);
333 signal EventInfoRdDone : std_logic_vector(12 downto 0) := (others => '0');
334 signal AMC_DATA_RdEn : std_logic_vector(11 downto 0) := (others => '0');
335 signal Cntr_ADDR : std_logic_vector(11 downto 0) := (others => '0');
336 signal AMC_if_ADDR : std_logic_vector(7 downto 0) := (others => '0');
337 signal ipb_strobe_q : std_logic := '0';
338 signal UsrClk : std_logic := '0';
339 signal UsrClk_out : std_logic_vector(11 downto 0) := (others => '0');
340 signal resetCntr_SyncRegs : std_logic_vector(2 downto 0) := (others => '0');
341 signal resetSyncRegs : std_logic_vector(2 downto 0) := (others => '0');
342 signal CntrRst : std_logic := '0';
343 signal rst_AMC_cntr : std_logic := '0';
344 signal evn_out : std_logic_vector(59 downto 0) := (others => '0');
345 signal evn_wa : std_logic_vector(8 downto 0) := (others => '0');
346 signal evn_ra : std_logic_vector(8 downto 0) := (others => '0');
347 signal evt_cnt : array3x8 := (others => (others => '0'));
348 signal evn : std_logic_vector(23 downto 0) := (others => '0');
349 signal CDF_in : std_logic_vector(71 downto 0) := (others => '0');
350 signal CDF_out : std_logic_vector(71 downto 0) := (others => '0');
351 signal CDF_wa : std_logic_vector(8 downto 0) := (others => '0');
352 signal CDF_ra : std_logic_vector(8 downto 0) := (others => '0');
353 signal CDF_cnt : std_logic_vector(7 downto 0) := (others => '0');
354 signal empty_event_flag : std_logic := '0';
355 signal evn_buf_full_i : std_logic_vector(2 downto 0) := (others => '0');
356 signal ovfl_warning_i : std_logic_vector(3 downto 0) := (others => '0');
357 signal ovfl_warning_p : std_logic := '0';
358 signal header : std_logic := '0';
359 signal init_bldr : std_logic := '0';
360 signal CDF_header : std_logic := '0';
361 signal CDF_empty : std_logic := '0';
362 signal BlockHeader : std_logic := '0';
363 signal ec_sel_AMC : std_logic := '0';
364 signal sel_AMC : std_logic_vector(3 downto 0) := (others => '0');
365 signal LastBlock : std_logic := '0';
366 signal FirstBlock : std_logic_vector(2 downto 0) := (others => '0');
367 signal sel_CDF : std_logic := '0';
368 signal evn_empty : std_logic := '0';
369 signal sel_evn : std_logic_vector(1 downto 0) := (others => '0');
370 signal L1A_WrEn : std_logic := '0';
371 signal L1A_DATA : std_logic_vector(15 downto 0) := (others => '0');
372 signal EvtTy : std_logic_vector(3 downto 0) := (others => '0');
373 signal CalTy : std_logic_vector(3 downto 0) := (others => '0');
374 signal EventInfo_avl : std_logic := '0';
375 signal rst_init_bldr : std_logic := '0';
376 signal Builder_busy : std_logic_vector(2 downto 0) := (others => '0');
377 signal ec_CDF_ra : std_logic := '0';
378 signal summary : std_logic_vector(63 downto 0) := (others => '0');
379 signal AMC_TTC_status : std_logic_vector(31 downto 0) := (others => '0');
380 signal fake_en: std_logic := '0';
381 signal fake_DATA : std_logic_vector(15 downto 0) := (others => '0');
382 signal fake_header : std_logic := '0';
383 signal fake_CRC : std_logic := '0';
384 signal fake_WrEn : std_logic := '0';
385 signal fake_word_cnt : std_logic_vector(15 downto 0) := (others => '0');
386 signal fake_evt_cnt : std_logic_vector(15 downto 0) := (others => '0');
387 signal empty_evt_cnt : std_logic_vector(15 downto 0) := (others => '0');
388 signal fake_header_cnt: std_logic_vector(15 downto 0) := (others => '0');
389 signal EventBuilt : std_logic_vector(2 downto 0) := (others => '0');
390 signal badEventCRCToggle : std_logic_vector(11 downto 0) := (others => '0');
391 signal ReSyncFakeEventToggle : std_logic_vector(11 downto 0) := (others => '0');
392 signal EventBuiltToggle : std_logic_vector(2 downto 0) := (others => '0');
393 signal badEventCRCToggleSyncRegs : array12x4 := (others => (others => '0'));
394 signal ReSyncFakeEventToggleSyncRegs : array12x4 := (others => (others => '0'));
395 signal EventBuiltToggleSyncRegs : array3x4 := (others => (others => '0'));
396 signal EventBuiltCnt : array3x16 := (others => (others => '0'));
397 signal next_bldr : std_logic_vector(1 downto 0) := (others => '0');
398 signal AMC_wcp : array12x13 := (others => (others => '0'));
399 signal AMC_wc : std_logic_vector(17 downto 0) := (others => '0');
400 signal AMC_wc_we : std_logic_vector(2 downto 0) := (others => '0');
401 signal en_block_wc : std_logic_vector(2 downto 0) := (others => '0');
402 signal block_wc_we : std_logic_vector(2 downto 0) := (others => '0');
403 signal AMC_wc_mask : std_logic_vector(2 downto 0) := (others => '0');
404 signal AMC_header : array3x66 := (others => (others => '0'));
405 signal AMC_header_we : std_logic_vector(2 downto 0) := (others => '0');
406 signal bldr_fifo_full : std_logic_vector(2 downto 0) := (others => '0');
407 type array3X12 is array(0 to 2) of std_logic_vector(11 downto 0);
408 signal AMC_DATA_re : array3X12 := (others => (others => '0'));
409 signal AMC_hasData : std_logic_vector(11 downto 0) := (others =>'0');
410 signal Mbit_word : std_logic_vector(11 downto 0) := (others =>'0');
411 --signal AMC_hasData_l : std_logic_vector(11 downto 0) := (others =>'0');
412 signal AMC_REFCLK : std_logic := '0';
413 signal AMC_TTS_OR : std_logic_vector(7 downto 0) := (others =>'0');
414 signal AMC_TTS_RQST_OR : std_logic_vector(2 downto 0) := (others =>'0');
415 signal AMC_qpll_lock : std_logic_vector(2 downto 0) := (others =>'0');
416 signal AMC_rxprbserr : std_logic_vector(11 downto 0) := (others =>'0');
417 signal AMC_rxcommaalignen : std_logic_vector(11 downto 0) := (others =>'0');
418 signal AMC_rxresetdone : std_logic_vector(11 downto 0) := (others =>'0');
419 signal AMC_txfsmresetdone : std_logic_vector(11 downto 0) := (others =>'0');
420 signal AMC_rxfsmresetdone : std_logic_vector(11 downto 0) := (others =>'0');
421 signal AMC_data_valid : std_logic_vector(11 downto 0) := (others =>'0');
422 signal AMC_RXDATA : array12x16 := (others => (others => '0'));
423 signal AMC_TXDATA : array12x16 := (others => (others => '0'));
424 signal AMC_RXNOTINTABLE : array12x2 := (others => (others => '0'));
425 signal AMC_rxchariscomma : array12x2 := (others => (others => '0'));
426 signal AMC_rxcharisk : array12x2 := (others => (others => '0'));
427 signal AMC_txcharisk : array12x2 := (others => (others => '0'));
428 signal AMC_rxprbssel : array12x3 := (others => (others => '0'));
429 signal AMC_txprbssel : array12x3 := (others => (others => '0'));
430 type array3X4 is array(0 to 2) of std_logic_vector(3 downto 0);
431 --signal AMC_rdata : array12x32 := (others => (others => '0'));
432 signal channel : array3X4 := (others => (others => '0'));
433 -- monitor signals
434 signal mon_wc: array3X16 := (others => (others => '0'));
435 signal mon_evt_wcp : std_logic_vector(47 downto 0) := (others => '0');
436 signal zero_wc : std_logic_vector(2 downto 0) := (others => '0');
437 signal more_wc : std_logic_vector(2 downto 0) := (others => '0');
438 signal mon_en: std_logic := '0';
439 signal scale_cntr : std_logic_vector(15 downto 0) := (others => '0');
440 signal ce_scale : std_logic := '0';
441 signal ld_scale : std_logic := '0';
442 --signal MonBufAbort: std_logic := '0';
443 signal rst_mon_wc: std_logic := '0';
444 signal ce_wc_reg_wa: std_logic := '0';
445 signal wc_reg_wa: std_logic_vector(9 downto 0) := (others => '0');
446 --signal start_wc_reg_wa: std_logic_vector(9 downto 0) := (others => '0');
447 signal down_count : std_logic := '0';
448 signal mon_mask: std_logic_vector(19 downto 0) := (others => '0');
449 signal sample_event: std_logic := '0';
450 signal scale : std_logic_vector(31 downto 0) := (others => '0');
451 signal pending : std_logic := '0';
452 signal AMC_Ready_i : std_logic_vector(11 downto 0);
453 signal AMC_OK : std_logic_vector(11 downto 0);
454 signal block_num : std_logic_vector(11 downto 0) := (others => '0');
455 signal resetFIFO : std_logic := '0';
456 signal fifo_rst : std_logic := '0';
457 signal fifo_en : std_logic := '0';
458 signal resetFIFO_AMC : std_logic := '0';
459 signal fifo_rst_AMC : std_logic := '0';
460 signal fifo_en_AMC : std_logic := '0';
461 signal OneSFP : std_logic := '0';
462 signal TwoSFP : std_logic := '0';
463 signal ThreeSFP : std_logic := '0';
464 signal fake_full : std_logic_vector(11 downto 0) := (others => '0');
465 signal LinkFull : std_logic := '0';
466 signal EventInSlink : array3x4 := (others => (others => '0'));
467 signal TTS_FIFO_do : std_logic_vector(7 downto 0) := (others => '0');
468 signal TTS_FIFO_di : std_logic_vector(7 downto 0) := (others => '0');
469 signal TTS_FIFO_wa : std_logic_vector(4 downto 0) := (others => '0');
470 signal TTS_FIFO_ra : std_logic_vector(4 downto 0) := (others => '0');
471 signal TTS_FIFO_waSyncRegs : std_logic_vector(2 downto 0) := (others => '0');
472 signal TTS_FIFO_waSyncRegs2 : std_logic_vector(2 downto 0) := (others => '0');
473 signal TTS_FIFO_waSyncRegs3 : std_logic_vector(2 downto 0) := (others => '0');
474 signal evt_bldr_debug : STD_LOGIC_VECTOR(255 DOWNTO 0);
475 signal stop_mon : std_logic := '0';
476 signal errors : std_logic_vector(7 downto 0) := (others => '0');
477 signal err_TTS : std_logic_vector(7 downto 0) := (others => '0');
478 signal AMC_wc_sum_we : std_logic := '0';
479 signal rst_AMC_wc_sum : std_logic := '0';
480 signal wr_AMC_wc_sum : std_logic := '0';
481 signal sel_AMC_q : std_logic_vector(3 downto 0) := (others => '0');
482 signal AMC_wc_sum_di : std_logic_vector(5 downto 0) := (others => '0');
483 signal AMC_wc_sum_do : std_logic_vector(5 downto 0) := (others => '0');
484 signal AMC_wc_sum_a : std_logic_vector(4 downto 0) := (others => '0');
485 signal enRstAMC_link : std_logic := '0';
486 signal RstAMC_link : std_logic := '0';
487 signal RstAMC_link_dl : std_logic := '0';
488 signal RstAMC_linkSync : std_logic_vector(3 downto 0) := (others => '0');
489 signal AllEventBuilt_i : std_logic := '0';
490 signal event_number_avl_q : std_logic_vector(2 downto 0) := (others => '0');
491 signal bcnt : std_logic_vector(11 downto 0) := (others => '0');
492 signal event_cnt : std_logic_vector(23 downto 0) := (others => '0');
493 signal event_status : std_logic_vector(19 downto 0) := (others => '0');
494 signal L1A_buf_we : std_logic := '0';
495 signal L1A_buf_do : std_logic_vector(31 downto 0) := (others => '0');
496 signal L1A_buf_di : std_logic_vector(31 downto 0) := (others => '0');
497 signal L1A_buf_wa : std_logic_vector(8 downto 0) := (others => '0');
498 signal RxBufUdfErr : std_logic_vector(11 downto 0) := (others => '0');
499 signal RxBufOvfErr : std_logic_vector(11 downto 0) := (others => '0');
500 signal RxBufOvf : std_logic_vector(11 downto 0) := (others => '0');
501 signal RxBufUdf : std_logic_vector(11 downto 0) := (others => '0');
502 signal RxClkCntr : std_logic_vector(19 downto 0) := (others => '0');
503 signal RxClkCntr19_q : std_logic := '0';
504 signal updateRatio : std_logic := '0';
505 signal RxClkRatio : array12x21 := (others => (others => '0'));
506 signal AMC_if_RdEn : std_logic := '0';
507 signal AMC_if_data : std_logic_vector(15 downto 0) := (others => '0');
508 signal AMC_cntr_data : std_logic_vector(31 downto 0) := (others => '0');
509 signal strobe2ms : std_logic := '0';
510 signal Cntr2ms : std_logic_vector(18 downto 0) := (others => '0');
511 component icon2
512  PORT (
513  CONTROL0 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
514  CONTROL1 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0));
515 
516 end component;
517 component ila128x4096
518  PORT (
519  CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
520  CLK : IN STD_LOGIC;
521  DATA : IN STD_LOGIC_VECTOR(143 DOWNTO 0);
522  TRIG0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
523  TRIG1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
524  TRIG2 : IN STD_LOGIC_VECTOR(7 DOWNTO 0));
525 
526 end component;
527 signal CONTROL0 : STD_LOGIC_VECTOR(35 DOWNTO 0);
528 signal CONTROL1 : STD_LOGIC_VECTOR(35 DOWNTO 0);
529 signal DATA0 : STD_LOGIC_VECTOR(143 DOWNTO 0);
530 signal TRIG0 : STD_LOGIC_VECTOR(7 DOWNTO 0);
531 signal TRIG1 : STD_LOGIC_VECTOR(7 DOWNTO 0);
532 signal TRIG2 : STD_LOGIC_VECTOR(7 DOWNTO 0);
533 signal DATA1 : STD_LOGIC_VECTOR(143 DOWNTO 0);
534 signal TRIG0b : STD_LOGIC_VECTOR(7 DOWNTO 0);
535 signal TRIG1b : STD_LOGIC_VECTOR(7 DOWNTO 0);
536 signal TRIG2b : STD_LOGIC_VECTOR(7 DOWNTO 0);
537 component chipscope1
538  generic (N : integer := 5);
539  Port ( clk : in STD_LOGIC;
540  Din : in STD_LOGIC_VECTOR (303 downto 0));
541 end component;
542 signal CS : STD_LOGIC_VECTOR(303 DOWNTO 0) := (others => '0');
543 begin
544 --i_chipscope : chipscope1 port map(clk => UsrClk, Din => cs);
545 --cs(61 downto 0) <= AMC_debug(3)(61 downto 0);
546 --cs(289) <= AMC_debug(3)(44);
547 --cs(288) <= AMC_debug(3)(40);
548 --i_chipscope : chipscope1 port map(clk => UsrClk, Din => cs);
549 --cs(288) <= AMC_debug(1)(48);
550 --cs(48 downto 0) <= AMC_debug(1)(48 downto 0);
551 --cs(303 downto 296) <= cs(212) & cs(210 downto 204);
552 --cs(295 downto 288) <= cs(147) & cs(145 downto 139);
553 --cs(295 downto 288) <= AMC_debug(0)(80) & AMC_debug(0)(62 downto 56);
554 --cs(288) <= AMC_debug(4)(82);
555 --cs(287) <= sel_CDF;
556 --cs(264 downto 183) <= AMC_debug(4)(81 downto 0);
557 --cs(182 downto 0) <= evt_bldr_debug(182 downto 0);
558 --i_icon : icon2
559 -- port map (
560 -- CONTROL0 => CONTROL0,
561 -- CONTROL1 => CONTROL1);
562 --i_ila : ila128x4096
563 -- port map (
564 -- CONTROL => CONTROL0,
565 -- CLK => UsrClk,
566 -- DATA => DATA0,
567 -- TRIG0 => TRIG0,
568 -- TRIG1 => x"00",
569 -- TRIG2 => x"00");
570 --DATA0(3 downto 0) <= TTC_status(10)(84 downto 81);
571 --DATA0(16 downto 4) <= TTC_status(10)(18 downto 6);
572 --DATA0(44 downto 17) <= TTC_status(10)(118 downto 91);
573 --DATA0(46 downto 45) <= AMC_rxchariscomma(10);
574 --DATA0(48 downto 47) <= AMC_rxcharisk(10);
575 --DATA0(64 downto 49) <= AMC_RXDATA(10);
576 --DATA0(66 downto 65) <= TTC_status(10)(53 downto 52);
577 --DATA0(70 downto 67) <= TTC_status(9)(84 downto 81);
578 --DATA0(83 downto 71) <= TTC_status(9)(18 downto 6);
579 --DATA0(85 downto 84) <= TTC_status(9)(53 downto 52);
580 --DATA0(87 downto 86) <= AMC_rxchariscomma(9);
581 --DATA0(89 downto 88) <= AMC_rxcharisk(9);
582 --DATA0(105 downto 90) <= AMC_RXDATA(9);
583 --DATA0(109 downto 106) <= TTC_status(1)(84 downto 81);
584 --DATA0(122 downto 110) <= TTC_status(1)(18 downto 6);
585 --DATA0(124 downto 123) <= TTC_status(1)(53 downto 52);
586 --DATA0(125) <= AMC_rxchariscomma(1)(0);
587 --DATA0(127 downto 126) <= AMC_rxcharisk(1);
588 --DATA0(143 downto 128) <= AMC_RXDATA(1);
589 --TRIG0(1 downto 0) <= TTC_status(10)(53 downto 52) ;
590 --TRIG0(3 downto 2) <= TTC_status(9)(53 downto 52) ;
591 --TRIG0(5 downto 4) <= TTC_status(1)(53 downto 52) ;
592 --TRIG0(7 downto 6) <= "00" ;
593 --i_ila_b : ila128x4096
594 -- port map (
595 -- CONTROL => CONTROL1,
596 -- CLK => TTC_clk,
597 -- DATA => DATA1,
598 -- TRIG0 => TRIG1,
599 -- TRIG1 => x"00",
600 -- TRIG2 => x"00");
601 --DATA1(0) <= BC0;
602 --DATA1(9 downto 1) <= TTC_status(10)(35 downto 27);
603 --DATA1(46 downto 10) <= TTC_status(10)(90 downto 54);
604 --DATA1(55 downto 47) <= TTC_status(9)(35 downto 27);
605 --DATA1(92 downto 56) <= TTC_status(9)(90 downto 54);
606 --DATA1(101 downto 93) <= TTC_status(1)(35 downto 27);
607 --DATA1(138 downto 102) <= TTC_status(1)(90 downto 54);
608 --DATA1(142 downto 139) <= bcnt;
609 --TRIG1(0) <= BC0;
610 --TRIG1(2 downto 1) <= TTC_status(10)(31 downto 30);
611 --TRIG1(4 downto 3) <= TTC_status(9)(31 downto 30);
612 --TRIG1(6 downto 5) <= TTC_status(1)(31 downto 30);
613 --TRIG1(7) <= '0';
614 AllEventBuilt <= AllEventBuilt_i;
615 AMC_Ready <= AMC_Ready_i;
616 mon_ctrl <= scale;
617 process(sysclk,reset)
618 begin
619  if(reset = '1')then
620  resetSyncRegs <= (others => '1');
621  RstAMC_link <= '1';
622  elsif(sysclk'event and sysclk = '1')then
623  resetSyncRegs <= resetSyncRegs(1 downto 0) & '0';
624  if(enRstAMC_link = '1' and AllEventBuilt_i = '1')then
625  RstAMC_link <= '1';
626  else
627  RstAMC_link <= resetSyncRegs(1);
628  end if;
629  end if;
630 end process;
631 process(sysclk)
632 begin
633  if(sysclk'event and sysclk = '1')then
634  if(resetSyncRegs(2) = '1')then
635  L1A_buf_wa <= (others => '0');
636  elsif(L1A_buf_we = '1')then
637  L1A_buf_wa <= L1A_buf_wa + 1;
638  end if;
639  if(resetSyncRegs(2) = '1' or ttc_evcnt_reset = '1')then
640  event_cnt <= (others => '0');
641  elsif(event_number_avl = '1')then
642  event_cnt <= event_cnt + 1;
643  end if;
644  event_number_avl_q <= event_number_avl_q(1 downto 0) & event_number_avl;
645  if(resetSyncRegs(2) = '1')then
646  L1A_buf_we <= '0';
647  else
648  L1A_buf_we <= event_number_avl or or_reduce(event_number_avl_q);
649  end if;
650  if(event_number_avl = '1')then
651  L1A_buf_di <= event_number(43 downto 12); -- OcN
652  bcnt <= event_number(11 downto 0); -- OcN
653  event_status <= event_number(59 downto 44) &"00" & event_number(45) & not event_number(45);
654  elsif(event_number_avl_q(0) = '1')then
655  L1A_buf_di <= x"00000" & bcnt; -- bcnt
656  elsif(event_number_avl_q(1) = '1')then
657  L1A_buf_di <= x"00" & event_cnt; -- bcnt
658  else
659  L1A_buf_di <= x"000" & event_status; -- bcnt
660  end if;
661  end if;
662 end process;
663 -- if(en_cal_win = '0')then
664 -- event_number(51 downto 48) <= x"0";
665 -- event_number(44) <= '0';
666 -- else
667 -- event_number(51) <= cal_win and brcst_GapTrig and cal_type(3) and not brcst_GapPed;
668 -- event_number(50) <= cal_win and brcst_GapTrig and cal_type(2) and not brcst_GapPed;
669 -- event_number(49) <= cal_win and brcst_GapTrig and cal_type(1) and not brcst_GapPed;
670 -- event_number(48) <= cal_win and ((brcst_GapTrig and cal_type(0)) or brcst_GapPed);
671 -- event_number(44) <= cal_win and (brcst_GapTrig or brcst_GapPed);
672 -- end if;
673 -- event_number(59 downto 56) <= cal_type;
674 -- event_number(55 downto 52) <= state;
675 -- event_number(47) <= brcst_GapTrig;
676 -- event_number(46) <= brcst_GapPed;
677 -- event_number(45) <= cal_win;
678 -- event_number(43 downto 0) <= oc & bcnt;
679 -- receiving L1 information
680 i_L1A_buf : BRAM_SDP_MACRO
681  generic map (
682  BRAM_SIZE => "18Kb", -- Target BRAM, "18Kb" or "36Kb"
683  DEVICE => "7SERIES", -- Target device: "VIRTEX5", "VIRTEX6", "7SERIES", "SPARTAN6"
684  WRITE_WIDTH => 32, -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
685  READ_WIDTH => 32) -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
686  port map (
687  DO => L1A_buf_do, -- Output read data port, width defined by READ_WIDTH parameter
688  DI => L1A_buf_di, -- Input write data port, width defined by WRITE_WIDTH parameter
689  RDADDR => ipb_addr(8 downto 0), -- Input read address, width defined by read port depth
690  RDCLK => sysclk, -- 1-bit input read clock
691  RDEN => '1', -- 1-bit input read port enable
692  REGCE => '1', -- 1-bit input read output register enable
693  RST => '0', -- 1-bit input reset
694  WE => x"f", -- Input write enable, width defined by write port depth
695  WRADDR => L1A_buf_wa, -- Input write address, width defined by write port depth
696  WRCLK => sysclk, -- 1-bit input write clock
697  WREN => L1A_buf_we -- 1-bit input write port enable
698  );
699 ovfl_warning <= ovfl_warning_i(3);
700 i_evn : BRAM_SDP_MACRO
701  generic map (
702  BRAM_SIZE => "36Kb", -- Target BRAM, "18Kb" or "36Kb"
703  DEVICE => "7SERIES", -- Target device: "VIRTEX5", "VIRTEX6", "7SERIES", "SPARTAN6"
704  WRITE_WIDTH => 60, -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
705  READ_WIDTH => 60, -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
706  DO_REG => 0, -- Optional output register (0 or 1)
707  SIM_COLLISION_CHECK => "NONE", -- Collision check enable "ALL", "WARNING_ONLY",
708  -- "GENERATE_X_ONLY" or "NONE"
709  WRITE_MODE => "WRITE_FIRST", -- Specify "READ_FIRST" for same clock or synchronous clocks
710  -- Specify "WRITE_FIRST for asynchrononous clocks on ports
711  INIT => X"000000000000000000") -- Initial values on output port
712  port map (
713  DO => evn_out, -- Output read data port, width defined by READ_WIDTH parameter
714  DI => event_number, -- Input write data port, width defined by WRITE_WIDTH parameter
715  RDADDR => evn_ra, -- Input read address, width defined by read port depth
716  RDCLK => sysclk, -- 1-bit input read clock
717  RDEN => '1', -- 1-bit input read port enable
718  REGCE => '1', -- 1-bit input read output register enable
719  RST => '0', -- 1-bit input reset
720  WE => x"ff", -- Input write enable, width defined by write port depth
721  WRADDR => evn_wa, -- Input write address, width defined by write port depth
722  WRCLK => sysclk, -- 1-bit input write clock
723  WREN => event_number_avl -- 1-bit input write port enable
724  );
725 process(sysclk)
726 variable enable : std_logic_vector(2 downto 0);
727 begin
728  if(ThreeSFP = '1')then
729  enable := "111";
730  elsif(TwoSFP = '1')then
731  enable := "011";
732  else
733  enable := "001";
734  end if;
735  if(sysclk'event and sysclk = '1')then
736  if(resetSyncRegs(2) = '1')then
737  evn_wa <= (others => '0');
738  elsif(event_number_avl = '1')then
739  evn_wa <= evn_wa + 1;
740  end if;
741  if(resetSyncRegs(2) = '1')then
742  evn_ra <= (others => '0');
743  elsif(sel_evn = "10")then
744  evn_ra <= evn_ra + 1;
745  end if;
746  if(ttc_evcnt_reset = '1' or resetSyncRegs(2) = '1')then
747  evn <= x"000001";
748  elsif(sel_evn = "10")then
749  evn <= evn + 1;
750  end if;
751  for i in 0 to 2 loop
752  if(resetSyncRegs(2) = '1' or enable(i) = '0')then
753  evt_cnt(i) <= (others => '0');
754  elsif(event_number_avl = '1' and EventBuilt(i) = '0')then
755  evt_cnt(i) <= evt_cnt(i) + 1;
756  elsif(event_number_avl = '0' and EventBuilt(i) = '1')then
757  evt_cnt(i) <= evt_cnt(i) - 1;
758  end if;
759  if(and_reduce(evt_cnt(i)(7 downto 5)) = '1')then
760  evn_buf_full_i(i) <= '1';
761  else
762  evn_buf_full_i(i) <= '0';
763  end if;
764  -- when reached 0x60, throttle L1A. Return only after go below 0x40
765  if(or_reduce(evt_cnt(i)(7 downto 6)) = '0')then
766  ovfl_warning_i(i) <= '0';
767  elsif(evt_cnt(i)(5) = '1')then
768  ovfl_warning_i(i) <= '1';
769  end if;
770  end loop;
771  evn_buf_full <= or_reduce(evn_buf_full_i);
772  ovfl_warning_i(3) <= or_reduce(ovfl_warning_i(2 downto 0)) or (or_reduce(TTS_FIFO_do(4 downto 0)) and en_localL1A);
773  end if;
774 end process;
775 -- send L1info to AMC_Link
776 process(sysclk)
777 begin
778  if(sysclk'event and sysclk = '1')then
779  if(resetSyncRegs(2) = '1' or evn_wa = evn_ra)then
780  evn_empty <= '1';
781  else
782  evn_empty <= '0';
783  end if;
784  L1A_WrEn <= not evn_empty;
785  if(resetSyncRegs(2) = '1' or evn_empty = '1')then
786  sel_evn <= "00";
787  else
788  sel_evn(1) <= sel_evn(1) xor sel_evn(0);
789  sel_evn(0) <= not sel_evn(0);
790  end if;
791  case sel_evn is
792  when "00" => L1A_DATA <= evn_out(11 downto 0) & x"0"; -- BX
793  when "01" => L1A_DATA <= evn(15 downto 0);
794  when "10" => L1A_DATA <= x"00" & evn(23 downto 16);
795  when others => L1A_DATA <= evn_out(27 downto 12); -- OrN
796  end case;
797  end if;
798 end process;
799 i_CDF : BRAM_SDP_MACRO
800  generic map (
801  BRAM_SIZE => "36Kb", -- Target BRAM, "18Kb" or "36Kb"
802  DEVICE => "7SERIES", -- Target device: "VIRTEX5", "VIRTEX6", "7SERIES", "SPARTAN6"
803  WRITE_WIDTH => 72, -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
804  READ_WIDTH => 72, -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
805  DO_REG => 0, -- Optional output register (0 or 1)
806  SIM_COLLISION_CHECK => "NONE", -- Collision check enable "ALL", "WARNING_ONLY",
807  -- "GENERATE_X_ONLY" or "NONE"
808  WRITE_MODE => "WRITE_FIRST", -- Specify "READ_FIRST" for same clock or synchronous clocks
809  -- Specify "WRITE_FIRST for asynchrononous clocks on ports
810  INIT => X"000000000000000000") -- Initial values on output port
811  port map (
812  DO => CDF_out, -- Output read data port, width defined by READ_WIDTH parameter
813  DI => CDF_in, -- Input write data port, width defined by WRITE_WIDTH parameter
814  RDADDR => CDF_ra, -- Input read address, width defined by read port depth
815  RDCLK => sysclk, -- 1-bit input read clock
816  RDEN => '1', -- 1-bit input read port enable
817  REGCE => '1', -- 1-bit input read output register enable
818  RST => '0', -- 1-bit input reset
819  WE => x"ff", -- Input write enable, width defined by write port depth
820  WRADDR => CDF_wa, -- Input write address, width defined by write port depth
821  WRCLK => sysclk, -- 1-bit input write clock
822  WREN => sel_evn(0) -- 1-bit input write port enable
823  );
824 process(sysclk)
825 begin
826  if(sysclk'event and sysclk = '1')then
827  if(resetSyncRegs(2) = '1')then
828  CDF_wa <= (others => '0');
829  elsif(sel_evn(0) = '1')then
830  CDF_wa <= CDF_wa + 1;
831  end if;
832  if(resetSyncRegs(2) = '1')then
833  CDF_ra <= (others => '0');
834  elsif(ec_CDF_ra = '1')then
835  CDF_ra <= CDF_ra + 1;
836  end if;
837  if(resetSyncRegs(2) = '1')then
838  CDF_cnt <= (others => '0');
839  elsif(sel_evn(0) = '1' and CDF_wa(0) = '1' and (ec_CDF_ra = '0' or CDF_ra(0) = '1'))then
840  CDF_cnt <= CDF_cnt + 1;
841  elsif((sel_evn(0) = '0' or CDF_wa(0) = '0') and ec_CDF_ra = '1' and CDF_ra(0) = '0')then
842  CDF_cnt <= CDF_cnt - 1;
843  end if;
844  if(resetSyncRegs(2) = '1')then
845  CDF_empty <= '1';
846  elsif(or_reduce(CDF_cnt(7 downto 1)) = '0' and (CDF_cnt(0) = '0' or ec_CDF_ra = '1'))then
847  CDF_empty <= '1';
848  elsif(or_reduce(CDF_cnt) = '1')then
849  CDF_empty <= '0';
850  end if;
851  if(sel_evn(1) = '0')then
852 -- CDF_in <= x"005" & EvtTy & evn & evn_out(11 downto 0) & Source_ID(11 downto 0) & x"08"; -- header1
853  CDF_in <= x"005" & EvtTy & evn & evn_out(11 downto 0) & x"00008"; -- header1
854  else
855  CDF_in <= x"00" & uFOV & CalTy & x"00000" & evn_out(43 downto 12) & x"0"; -- header2
856  end if;
857  end if;
858 end process;
859 EvtTy <= "00" & evn_out(45) & not evn_out(45);
860 CalTy <= evn_out(51 downto 48);
861 process(sysclk, ThreeSFP, TwoSFP, sel_AMC)
862 variable bldr_mask_sel : std_logic_vector(4 downto 0);
863 variable bldr_mask : std_logic_vector(2 downto 0);
864 --variable Mbit_word : std_logic_vector(11 downto 0);
865 begin
866  bldr_mask_sel(4) := ThreeSFP;
867  bldr_mask_sel(3) := TwoSFP;
868  bldr_mask_sel(2 downto 0) := sel_AMC(3 downto 1);
869  case bldr_mask_sel is
870  when "10100" | "10101" => bldr_mask := "100";
871  when "10000" | "10001" | "01000" | "01001" | "01010" => bldr_mask := "010";
872  when others => bldr_mask := "001";
873  end case;
874 -- for i in 0 to 11 loop
875 -- Mbit_word(i) := EventInfo(i)(25);
876 -- end loop;
877  if(sysclk'event and sysclk = '1')then
878  if(resetSyncRegs(2) = '1')then
879  CDF_header <= '1';
880  header <= '0';
881  init_bldr <= '0';
882  EventInfo_avl <= '0';
883  ec_sel_AMC <= '0';
884  AMC_wc_we <= "000";
885  AMC_wc_sum_we <= '0';
886  BlockHeader <= '0';
887  ec_CDF_ra <= '0';
888  AMC_header_we <= "000";
889  sel_CDF <= '0';
890  buf_rqst <= x"0";
891  sel_AMC <= x"0";
892  else
893  if((and_reduce(not AMC_hasData or EventInfo_dav) = '1' and or_reduce(AMC_hasData) = '1') or (or_reduce(amc_en) = '0' and CDF_empty = '0'))then
894  EventInfo_avl <= '1';
895  else
896  EventInfo_avl <= '0';
897  end if;
898 -- LastBlock <= not or_reduce(AMC_hasData and Mbit_word);
899  LastBlock <= '1';
900  for i in 0 to 11 loop
901  if(AMC_hasData(i) = '1' and EventInfo(i)(25) = '1')then
902  LastBlock <= '0';
903  end if;
904  end loop;
905  if(EventInfo_avl = '1' and init_bldr = '0' and bldr_fifo_full = "000" and ((mon_en = '0' and TCPbuf_avl = '1') or (mon_en = '1' and mon_buf_avl = '1')))then
906  if(CDF_header = '1')then
907  ec_CDF_ra <= '1';
908  zero_wc <= not ThreeSFP & OneSFP & '0';
909  else
910  BlockHeader <= '1';
911  end if;
912  header <= '1';
913  init_bldr <= '1';
914  buf_rqst <= LastBlock & CDF_header & not mon_en & mon_en;
915  AMC_header(0)(64) <= mon_en and mon_buf_avl;
916  AMC_header(1)(64) <= mon_en and mon_buf_avl;
917  AMC_header(2)(64) <= mon_en and mon_buf_avl;
918  more_wc <= "000";
919  for i in 0 to 11 loop
920  Mbit_word(i) <= AMC_hasData(i) and EventInfo(i)(25);
921  end loop;
922  elsif(rst_init_bldr = '1')then
923  init_bldr <= '0';
924 -- zero_wc <= zero_wc or not more_wc;
925  zero_wc <= not more_wc;
926  if(LastBlock = '1')then
927  ec_CDF_ra <= '1';
928  CDF_header <= '1';
929  end if;
930  else
931  header <= '0';
932  ec_CDF_ra <= '0';
933  buf_rqst <= x"0";
934  if(init_bldr = '1')then
935  CDF_header <= '0';
936  BlockHeader <= CDF_header;
937  end if;
938  if(ec_sel_AMC = '1' and Mbit_word(conv_integer(sel_AMC)) = '1')then
939  more_wc <= more_wc or bldr_mask;
940  end if;
941  end if;
942  sel_CDF <= (CDF_header and init_bldr) or BlockHeader;
943 -- if(BlockHeader = '1')then
944 -- AMC_hasData_l <= AMC_hasData;
945 -- end if;
946  if(BlockHeader = '1')then
947  ec_sel_AMC <= '1';
948  elsif(sel_AMC = x"b")then
949  ec_sel_AMC <= '0';
950  end if;
951  if(AMC_hasData(conv_integer(sel_AMC)) = '1' and ec_sel_AMC = '1')then
952  AMC_wc_we <= bldr_mask;
953  AMC_wc_sum_we <= or_reduce(bldr_mask);
954  else
955  AMC_wc_we <= "000";
956  AMC_wc_sum_we <= '0';
957  end if;
958  for i in 0 to 2 loop
959  if((sel_CDF = '1' and (FirstBlock(i) = '1' or nAMC(i) /= x"0")) or AMC_wc_we(i) = '1')then
960  AMC_header_we(i) <= '1';
961  else
962  AMC_header_we(i) <= '0';
963  end if;
964  end loop;
965  if(ec_sel_AMC = '0' or sel_AMC = x"b")then
966  sel_AMC <= x"0";
967  else
968  sel_AMC <= sel_AMC + 1;
969  end if;
970  end if;
971  for i in 0 to 2 loop
972  case AMC_hasData(i*4+3 downto i*4) is
973  when x"1" | x"2" | x"4" | x"8" => mAMC(i) <= x"1";
974  when x"3" | x"5" | x"6" | x"9" | x"a" | x"c" => mAMC(i) <= x"2";
975  when x"7" | x"b" | x"d" | x"e" => mAMC(i) <= x"3";
976  when x"f" => mAMC(i) <= x"4";
977  when others => mAMC(i) <= x"0";
978  end case;
979  end loop;
980  kAMC(0)(1) <= AMC_hasData(5) and AMC_hasData(4);
981  kAMC(0)(0) <= AMC_hasData(5) xor AMC_hasData(4);
982  kAMC(1)(1) <= AMC_hasData(7) and AMC_hasData(6);
983  kAMC(1)(0) <= AMC_hasData(7) xor AMC_hasData(6);
984  if(ThreeSFP = '1')then
985  nAMC(0) <= mAMC(1);
986  elsif(TwoSFP = '1')then
987  nAMC(0) <= mAMC(2) + kAMC(1);
988  else
989  nAMC(0) <= mAMC(0) + mAMC(1) + mAMC(2);
990  end if;
991  if(ThreeSFP = '1')then
992  nAMC(1) <= mAMC(0);
993  elsif(TwoSFP = '1')then
994  nAMC(1) <= mAMC(0) + kAMC(0);
995  else
996  nAMC(1) <= x"0";
997  end if;
998  if(ThreeSFP = '1')then
999  nAMC(2) <= mAMC(2);
1000  else
1001  nAMC(2) <= x"0";
1002  end if;
1003  summary <= '0' & EventInfo(conv_integer(sel_AMC))(26 downto 20) & x"0" & EventInfo(conv_integer(sel_AMC))(19 downto 0) & block_num & (sel_AMC+1) & AMCinfo(conv_integer(sel_AMC));
1004  for i in 0 to 2 loop
1005  AMC_header(i)(65) <= not BlockHeader and sel_CDF;
1006  if(sel_CDF = '0')then
1007  AMC_header(i)(55 downto 52) <= summary(55 downto 52);
1008  elsif(BlockHeader = '1')then
1009  AMC_header(i)(55 downto 52) <= CDF_out(55 downto 52);
1010  else
1011  AMC_header(i)(55 downto 52) <= nAMC(i);
1012  end if;
1013  if(sel_CDF = '1')then
1014  AMC_header(i)(63 downto 56) <= CDF_out(63 downto 56);
1015  AMC_header(i)(51 downto 20) <= CDF_out(51 downto 20);
1016  AMC_header(i)(7 downto 0) <= CDF_out(7 downto 0);
1017  else
1018  AMC_header(i)(63 downto 56) <= summary(63 downto 56);
1019  AMC_header(i)(51 downto 20) <= summary(51 downto 20);
1020  AMC_header(i)(7 downto 0) <= summary(7 downto 0);
1021  end if;
1022  end loop;
1023  if(sel_CDF = '0')then
1024  AMC_header(0)(19 downto 8) <= summary(19 downto 8);
1025  AMC_header(1)(19 downto 8) <= summary(19 downto 8);
1026  AMC_header(2)(19 downto 8) <= summary(19 downto 8);
1027  elsif(BlockHeader = '1')then
1028  if(OneSFP = '1')then
1029  AMC_header(0)(19 downto 8) <= source_ID(0);
1030  else
1031  AMC_header(0)(19 downto 8) <= source_ID(1);
1032  end if;
1033  AMC_header(1)(19 downto 8) <= source_ID(0);
1034  AMC_header(2)(19 downto 8) <= source_ID(2);
1035  else
1036  AMC_header(0)(19 downto 8) <= CDF_out(19 downto 8);
1037  AMC_header(1)(19 downto 8) <= CDF_out(19 downto 8);
1038  AMC_header(2)(19 downto 8) <= CDF_out(19 downto 8);
1039  end if;
1040  if(CDF_header = '1')then
1041  FirstBlock(0) <= '1';
1042  FirstBlock(1) <= not OneSFP;
1043  FirstBlock(2) <= ThreeSFP;
1044  block_num <= (others => '0');
1045  elsif(rst_init_bldr = '1')then
1046  FirstBlock <= "000";
1047  block_num <= block_num + 1;
1048  end if;
1049  if(fifo_en = '0' or (EventInfoRdDone(12) = '1' and LastBlock = '1'))then
1050  AMC_hasData <= AMC_en;
1051 -- elsif(ec_sel_AMC = '1' and EventInfo(conv_integer(sel_AMC))(25) = '0')then -- More bit is '0'
1052 -- AMC_hasData(conv_integer(sel_AMC)) <= '0';
1053  elsif(EventInfoRdDone(12) = '1')then
1054  AMC_hasData <= Mbit_word;
1055  end if;
1056  for i in 0 to 11 loop
1057  if(Mbit_word(i) = '1')then
1058  AMC_wcp(i) <= "1000000000000";
1059  else
1060  AMC_wcp(i) <= EventInfo(i)(12 downto 0);
1061  end if;
1062  end loop;
1063  if(OneSFP = '1')then
1064 -- AMC_wc(17) <= not or_reduce(AMC_hasData and Mbit_word);
1065  AMC_wc(17) <= not or_reduce(Mbit_word);
1066  elsif(TwoSFP = '1')then
1067  if(sel_AMC = x"0")then
1068  AMC_wc(17) <= not or_reduce(Mbit_word(5 downto 0));
1069  elsif(sel_AMC = x"6")then
1070  AMC_wc(17) <= not or_reduce(Mbit_word(11 downto 6));
1071  end if;
1072  else
1073  if(sel_AMC = x"0")then
1074  AMC_wc(17) <= not or_reduce(Mbit_word(3 downto 0));
1075  elsif(sel_AMC = x"4")then
1076  AMC_wc(17) <= not or_reduce(Mbit_word(7 downto 4));
1077  elsif(sel_AMC = x"8")then
1078  AMC_wc(17) <= not or_reduce(Mbit_word(11 downto 8));
1079  end if;
1080  end if;
1081  AMC_wc(16 downto 0) <= sel_AMC & AMC_wcp(conv_integer(sel_AMC));
1082  end if;
1083 end process;
1084 kAMC(1)(3 downto 2) <= "00";
1085 kAMC(0)(3 downto 2) <= "00";
1086 --AMC_header(1)(64 downto 56) <= AMC_header(0)(64 downto 56);
1087 --AMC_header(1)(51 downto 0) <= AMC_header(0)(51 downto 0);
1088 --AMC_header(2)(64 downto 56) <= AMC_header(0)(64 downto 56);
1089 --AMC_header(2)(51 downto 0) <= AMC_header(0)(51 downto 0);
1090 i_evt_bldr0: evt_bldr PORT MAP(
1091  clk => sysclk ,
1092  reset => resetSyncRegs(2),
1093  fifo_rst => fifo_rst,
1094  fifo_en => fifo_en,
1095  en_inject_err => en_inject_err,
1096  OneSFP => OneSFP,
1097  Source_ID => x"00",
1098  block_wc => mon_wc(0),
1099  block_wc_we => block_wc_we(0),
1100  AMC_wc => AMC_wc,
1101  AMC_wc_we => AMC_wc_we(0),
1102  AMC_wc_end => rst_init_bldr,
1103  bldr_fifo_full => bldr_fifo_full (0),
1104  AMC_header => AMC_header(0),
1105  AMC_header_we => AMC_header_we(0),
1106  AMC_DATA => AMC_DATA,
1107  AMC_DATA_re => AMC_DATA_re(0),
1108  AMCCRC_bad => AMCCRC_bad(0),
1109  evt_data => evt_data(0),
1110  evt_data_we => evt_data_we(0),
1111  evt_buf_full => evt_buf_full(0),
1112  evt_data_re => evt_data_re(0),
1113  evt_data_rdy => evt_data_rdy(0),
1114  debug => evt_bldr_debug ,
1115  EventBuilt => EventBuilt(0)
1116  );
1117 i_evt_bldr1: evt_bldr PORT MAP(
1118  clk => sysclk ,
1119  reset => resetSyncRegs(2),
1120  fifo_rst => fifo_rst,
1121  fifo_en => fifo_en,
1122  en_inject_err => en_inject_err,
1123  OneSFP => OneSFP,
1124  Source_ID => x"00",
1125  block_wc => mon_wc(1),
1126  block_wc_we => block_wc_we(1),
1127  AMC_wc => AMC_wc,
1128  AMC_wc_we => AMC_wc_we(1),
1129  AMC_wc_end => rst_init_bldr,
1130  bldr_fifo_full => bldr_fifo_full (1),
1131  AMC_header => AMC_header(1),
1132  AMC_header_we => AMC_header_we(1),
1133  AMC_DATA => AMC_DATA1,
1134  AMC_DATA_re => AMC_DATA_re(1),
1135  AMCCRC_bad => AMCCRC_bad(1),
1136  evt_data => evt_data(1),
1137  evt_data_we => evt_data_we(1),
1138  evt_buf_full => evt_buf_full(1),
1139  evt_data_re => evt_data_re(1),
1140  evt_data_rdy => evt_data_rdy(1),
1141  debug => open,
1142  EventBuilt => EventBuilt(1)
1143  );
1144 g_AMC_DATA1: for i in 0 to 5 generate
1145  AMC_DATA1(i) <= AMC_DATA(i);
1146  AMC_DATA1(i+6) <= (others => '0');
1147 end generate;
1148 i_evt_bldr2: evt_bldr PORT MAP(
1149  clk => sysclk ,
1150  reset => resetSyncRegs(2),
1151  fifo_rst => fifo_rst,
1152  fifo_en => fifo_en,
1153  en_inject_err => en_inject_err,
1154  OneSFP => OneSFP,
1155  Source_ID => x"00",
1156  block_wc => mon_wc(2),
1157  block_wc_we => block_wc_we(2),
1158  AMC_wc => AMC_wc,
1159  AMC_wc_we => AMC_wc_we(2),
1160  AMC_wc_end => rst_init_bldr,
1161  bldr_fifo_full => bldr_fifo_full (2),
1162  AMC_header => AMC_header(2),
1163  AMC_header_we => AMC_header_we(2),
1164  AMC_DATA => AMC_DATA2,
1165  AMC_DATA_re => AMC_DATA_re(2),
1166  AMCCRC_bad => AMCCRC_bad(2),
1167  evt_data => evt_data(2),
1168  evt_data_we => evt_data_we(2),
1169  evt_buf_full => evt_buf_full(2),
1170  evt_data_re => evt_data_re(2),
1171  evt_data_rdy => evt_data_rdy(2),
1172  debug => open,
1173  EventBuilt => EventBuilt(2)
1174  );
1175 g_AMC_DATA2: for i in 0 to 3 generate
1176  AMC_DATA2(i) <= AMC_DATA(i+8);
1177  AMC_DATA2(i+4) <= AMC_DATA(i+8);
1178  AMC_DATA2(i+8) <= AMC_DATA(i+8);
1179 end generate;
1180 AMC_DATA_RdEn <= AMC_DATA_re(0) or AMC_DATA_re(1) or AMC_DATA_re(2);
1181 process(sysclk)
1182 begin
1183  if(sysclk'event and sysclk = '1')then
1184  for i in 0 to 11 loop
1185  if(AMCCRC_bad(0)(i) = '1' or AMCCRC_bad(1)(i) = '1' or AMCCRC_bad(2)(i) = '1')then
1186  badEventCRCToggle(i) <= not badEventCRCToggle(i);
1187  end if;
1188  if(EventInfo(i)(31) = '1' and EventInfo(i)(25) = '0' and EventInfoRdDone(i) = '1')then
1189  ReSyncFakeEventToggle(i) <= not ReSyncFakeEventToggle(i);
1190  end if;
1191  end loop;
1192  end if;
1193 end process;
1194 i_FIFO_RESET_AMC: FIFO_RESET_7S PORT MAP(
1195  reset => resetFIFO_AMC,
1196  clk => sysclk ,
1197  fifo_rst => fifo_rst_AMC,
1198  fifo_en => fifo_en_AMC
1199  );
1200 resetFIFO_AMC <= reset or or_reduce(not AMC_txfsmresetdone and AMC_en) or RstAMC_link;
1201 g_AMC_Link : for i in 0 to 11 generate
1202  i_AMC_Link: AMC_Link
1203  PORT MAP(
1204  sysclk => sysclk,
1205  reset => RstAMC_link,
1206  resetCntr => CntrRst,
1207  fifo_rst => fifo_rst_AMC,
1208  fifo_en => fifo_en_AMC,
1209  test => test,
1210  strobe2ms => strobe2ms,
1211  NoReSyncFake => NoReSyncFake,
1212  UsrClk => UsrClk,
1213  RXNOTINTABLE => AMC_RXNOTINTABLE(i),
1214  rxcommaalignen => AMC_rxcommaalignen(i),
1215  rxchariscomma => AMC_rxchariscomma(i),
1216  rxcharisk => AMC_rxcharisk(i),
1217  rxresetdone => AMC_rxresetdone(i),
1218  qpll_lock => AMC_qpll_lock(i/4),
1219  txfsmresetdone => AMC_txfsmresetdone(i),
1220  data_valid => AMC_data_valid(i),
1221  RXDATA => AMC_RXDATA(i),
1222  txcharisk => AMC_txcharisk(i),
1223  TXDATA => AMC_TXDATA(i),
1224  Ready => AMC_Ready_i(i),
1225  AMC_ID => AMC_ID(i),
1226  AMCinfo => AMCinfo(i),
1227  EventInfo => EventInfo(i),
1228  EventInfo_dav => EventInfo_dav(i),
1229  AMC_DATA_RdEn => AMC_DATA_RdEn(i),
1230  EventInfoRdDone => EventInfoRdDone(i),
1231  AMC_DATA => AMC_DATA(i),
1232  bad_AMC => AMC_status(i),
1233  AMC_OK => AMC_OK(i),
1234  L1A_DATA => L1A_DATA,
1235  L1A_WrEn => L1A_WrEn,
1236  fake_header => fake_header,
1237  fake_CRC => fake_CRC,
1238  fake_DATA => fake_DATA,
1239  fake_WrEn => fake_WrEn,
1240  fake_full => fake_full(i),
1241  Cntr_ADDR => Cntr_ADDR,
1242  Cntr_DATA => Cntr_DATA(i),
1243  debug_out => AMC_debug(i),
1244  TTCclk => TTC_clk,
1245  BC0 => BC0,
1246  TTC_LOS => TTC_LOS,
1247  AMC_en => AMC_en(i),
1248  TTS_disable => TTS_disable(i),
1249  TTC_status => TTC_status(i),
1250  TrigData => TrigData(i),
1251  TTS_RQST => AMC_TTS_RQST(i),
1252  TTS_coded => AMC_TTS(i)(4 downto 0)
1253  );
1254 end generate;
1255 i_AMC_wrapper: AMC_wrapper PORT MAP(
1256  DRPclk => DRPclk,
1257  SOFT_RESET => GTXreset,
1258  UsrClk => UsrClk,
1259  test => test,
1260  Dis_pd => Dis_pd,
1261  AMC_en => AMC_en ,
1262  RXDATA => AMC_RXDATA,
1263  RxBufOvf => RxBufOvf,
1264  RxBufUdf => RxBufUdf,
1265  sampleRatio => RxClkCntr19_q,
1266  updateRatio => updateRatio,
1267  RxClkRatio => RxClkRatio,
1268  rxprbserr => AMC_rxprbserr,
1269  rxprbssel => AMC_rxprbssel,
1270  RXNOTINTABLE => AMC_RXNOTINTABLE,
1271  rxcommaalignen => AMC_rxcommaalignen,
1272  rxchariscomma => AMC_rxchariscomma,
1273  rxcharisk => AMC_rxcharisk,
1274  rxresetdone => AMC_rxresetdone,
1275  txdiffctrl => AMC_txdiffctrl,
1276  TXDATA => AMC_TXDATA,
1277  txoutclk => UsrClk_out,
1278  txcharisk => AMC_txcharisk,
1279  txresetdone => open,
1280  txprbssel => AMC_txprbssel,
1281  qpll_lock => AMC_qpll_lock,
1282  txfsmresetdone => AMC_txfsmresetdone,
1283  rxfsmresetdone => AMC_rxfsmresetdone,
1284  data_valid => AMC_data_valid,
1285  AMC_REFCLK => AMC_REFCLK,
1286  RXN => AMC_RXN,
1287  RXP => AMC_RXP,
1288  TXN => AMC_TXN,
1289  TXP => AMC_TXP
1290  );
1291 process(sysclk)
1292 begin
1293  if(sysclk'event and sysclk = '1')then
1294  ovfl_warning_p <= ovfl_warning_i(3) and not en_localL1A;
1295  if(resetSyncRegs(2) = '1')then
1296  AllEventBuilt_i <= '1';
1297  else
1298  for i in 0 to 2 loop
1299  if(EventBuilt(i) = '1')then
1300  EventBuiltToggle(i) <= not EventBuiltToggle(i);
1301  end if;
1302  end loop;
1303  if(evt_cnt(0) = x"00" and evt_cnt(1) = x"00" and evt_cnt(2) = x"00")then
1304  AllEventBuilt_i <= '1';
1305  else
1306  AllEventBuilt_i <= '0';
1307  end if;
1308  end if;
1309  if(RstAMC_link_dl = '1')then
1310  enRstAMC_link <= '0';
1311  elsif(ReSync = '1')then
1312  enRstAMC_link <= '1';
1313  end if;
1314  end if;
1315 end process;
1316 i_RstAMC_link_dl : SRL16E
1317  port map (
1318  Q => RstAMC_link_dl , -- SRL data output
1319  A0 => '1', -- Select[0] input
1320  A1 => '1', -- Select[1] input
1321  A2 => '1', -- Select[2] input
1322  A3 => '1', -- Select[3] input
1323  CE => '1', -- Clock enable input
1324  CLK => sysclk, -- Clock input
1325  D => RstAMC_link -- SRL data input
1326  );
1327 process(UsrClk)
1328 begin
1329  if(UsrClk'event and UsrClk = '1')then
1330  LinkFull <= or_reduce(fake_full);
1331  if(Cntr2ms(18 downto 17) = "11" and Cntr2ms(14) = '1')then
1332  Cntr2ms <= (others => '0');
1333  strobe2ms <= '1';
1334  else
1335  Cntr2ms <= Cntr2ms + 1;
1336  strobe2ms <= '0';
1337  end if;
1338  end if;
1339 end process;
1340 fake_en <= '0' when test = '0' or AMC_en = x"000" else '1';
1341 i_fake_event: fake_event PORT MAP(
1342  sysclk => sysclk,
1343  UsrClk => UsrClk,
1344  reset => resetSyncRegs(2),
1345  fifo_rst => fifo_rst,
1346  fifo_en => fifo_en,
1347  fake_en => fake_en,
1348  sync => '1',
1349  fake_length => fake_length,
1350  ovfl_warning => ovfl_warning_p ,
1351  LinkFull => LinkFull,
1352  L1A_DATA => L1A_DATA,
1353  L1A_WrEn => L1A_WrEn,
1354  fake_header => fake_header,
1355  fake_CRC => fake_CRC,
1356  empty_event_flag => empty_event_flag,
1357  fake_DATA => fake_DATA,
1358  fake_WrEn => fake_WrEn
1359  );
1360 process(UsrClk,reset)
1361 begin
1362  if(reset = '1')then
1363  for i in 0 to 11 loop
1364  AMC_TTS(i)(7 downto 5) <= "000";
1365  end loop;
1366  elsif(UsrClk'event and UsrClk = '1')then
1367  for i in 0 to 11 loop
1368  if(AMC_TTS(i)(2) = '1' and AMC_Ready_i(i) = '1')then -- Out of Sync
1369  AMC_TTS(i)(5) <= '1';
1370  end if;
1371  if(AMC_TTS(i)(3) = '1' and AMC_Ready_i(i) = '1')then -- error
1372  AMC_TTS(i)(6) <= '1';
1373  end if;
1374  if(AMC_TTS(i)(4) = '1' and AMC_Ready_i(i) = '1')then -- disconnected
1375  AMC_TTS(i)(7) <= '1';
1376  end if;
1377  end loop;
1378  end if;
1379 end process;
1380 process(UsrClk)
1381 begin
1382  if(UsrClk'event and UsrClk = '1')then
1383  AMC_TTS_OR <= AMC_TTS(0) or AMC_TTS(1) or AMC_TTS(2) or AMC_TTS(3) or AMC_TTS(4) or AMC_TTS(5) or
1384  AMC_TTS(6) or AMC_TTS(7) or AMC_TTS(8) or AMC_TTS(9) or AMC_TTS(10) or AMC_TTS(11) or err_TTS;
1385  AMC_TTS_RQST_OR <= AMC_TTS_RQST(0) or AMC_TTS_RQST(1) or AMC_TTS_RQST(2) or AMC_TTS_RQST(3) or AMC_TTS_RQST(4) or AMC_TTS_RQST(5) or
1386  AMC_TTS_RQST(6) or AMC_TTS_RQST(7) or AMC_TTS_RQST(8) or AMC_TTS_RQST(9) or AMC_TTS_RQST(10) or AMC_TTS_RQST(11);
1387  end if;
1388 end process;
1389 err_TTS <= "000000" & stop_mon & '0';
1390 process(UsrClk,reset)
1391 begin
1392  if(reset = '1')then
1393  TTS_FIFO_wa <= (others => '0');
1394  elsif(UsrClk'event and UsrClk = '1')then
1395  case TTS_FIFO_wa(2 downto 0) is
1396  when "000" => TTS_FIFO_wa(2 downto 0) <= "001";
1397  when "001" => TTS_FIFO_wa(2 downto 0) <= "011";
1398  when "011" => TTS_FIFO_wa(2 downto 0) <= "010";
1399  when "010" => TTS_FIFO_wa(2 downto 0) <= "110";
1400  when "110" => TTS_FIFO_wa(2 downto 0) <= "111";
1401  when "111" => TTS_FIFO_wa(2 downto 0) <= "101";
1402  when "101" => TTS_FIFO_wa(2 downto 0) <= "100";
1403  when others => TTS_FIFO_wa(2 downto 0) <= "000";
1404  end case;
1405  end if;
1406 end process;
1407 i_TTS_FIFO: RAM32x8 PORT MAP(
1408  wclk => UsrClk ,
1409  di => TTS_FIFO_di,
1410  we => '1',
1411  wa => TTS_FIFO_wa,
1412  ra => TTS_FIFO_ra,
1413  do => TTS_FIFO_do
1414  );
1415 TTS_FIFO_di <= AMC_TTS_RQST_OR & AMC_TTS_OR(4 downto 0);
1416 TTS_FIFO_ra <= "00" & TTS_FIFO_waSyncRegs3;
1417 process(sysclk)
1418 begin
1419  if(sysclk'event and sysclk = '1')then
1420  TTS_FIFO_waSyncRegs <= TTS_FIFO_wa(2 downto 0);
1421  TTS_FIFO_waSyncRegs2 <= TTS_FIFO_waSyncRegs;
1422  TTS_FIFO_waSyncRegs3 <= TTS_FIFO_waSyncRegs2;
1423  if(enRstAMC_link = '1' or AMC_en /= AMC_Ready_i)then
1424  TTS_coded <= "00010";
1425  else
1426  TTS_coded <= TTS_FIFO_do(4 downto 0);
1427  end if;
1428  TTS_RQST <= TTS_FIFO_do(7 downto 5);
1429  end if;
1430 end process;
1431 i_UsrClk_buf: bufg port map(i => UsrClk_out(6), o => UsrClk );
1432 process(UsrClk)
1433 begin
1434  if(UsrClk'event and UsrClk = '1')then
1435  RxClkCntr <= RxClkCntr + 1;
1436  RXClkCntr19_q <= RXClkCntr(19);
1437  if(RXClkCntr19_q = '1' and RXClkCntr(19) = '0')then
1438  if(Cntr_ADDR(11 downto 5) = "1110001")then
1439  updateRatio <= '0';
1440  else
1441  updateRatio <= '1';
1442  end if;
1443  end if;
1444  if(Cntr_ADDR(11 downto 7) = "11000" or Cntr_ADDR(11 downto 6) = "111000")then
1445  AMC_if_RdEn <= '1';
1446  else
1447  AMC_if_RdEn <= '0';
1448  end if;
1449  if(Cntr_ADDR(11 downto 7) = "11000" or Cntr_ADDR(11 downto 6) = "111000")then
1450  AMC_if_ADDR <= Cntr_ADDR(9) & Cntr_ADDR(6 downto 0);
1451  else
1452  AMC_if_ADDR <= (others => '0');
1453  end if;
1454  if(AMC_if_RdEn = '0')then
1455  AMC_if_data <= (others => '0');
1456  elsif(AMC_if_ADDR(7) = '0')then
1457  case AMC_if_ADDR(6 downto 4) is
1458  when "000" =>
1459  case AMC_if_ADDR(3 downto 0) is
1460  when x"0" => AMC_if_data <= EventInfo(0)(15 downto 0);
1461  when x"1" => AMC_if_data <= EventInfo(0)(31 downto 16);
1462  when x"2" => AMC_if_data <= EventInfo(1)(15 downto 0);
1463  when x"3" => AMC_if_data <= EventInfo(1)(31 downto 16);
1464  when x"4" => AMC_if_data <= EventInfo(2)(15 downto 0);
1465  when x"5" => AMC_if_data <= EventInfo(2)(31 downto 16);
1466  when x"6" => AMC_if_data <= EventInfo(3)(15 downto 0);
1467  when x"7" => AMC_if_data <= EventInfo(3)(31 downto 16);
1468  when x"8" => AMC_if_data <= EventInfo(4)(15 downto 0);
1469  when x"9" => AMC_if_data <= EventInfo(4)(31 downto 16);
1470  when x"a" => AMC_if_data <= EventInfo(5)(15 downto 0);
1471  when x"b" => AMC_if_data <= EventInfo(5)(31 downto 16);
1472  when x"c" => AMC_if_data <= EventInfo(6)(15 downto 0);
1473  when x"d" => AMC_if_data <= EventInfo(6)(31 downto 16);
1474  when x"e" => AMC_if_data <= EventInfo(7)(15 downto 0);
1475  when others => AMC_if_data <= EventInfo(7)(31 downto 16);
1476  end case;
1477  when "001" =>
1478  case AMC_if_ADDR(3 downto 0) is
1479  when x"0" => AMC_if_data <= EventInfo(8)(15 downto 0);
1480  when x"1" => AMC_if_data <= EventInfo(8)(31 downto 16);
1481  when x"2" => AMC_if_data <= EventInfo(9)(15 downto 0);
1482  when x"3" => AMC_if_data <= EventInfo(9)(31 downto 16);
1483  when x"4" => AMC_if_data <= EventInfo(10)(15 downto 0);
1484  when x"5" => AMC_if_data <= EventInfo(10)(31 downto 16);
1485  when x"6" => AMC_if_data <= EventInfo(11)(15 downto 0);
1486  when x"7" => AMC_if_data <= EventInfo(11)(31 downto 16);
1487  when x"8" => AMC_if_data <= LinkFull & not AMC_qpll_lock & EventInfo_dav;
1488  when x"9" => AMC_if_data <= x"0" & fake_full;
1489  when x"a" => AMC_if_data <= AMC_TTC_status(15 downto 0);
1490  when x"b" => AMC_if_data <= AMC_TTC_status(31 downto 16);
1491  when x"c" => AMC_if_data <= x"0" & AMC_rxfsmresetdone;
1492  when x"d" => AMC_if_data <= x"0" & AMC_txfsmresetdone;
1493  when x"e" => AMC_if_data <= "0000000" & CDF_empty & CDF_cnt;
1494  when others => AMC_if_data <= errors & x"00";
1495  end case;
1496  when "010" =>
1497  case AMC_if_ADDR(3 downto 0) is
1498  when x"0" => AMC_if_data <= "0000000" & evn_wa;
1499  when x"1" => AMC_if_data <= "0000000" & evn_ra;
1500  when x"2" => AMC_if_data <= evn(15 downto 0);
1501  when x"3" => AMC_if_data <= x"00" & evn(23 downto 16);
1502  when x"4" => AMC_if_data <= "0000000" & CDF_wa;
1503  when x"5" => AMC_if_data <= "0000000" & CDF_ra;
1504  when x"6" => AMC_if_data <= ec_CDF_ra & AMC_wc_we & sel_CDF & AMC_header_we & sel_evn & "00" & sel_AMC;
1505  when x"7" => AMC_if_data <= "000" & evt_buf_full & mon_en & WaitMonBuF & TCPbuf_avl & mon_buf_avl & init_bldr & evn_empty & EventInfo_avl & bldr_fifo_full;
1506  when x"8" => AMC_if_data <= fake_word_cnt;
1507  when x"a" => AMC_if_data <= fake_header_cnt;
1508  when x"c" => AMC_if_data <= fake_evt_cnt;
1509  when x"e" => AMC_if_data <= empty_evt_cnt;
1510  when others => AMC_if_data <= (others => '0');
1511  end case;
1512  when "011" =>
1513  case AMC_if_ADDR(3 downto 0) is
1514  when x"0" => AMC_if_data <= TTC_status(3)(5 downto 2) & TTC_status(2)(5 downto 2) & TTC_status(1)(5 downto 2) & TTC_status(0)(5 downto 2);
1515  when x"1" => AMC_if_data <= TTC_status(7)(5 downto 2) & TTC_status(6)(5 downto 2) & TTC_status(5)(5 downto 2) & TTC_status(4)(5 downto 2);
1516  when x"2" => AMC_if_data <= TTC_status(11)(5 downto 2) & TTC_status(10)(5 downto 2) & TTC_status(9)(5 downto 2) & TTC_status(8)(5 downto 2);
1517  when x"4" => AMC_if_data <= AMC_TTS(1) & AMC_TTS(0);
1518  when x"5" => AMC_if_data <= AMC_TTS(3) & AMC_TTS(2);
1519  when x"6" => AMC_if_data <= AMC_TTS(5) & AMC_TTS(4);
1520  when x"7" => AMC_if_data <= AMC_TTS(7) & AMC_TTS(6);
1521  when x"8" => AMC_if_data <= AMC_TTS(9) & AMC_TTS(8);
1522  when x"9" => AMC_if_data <= AMC_TTS(11) & AMC_TTS(10);
1523  when x"a" => AMC_if_data <= evt_cnt(1) & evt_cnt(0);
1524  when x"b" => AMC_if_data <= enRstAMC_link & "00000" & AllEventBuilt_i & AllEventBuilt_i & evt_cnt(2);
1525  when x"c" => AMC_if_data <= x"0" & AMC_TTS_RQST(3) & AMC_TTS_RQST(2) & AMC_TTS_RQST(1) & AMC_TTS_RQST(0);
1526  when x"d" => AMC_if_data <= x"0" & AMC_TTS_RQST(7) & AMC_TTS_RQST(6) & AMC_TTS_RQST(5) & AMC_TTS_RQST(4);
1527  when x"e" => AMC_if_data <= x"0" & AMC_TTS_RQST(11) & AMC_TTS_RQST(10) & AMC_TTS_RQST(9) & AMC_TTS_RQST(8);
1528  when others => AMC_if_data <= (others => '0');
1529  end case;
1530  when "100" =>
1531  case AMC_if_ADDR(3 downto 0) is
1532  when x"0" => AMC_if_data <= badEventCRC_cntr(0);
1533  when x"2" => AMC_if_data <= badEventCRC_cntr(1);
1534  when x"4" => AMC_if_data <= badEventCRC_cntr(2);
1535  when x"6" => AMC_if_data <= badEventCRC_cntr(3);
1536  when x"8" => AMC_if_data <= badEventCRC_cntr(4);
1537  when x"a" => AMC_if_data <= badEventCRC_cntr(5);
1538  when x"c" => AMC_if_data <= badEventCRC_cntr(6);
1539  when x"e" => AMC_if_data <= badEventCRC_cntr(7);
1540  when others => AMC_if_data <= (others => '0');
1541  end case;
1542  when "101" =>
1543  case AMC_if_ADDR(3 downto 0) is
1544  when x"0" => AMC_if_data <= badEventCRC_cntr(8);
1545  when x"2" => AMC_if_data <= badEventCRC_cntr(9);
1546  when x"4" => AMC_if_data <= badEventCRC_cntr(10);
1547  when x"6" => AMC_if_data <= badEventCRC_cntr(11);
1548  when x"8" => AMC_if_data <= EventBuiltCnt(0);
1549  when x"a" => AMC_if_data <= EventBuiltCnt(1);
1550  when x"c" => AMC_if_data <= EventBuiltCnt(2);
1551  when others => AMC_if_data <= (others => '0');
1552  end case;
1553  when "110" | "111" =>
1554  if(AMC_if_ADDR(0) = '0')then
1555  AMC_if_data <= x"00" & "00" & AMC_wc_sum_do;
1556  else
1557  AMC_if_data <= (others => '0');
1558  end if;
1559  when others => AMC_if_data <= (others => '0');
1560  end case;
1561  else
1562  case AMC_if_ADDR(5 downto 4) is
1563  when "00" =>
1564  case AMC_if_ADDR(3 downto 0) is
1565  when x"0" => AMC_if_data <= ReSyncFakeEvent_cntr(0);
1566  when x"2" => AMC_if_data <= ReSyncFakeEvent_cntr(1);
1567  when x"4" => AMC_if_data <= ReSyncFakeEvent_cntr(2);
1568  when x"6" => AMC_if_data <= ReSyncFakeEvent_cntr(3);
1569  when x"8" => AMC_if_data <= ReSyncFakeEvent_cntr(4);
1570  when x"a" => AMC_if_data <= ReSyncFakeEvent_cntr(5);
1571  when x"c" => AMC_if_data <= ReSyncFakeEvent_cntr(6);
1572  when x"e" => AMC_if_data <= ReSyncFakeEvent_cntr(7);
1573  when others => AMC_if_data <= (others => '0');
1574  end case;
1575  when "01" =>
1576  case AMC_if_ADDR(3 downto 0) is
1577  when x"0" => AMC_if_data <= ReSyncFakeEvent_cntr(8);
1578  when x"2" => AMC_if_data <= ReSyncFakeEvent_cntr(9);
1579  when x"4" => AMC_if_data <= ReSyncFakeEvent_cntr(10);
1580  when x"6" => AMC_if_data <= ReSyncFakeEvent_cntr(11);
1581  when others => AMC_if_data <= (others => '0');
1582  end case;
1583  when "10" =>
1584  case AMC_if_ADDR(3 downto 0) is
1585  when x"0" => AMC_if_data <= RxClkRatio(0)(15 downto 0);
1586  when x"1" => AMC_if_data <= x"00" & "000" & RxClkRatio(0)(20 downto 16);
1587  when x"2" => AMC_if_data <= RxClkRatio(1)(15 downto 0);
1588  when x"3" => AMC_if_data <= x"00" & "000" & RxClkRatio(1)(20 downto 16);
1589  when x"4" => AMC_if_data <= RxClkRatio(2)(15 downto 0);
1590  when x"5" => AMC_if_data <= x"00" & "000" & RxClkRatio(2)(20 downto 16);
1591  when x"6" => AMC_if_data <= RxClkRatio(3)(15 downto 0);
1592  when x"7" => AMC_if_data <= x"00" & "000" & RxClkRatio(3)(20 downto 16);
1593  when x"8" => AMC_if_data <= RxClkRatio(4)(15 downto 0);
1594  when x"9" => AMC_if_data <= x"00" & "000" & RxClkRatio(4)(20 downto 16);
1595  when x"a" => AMC_if_data <= RxClkRatio(5)(15 downto 0);
1596  when x"b" => AMC_if_data <= x"00" & "000" & RxClkRatio(5)(20 downto 16);
1597  when x"c" => AMC_if_data <= RxClkRatio(6)(15 downto 0);
1598  when x"d" => AMC_if_data <= x"00" & "000" & RxClkRatio(6)(20 downto 16);
1599  when x"e" => AMC_if_data <= RxClkRatio(7)(15 downto 0);
1600  when others => AMC_if_data <= x"00" & "000" & RxClkRatio(7)(20 downto 16);
1601  end case;
1602  when others =>
1603  case AMC_if_ADDR(3 downto 0) is
1604  when x"0" => AMC_if_data <= RxClkRatio(8)(15 downto 0);
1605  when x"1" => AMC_if_data <= x"00" & "000" & RxClkRatio(8)(20 downto 16);
1606  when x"2" => AMC_if_data <= RxClkRatio(9)(15 downto 0);
1607  when x"3" => AMC_if_data <= x"00" & "000" & RxClkRatio(9)(20 downto 16);
1608  when x"4" => AMC_if_data <= RxClkRatio(10)(15 downto 0);
1609  when x"5" => AMC_if_data <= x"00" & "000" & RxClkRatio(10)(20 downto 16);
1610  when x"6" => AMC_if_data <= RxClkRatio(11)(15 downto 0);
1611  when x"7" => AMC_if_data <= x"00" & "000" & RxClkRatio(11)(20 downto 16);
1612  when x"8" => AMC_if_data <= x"0" & RxBufUdfErr;
1613  when x"9" => AMC_if_data <= x"0" & RxBufOvfErr;
1614  when others => AMC_if_data <= (others => '0');
1615  end case;
1616  end case;
1617  end if;
1618  end if;
1619 end process;
1620 process(clk125, RstAMC_link)
1621 begin
1622  if(RstAMC_link = '1')then
1623  rst_AMC_cntr <= '1';
1624  RstAMC_linkSync <= (others => '1');
1625  elsif(clk125'event and clk125 = '1')then
1626  rst_AMC_cntr <= resetCntr or RstAMC_linkSync(3);
1627  RstAMC_linkSync <= RstAMC_linkSync(2 downto 0) & '0';
1628  end if;
1629 end process;
1630 i_AMC_cntr : AMC_cntr PORT MAP (
1631  UsrClk => UsrClk ,
1632  clk125 => clk125 ,
1633  sysclk => sysclk ,
1634  ipb_clk => ipb_clk,
1635  resetCntr => rst_AMC_cntr,
1636  DB_cmd => DB_cmd ,
1637  AMC_if_data => AMC_if_data,
1638  Cntr_DATA => Cntr_DATA,
1639  Cntr_ADDR => Cntr_ADDR,
1640  ipb_addr => ipb_addr(15 downto 0),
1641  ipb_rdata => AMC_cntr_data
1642  );
1643 process(UsrClk,reset)
1644 begin
1645  if(reset = '1')then
1646  RxBufOvfErr <= (others => '0');
1647  RxBufUdfErr <= (others => '0');
1648  elsif(UsrClk'event and UsrClk = '1')then
1649  for i in 0 to 11 loop
1650  RxBufOvfErr(i) <= (RxBufOvfErr(i) or RxBufOvf(i)) and AMC_en(i) and not test;
1651  RxBufUdfErr(i) <= (RxBufUdfErr(i) or RxBufUdf(i)) and AMC_en(i) and not test;
1652  end loop;
1653  end if;
1654 end process;
1655 process(TTC_status, AMC_en)
1656 begin
1657  for i in 0 to 11 loop
1658  AMC_TTC_status(i) <= TTC_status(i)(0) and AMC_en(i);
1659  AMC_TTC_status(i+16) <= TTC_status(i)(1) and AMC_en(i);
1660  end loop;
1661 end process;
1662 TTC_lock <= and_reduce(AMC_TTC_status(27 downto 16) or not AMC_en);
1663 BC0_lock <= AMC_TTC_status(11 downto 0);
1664 AMC_TTC_status(31 downto 28) <= x"0";
1665 AMC_TTC_status(15 downto 12) <= x"0";
1666 process(ipb_clk)
1667 begin
1668  if(ipb_clk'event and ipb_clk = '1')then
1669  if(ipb_strobe = '1' and ipb_write = '1' and ipb_addr(14 downto 0) = MON_ctrl_addr(14 downto 0) and ipb_addr(27) = '0')then
1670  scale <= ipb_wdata;
1671  end if;
1672  ipb_strobe_q <= ipb_strobe;
1673  end if;
1674 end process;
1675 ipb_ack <= '0' when ipb_addr(27) = '1' or ipb_addr(15 downto 11) /= AMC_reg_addr(15 downto 11) or ipb_write = '1' else ipb_strobe;
1676 process(ipb_addr)
1677 begin
1678  if(ipb_addr(15 downto 9) = L1A_buf_addr(15 downto 9))then
1679  ipb_rdata <= L1A_buf_do;
1680  elsif(ipb_addr(14 downto 11) /= AMC_reg_addr(14 downto 11))then
1681  ipb_rdata <= (others => '0');
1682  else
1683  ipb_rdata <= AMC_cntr_data;
1684  end if;
1685 end process;
1686 AMC_status(31 downto 28) <= (others => '0');
1687 AMC_status(27 downto 16) <= AMC_data_valid or not AMC_en;
1688 AMC_status(15 downto 12) <= (others => '0');
1689 process(UsrClk)
1690 begin
1691  if(UsrClk'event and UsrClk = '1')then
1692  for i in 0 to 2 loop
1693  EventBuiltToggleSyncRegs(i) <= EventBuiltToggleSyncRegs(i)(2 downto 0) & EventBuiltToggle(i);
1694  end loop;
1695  for i in 0 to 11 loop
1696  badEventCRCToggleSyncRegs(i) <= badEventCRCToggleSyncRegs(i)(2 downto 0) & badEventCRCToggle(i);
1697  ReSyncFakeEventToggleSyncRegs(i) <= ReSyncFakeEventToggleSyncRegs(i)(2 downto 0) & ReSyncFakeEventToggle(i);
1698  end loop;
1699  if(CntrRst = '1')then
1700  badEventCRC_cntr <= (others => (others => '0'));
1701  ReSyncFakeEvent_cntr <= (others => (others => '0'));
1702  EventBuiltCnt <= (others => (others => '0'));
1703  fake_word_cnt <= (others => '0');
1704  fake_evt_cnt <= (others => '0');
1705  empty_evt_cnt <= (others => '0');
1706  fake_header_cnt <= (others => '0');
1707  else
1708  for i in 0 to 11 loop
1709  if(badEventCRCToggleSyncRegs(i)(3) /= badEventCRCToggleSyncRegs(i)(2))then
1710  badEventCRC_cntr(i) <= badEventCRC_cntr(i) + 1;
1711  end if;
1712  if(ReSyncFakeEventToggleSyncRegs(i)(3) /= ReSyncFakeEventToggleSyncRegs(i)(2))then
1713  ReSyncFakeEvent_cntr(i) <= ReSyncFakeEvent_cntr(i) + 1;
1714  end if;
1715  end loop;
1716  for i in 0 to 2 loop
1717  if(EventBuiltToggleSyncRegs(i)(3) /= EventBuiltToggleSyncRegs(i)(2))then
1718  EventBuiltCnt(i) <= EventBuiltCnt(i) + 1;
1719  end if;
1720  end loop;
1721  if(fake_WrEn = '1')then
1722  fake_word_cnt <= fake_word_cnt + 1;
1723  end if;
1724  if(fake_CRC = '1')then
1725  fake_evt_cnt <= fake_evt_cnt + 1;
1726  end if;
1727  if(fake_CRC = '1' and empty_event_flag = '1')then
1728  empty_evt_cnt <= empty_evt_cnt + 1;
1729  end if;
1730  if(fake_WrEn = '1' and fake_header = '1')then
1731  fake_header_cnt <= fake_header_cnt + 1;
1732  end if;
1733  end if;
1734  resetCntr_SyncRegs <= resetCntr_SyncRegs(1 downto 0) & resetCntr;
1735  CntrRst <= (not resetCntr_SyncRegs(2) and resetCntr_SyncRegs(1)) or RstAMC_link;
1736  end if;
1737 end process;
1738 i_AMC_refclk: IBUFDS_GTE2
1739  port map
1740  (
1741  O => AMC_REFCLK,
1742  ODIV2 => open,
1743  CEB => '0',
1744  I => AMC_REFCLK_P, -- Connect to package pin AB6
1745  IB => AMC_REFCLK_N -- Connect to package pin AB5
1746  );
1747 -- monitoring logic
1748 process(sysclk)
1749 begin
1750  if(sysclk'event and sysclk = '1')then
1751  if(resetSyncRegs(2) = '1')then
1752  errors <= (others => '0');
1753  stop_mon <= '0';
1754  else
1755  if(or_reduce(AMCCRC_bad(0)) = '1' or or_reduce(AMCCRC_bad(1)) = '1' or or_reduce(AMCCRC_bad(2)) = '1')then
1756  errors(7) <= '1';
1757  end if;
1758  if(or_reduce(errors and scale(31 downto 24)) = '1' and rst_init_bldr = '1' and LastBlock = '1')then
1759  stop_mon <= '1';
1760  end if;
1761  end if;
1762  case scale(22 downto 19) is
1763  when x"0" => mon_mask <= x"00000";
1764  when x"1" => mon_mask <= x"80000";
1765  when x"2" => mon_mask <= x"c0000";
1766  when x"3" => mon_mask <= x"e0000";
1767  when x"4" => mon_mask <= x"f0000";
1768  when x"5" => mon_mask <= x"f8000";
1769  when x"6" => mon_mask <= x"fc000";
1770  when x"7" => mon_mask <= x"fe000";
1771  when x"8" => mon_mask <= x"ff000";
1772  when x"9" => mon_mask <= x"ff800";
1773  when x"a" => mon_mask <= x"ffc00";
1774  when x"b" => mon_mask <= x"ffe00";
1775  when x"c" => mon_mask <= x"fff00";
1776  when x"d" => mon_mask <= x"fff80";
1777  when x"e" => mon_mask <= x"fffc0";
1778  when others => mon_mask <= x"fffe0";
1779  end case;
1780  if(CDF_Header = '1' and init_bldr = '1')then
1781  if(and_reduce(CDF_out(51 downto 32) or mon_mask) = '1')then
1782  sample_event <= '1';
1783  else
1784  sample_event <= '0';
1785  end if;
1786  end if;
1787  if(flavor = "G2" and enSFP(3) = '0' and enSFP(2 downto 0) /= "000")then
1788  mon_en <= '1';
1789  pending <= '0';
1790  elsif(resetSyncRegs(2) = '1')then
1791 -- After reset, the first event will always be recorded
1792  mon_en <= not scale(23);
1793  pending <= '0';
1794  elsif(rst_init_bldr = '1' and LastBlock = '1')then
1795  if(scale(23) = '1')then
1796  mon_en <= sample_event and (mon_buf_avl or WaitMonBuf) and not stop_mon;
1797  pending <= '0';
1798  else
1799  mon_en <= (mon_buf_avl or WaitMonBuf) and not stop_mon and (and_reduce(scale_cntr) or pending);
1800  pending <= not mon_buf_avl and (and_reduce(scale_cntr) or pending);
1801  end if;
1802  end if;
1803 -- if(resetSyncRegs(2) = '1')then
1804 -- start_wc_reg_wa <= (others => '0');
1805 -- elsif(FirstBlock(0) = '1' and ce_wc_reg_wa = '1')then
1806 -- start_wc_reg_wa <= wc_reg_wa;
1807 -- end if;
1808  if(resetSyncRegs(2) = '1' or rst_mon_wc = '1')then
1809  mon_wc(0) <= (others => '0');
1810  elsif(zero_wc(0) = '0' and (header = '1' or sel_CDF = '1' or (more_wc(0) = '0' and rst_init_bldr = '1')))then
1811  mon_wc(0) <= mon_wc(0) + 1;
1812  elsif(AMC_wc_we(0) = '1')then
1813  mon_wc(0) <= mon_wc(0) + ("000" & AMC_wc(12 downto 0)) + 1;
1814  end if;
1815  if(resetSyncRegs(2) = '1' or rst_mon_wc = '1')then
1816  mon_wc(1) <= (others => '0');
1817  elsif(zero_wc(1) = '0' and (header = '1' or sel_CDF = '1' or (more_wc(1) = '0' and rst_init_bldr = '1')))then
1818  mon_wc(1) <= mon_wc(1) + 1;
1819  elsif(AMC_wc_we(1) = '1')then
1820  mon_wc(1) <= mon_wc(1) + ("000" & AMC_wc(12 downto 0)) + 1;
1821  end if;
1822  if(resetSyncRegs(2) = '1' or rst_mon_wc = '1')then
1823  mon_wc(2) <= (others => '0');
1824  elsif(zero_wc(2) = '0' and (header = '1' or sel_CDF = '1' or (more_wc(2) = '0' and rst_init_bldr = '1')))then
1825  mon_wc(2) <= mon_wc(2) + 1;
1826  elsif(AMC_wc_we(2) = '1')then
1827  mon_wc(2) <= mon_wc(2) + ("000" & AMC_wc(12 downto 0)) + 1;
1828  end if;
1829  if(ce_scale = '1')then
1830  if(ld_scale = '1')then
1831  scale_cntr <= not scale(15 downto 0);
1832  else
1833  scale_cntr <= scale_cntr + 1;
1834  end if;
1835  end if;
1836  if(resetSyncRegs(2) = '1')then
1837  ce_scale <= '0';
1838  ld_scale <= '0';
1839  ce_wc_reg_wa <= '0';
1840 -- MonBufAbort <= '0';
1841  else
1842  ce_scale <= init_bldr and CDF_Header;
1843  ld_scale <= mon_en or pending;
1844  ce_wc_reg_wa <= rst_init_bldr and AMC_header(0)(64);
1845 -- MonBufAbort <= rst_init_bldr and mon_en and not AMC_header(0)(64);
1846  end if;
1847  rst_mon_wc <= rst_init_bldr;
1848  if(resetSyncRegs(2) = '1' or rst_mon_wc = '1')then
1849  en_block_wc <= (others => '0');
1850  else
1851  en_block_wc <= en_block_wc or amc_header_we;
1852  end if;
1853  for i in 0 to 2 loop
1854  block_wc_we(i) <= rst_init_bldr and en_block_wc(i);
1855  end loop;
1856  if(resetSyncRegs(2) = '1')then
1857  EventInfoRdDone <= (others => '0');
1858  elsif(sel_AMC = x"b")then
1859 -- EventInfoRdDone <= '1' & AMC_hasData_l;
1860  EventInfoRdDone <= '1' & AMC_hasData;
1861  else
1862  EventInfoRdDone <= (others => '0');
1863  end if;
1864  rst_init_bldr <= EventInfoRdDone(12);
1865  if(resetSyncRegs(2) = '1')then
1866  wc_reg_wa <= (others => '0');
1867 -- elsif(MonBufAbort = '1')then
1868 -- wc_reg_wa <= start_wc_reg_wa;
1869  elsif(ce_wc_reg_wa = '1')then
1870  wc_reg_wa <= wc_reg_wa + 1;
1871  end if;
1872  end if;
1873 end process;
1874 g_mon_evt_wc: for i in 0 to 2 generate
1875  i_mon_evt_wc : BRAM_SDP_MACRO
1876  generic map (
1877  BRAM_SIZE => "18Kb", -- Target BRAM, "18Kb" or "36Kb"
1878  DEVICE => "7SERIES", -- Target device: "VIRTEX5", "VIRTEX6", "7SERIES", "SPARTAN6"
1879  WRITE_WIDTH => 16, -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
1880  READ_WIDTH => 16, -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
1881  DO_REG => 0, -- Optional output register (0 or 1)
1882  SIM_COLLISION_CHECK => "NONE", -- Collision check enable "ALL", "WARNING_ONLY",
1883  -- "GENERATE_X_ONLY" or "NONE"
1884  WRITE_MODE => "WRITE_FIRST", -- Specify "READ_FIRST" for same clock or synchronous clocks
1885  -- Specify "WRITE_FIRST for asynchrononous clocks on ports
1886  INIT => X"000000000000000000") -- Initial values on output port
1887  port map (
1888  DO => mon_evt_wcp(i*16+15 downto i*16), -- Output read data port, width defined by READ_WIDTH parameter
1889  DI => mon_wc(i), -- Input write data port, width defined by WRITE_WIDTH parameter
1890  RDADDR => ddr_pa, -- Input read address, width defined by read port depth
1891  RDCLK => ipb_clk, -- 1-bit input read clock
1892  RDEN => '1', -- 1-bit input read port enable
1893  REGCE => '1', -- 1-bit input read output register enable
1894  RST => MonBuf_empty, -- 1-bit input reset
1895  WE => "11", -- Input write enable, width defined by write port depth
1896  WRADDR => wc_reg_wa, -- Input write address, width defined by write port depth
1897  WRCLK => sysclk, -- 1-bit input write clock
1898  WREN => ce_wc_reg_wa -- 1-bit input write port enable
1899  );
1900 end generate;
1901 mon_evt_wc(15 downto 0) <= mon_evt_wcp(15 downto 0) when OneSFP = '1' else mon_evt_wcp(31 downto 16);
1902 mon_evt_wc(31 downto 16) <= x"0000" when OneSFP = '1' else mon_evt_wcp(15 downto 0);
1903 mon_evt_wc(47 downto 32) <= mon_evt_wcp(47 downto 32);
1904 process(sysclk)
1905 begin
1906  if(sysclk'event and sysclk = '1')then
1907  ThreeSFP <= and_reduce(EnSFP(2 downto 0));
1908  if(EnSFP(2 downto 0) = "011" or EnSFP(2 downto 0) = "101" or EnSFP(2 downto 0) = "110")then
1909  TwoSFP <= '1';
1910  else
1911  TwoSFP <= '0';
1912  end if;
1913  if(EnSFP(2 downto 0) = "001" or EnSFP(2 downto 0) = "010" or EnSFP(2 downto 0) = "100" or EnSFP(2 downto 0) = "000")then
1914  OneSFP <= '1';
1915  else
1916  OneSFP <= '0';
1917  end if;
1918  end if;
1919 end process;
1920 i_FIFO_RESET_7S: FIFO_RESET_7S PORT MAP(
1921  reset => resetFIFO,
1922  clk => sysclk ,
1923  fifo_rst => fifo_rst,
1924  fifo_en => fifo_en
1925  );
1926 resetFIFO <= reset or or_reduce(not AMC_txfsmresetdone and AMC_en);
1927 process(sysclk)
1928 begin
1929  if(sysclk'event and sysclk = '1')then
1930  if(resetSyncRegs(2) = '1')then
1931  rst_AMC_wc_sum <= '1';
1932  wr_AMC_wc_sum <= '0';
1933  else
1934  if(wr_AMC_wc_sum = '1' and ec_sel_AMC = '0')then
1935  rst_AMC_wc_sum <= '0';
1936  end if;
1937  wr_AMC_wc_sum <= ec_sel_AMC;
1938  end if;
1939  sel_AMC_q <= sel_AMC;
1940  end if;
1941 end process;
1942 i_AMC_wc_sum: RAM32x6Db PORT MAP(
1943  wclk => sysclk ,
1944  di => AMC_wc_sum_di,
1945  we => AMC_wc_sum_we,
1946  wa => AMC_wc_sum_a,
1947  ra => AMC_wc_sum_a,
1948  do => AMC_wc_sum_do
1949  );
1950 AMC_wc_sum_di <= AMC_wc_sum_do + AMC_wc(5 downto 0) when rst_AMC_wc_sum = '0' else AMC_wc(5 downto 0);
1951 AMC_wc_sum_a(3 downto 0) <= sel_AMC_q when wr_AMC_wc_sum = '1' else AMC_if_ADDR(4 downto 1);
1952 end Behavioral;
1953 
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