Behavioral Architecture Reference

List of all members.

Processes
PROCESS_325	( UsrClk )
PROCESS_326	( UsrClk ,BC0_lock )
PROCESS_327	( UsrClk )
PROCESS_328	( UsrClk )
PROCESS_329	( UsrClk ,RxResetDone )
PROCESS_330	( UsrClk ,reset ,RxResetDone ,txfsmresetdone ,qpll_lock )
PROCESS_331	( UsrClk )
PROCESS_332	( UsrClk )
PROCESS_333	( UsrClk )
PROCESS_334	( UsrClk )
PROCESS_335	( UsrClk )
PROCESS_336	( UsrClk )
PROCESS_337	( UsrClk )
PROCESS_338	( sysclk ,resetCntr )
PROCESS_339	( sysclk ,InitLink )
PROCESS_340	( UsrClk )

Components
HammingDecode	<Entity HammingDecode>
crc16D16	<Entity crc16D16>
EthernetCRCD16B	<Entity EthernetCRCD16B>
AMC_DATA_FIFO	<Entity AMC_DATA_FIFO>
TTC_trigger	<Entity TTC_trigger>

Constants
Acknowledge	std_logic_vector ( 7 downto 0 ) := x " 12 "
data	std_logic_vector ( 7 downto 0 ) := x " 34 "
InitRqst	std_logic_vector ( 7 downto 0 ) := x " 56 "
Counter	std_logic_vector ( 7 downto 0 ) := x " 78 "
K_word	std_logic_vector ( 15 downto 0 ) := x " 3cbc "
R_word	std_logic_vector ( 15 downto 0 ) := x " dcfb "
eof_word	std_logic_vector ( 15 downto 0 ) := x " 5cf7 "
IDLE	std_logic_vector ( 3 downto 0 ) := x " 0 "
SendK	std_logic_vector ( 3 downto 0 ) := x " 1 "
SendType	std_logic_vector ( 3 downto 0 ) := x " 2 "
SendSEQ	std_logic_vector ( 3 downto 0 ) := x " 3 "
SendWC	std_logic_vector ( 3 downto 0 ) := x " 4 "
WaitCRC	std_logic_vector ( 3 downto 0 ) := x " 5 "
SendCRC	std_logic_vector ( 3 downto 0 ) := x " 6 "
SendData	std_logic_vector ( 3 downto 0 ) := x " 7 "

Signals
AMCRdy	std_logic := ' 0 '
AMC_IDp1	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
AMC_IDp4	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
TxState	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
InitLink	std_logic := ' 0 '
RxResetDoneSyncRegs	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
RXDATA_q	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
TXDATA_i	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
reset_SyncRegs	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
fake_evn	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
sgl_err	std_logic := ' 0 '
dbl_err	std_logic := ' 0 '
sel_TTC	std_logic := ' 0 '
is_TTS	std_logic := ' 0 '
update_TTS	std_logic := ' 0 '
SendTTS	std_logic := ' 0 '
TTS_in	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
TTS_tmp	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
TTS	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
TTS_coded_i	std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
TTS_valid	std_logic := ' 0 '
TTC_lock	std_logic := ' 0 '
BC0_lock	std_logic := ' 0 '
BcntMm	std_logic := ' 0 '
BC0_link	std_logic := ' 0 '
BC0_matchCntr	std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )
TTC_missingCntr	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
HammingOutValid	std_logic := ' 0 '
bcnt_link	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
ec_delta_BC0	std_logic := ' 0 '
delta_BC0	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
MmCntr	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
TTC_DataValid	std_logic := ' 0 '
TTC_Data	std_logic_vector ( 23 downto 0 ) := ( others = > ' 0 ' )
TTC_FIFO_we	std_logic := ' 0 '
HammingOut	std_logic_vector ( 17 downto 0 ) := ( others = > ' 0 ' )
TTC_FIFO_Di	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
TTC_FIFO_Do	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
TTC_FIFO_Do_dl	std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )
TTC_FIFO_DoValid	std_logic := ' 0 '
TTC_FIFO_wa	std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
TTC_FIFO_wa0_SyncRegs	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
TTC_FIFO_ra	std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
BC0_offset	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
check_packet	std_logic := ' 0 '
ACK	std_logic := ' 0 '
Abort	std_logic := ' 0 '
CntrAbort	std_logic := ' 0 '
bad_K	std_logic := ' 0 '
SEQ_OK	std_logic := ' 0 '
CRC_OK	std_logic := ' 0 '
frame_OK	std_logic := ' 0 '
ACK_OK	std_logic := ' 0 '
WC_OKp	std_logic := ' 0 '
WC_OK	std_logic := ' 0 '
TypeInit	std_logic := ' 0 '
TypeACK	std_logic := ' 0 '
TypeData	std_logic := ' 0 '
TypeData_q	std_logic := ' 0 '
TypeCntr	std_logic := ' 0 '
Receiving	std_logic := ' 0 '
Receiving_q	std_logic := ' 0 '
Header2	std_logic := ' 0 '
IsACK	std_logic := ' 0 '
ACKNUM_full	std_logic := ' 0 '
ACKNUM_empty	std_logic := ' 0 '
ACKNUM_IN	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
RxSEQNUM	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
SEQNUM	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
NextSEQNUM	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
ACKNUM	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
CntrACKNUM	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
ACKNUM_MUX	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
ACKNUM_l	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
ACKNUM_a	std_logic_vector ( 1 downto 0 ) := ( others = > ' 1 ' )
RxType	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
RxWC	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
LinkVersion	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
accept	std_logic := ' 0 '
CntrAccept	std_logic := ' 0 '
we_ACKNUM	std_logic := ' 0 '
save_start_addr	std_logic := ' 0 '
eof	std_logic := ' 0 '
got_eof	std_logic := ' 0 '
fake_got_eof	std_logic := ' 0 '
BOE	std_logic := ' 0 '
AMCinfo_word	std_logic := ' 0 '
saved_BOE	std_logic := ' 0 '
dl_cntr	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
we_rfifo	std_logic := ' 0 '
rfifo	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
rfifo_a	std_logic_vector ( 1 downto 0 ) := ( others = > ' 1 ' )
EventBuf_ovf	std_logic := ' 0 '
EventBuf_full	std_logic := ' 0 '
ec_EventBuf_ra	std_logic := ' 0 '
ec_EventBuf_ra_q	std_logic := ' 0 '
evn_word	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
get_evn	std_logic := ' 0 '
evn_OK	std_logic_vector ( 5 downto 0 ) := ( others = > ' 0 ' )
evn	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
LengthMatch	std_logic := ' 0 '
UnknownLength	std_logic := ' 0 '
bad_EventLength	std_logic := ' 0 '
bad_AMCCRC	std_logic := ' 0 '
InitAMCCRC	std_logic := ' 0 '
AMCCRC	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
EventBuf_we	std_logic_vector ( 0 downto 0 ) := ( others = > ' 0 ' )
EventBuf_start	std_logic_vector ( 12 downto 0 ) := ( others = > ' 0 ' )
EventBuf_wa	std_logic_vector ( 12 downto 0 ) := ( others = > ' 0 ' )
EventBuf_ra	std_logic_vector ( 10 downto 0 ) := ( others = > ' 0 ' )
EventBuf_wc	std_logic_vector ( 10 downto 0 ) := ( others = > ' 0 ' )
EventBuf_space	std_logic_vector ( 10 downto 0 ) := ( others = > ' 0 ' )
EventBuf_Di	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
EventBuf_Do	std_logic_vector ( 63 downto 0 ) := ( others = > ' 0 ' )
EventWC	std_logic_vector ( 19 downto 0 ) := ( others = > ' 0 ' )
EventWC_tmp	std_logic_vector ( 19 downto 0 ) := ( others = > ' 0 ' )
AMCinfoDi	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
EventInfoDi	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
EventInfoDo	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
EventInfo_a	std_logic_vector ( 3 downto 0 ) := ( others = > ' 1 ' )
EventInfo_ovfl	std_logic_vector ( 1 downto 0 ) := ( others = > ' 1 ' )
EventInfoToggleSyncRegs	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
EventInfo_full	std_logic := ' 0 '
EventInfo_dav_i	std_logic := ' 0 '
we_EventInfo	std_logic := ' 0 '
end_of_block	std_logic := ' 0 '
end_of_event	std_logic := ' 0 '
EventInfoToggle	std_logic := ' 0 '
EventInfoToggle_q	std_logic := ' 0 '
re_EventInfo	std_logic := ' 0 '
EventInfoRdDoneToggle	std_logic := ' 0 '
EventInfoRdDoneToggleSyncRegs	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
we_RxCRC	std_logic := ' 0 '
Init_RxCRC	std_logic := ' 0 '
RxCRC	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
L1Ainfo_we	std_logic_vector ( 0 downto 0 ) := ( others = > ' 0 ' )
L1Ainfo_wa	std_logic_vector ( 9 downto 0 ) := ( others = > ' 0 ' )
L1Ainfo_ra	std_logic_vector ( 9 downto 0 ) := ( others = > ' 0 ' )
L1Ainfo_start	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
L1AinfoDo	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
L1Ainfo_wa2SyncRegs	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
L1Ainfo_wap	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
ec_L1Ainfo_ra	std_logic := ' 0 '
re_L1AinfoDo	std_logic := ' 0 '
L1Ainfo_empty	std_logic := ' 0 '
timer	std_logic_vector ( N downto 0 ) := ( others = > ' 0 ' )
ReSend	std_logic := ' 0 '
ReSend_l	std_logic := ' 0 '
ReSendQueIn	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
ReSendQueOut	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
we_ReSendQue	std_logic := ' 0 '
ReSendQue_a	std_logic_vector ( 1 downto 0 ) := ( others = > ' 1 ' )
ReSendQue_empty	std_logic := ' 0 '
ReSendQue_full	std_logic := ' 0 '
got_comma	std_logic := ' 0 '
GotCntr	std_logic := ' 0 '
L1Asent	std_logic := ' 0 '
TxType	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
packet_wc	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
we_TxCRC	std_logic := ' 0 '
Init_TxCRC	std_logic := ' 0 '
TxCRC	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
TxIsK	std_logic := ' 0 '
Cntr_RdEn	std_logic := ' 0 '
we_CntrBuf	std_logic := ' 0 '
CntrBuf_Di	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
CntrBuf_Do	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
CntrBuf_wa	std_logic_vector ( 5 downto 0 ) := ( others = > ' 0 ' )
CntrBuf_ra	std_logic_vector ( 5 downto 0 ) := ( others = > ' 0 ' )
we_CntrBuf2p	std_logic := ' 0 '
we_CntrBuf2	std_logic := ' 0 '
CntrBuf2_Di	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
CntrBuf2_SPO	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
CntrBuf2_SPO_q	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
CntrBuf2_Do	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
CntrBuf2_wa	std_logic_vector ( 5 downto 0 ) := ( others = > ' 0 ' )
resetCntrCycle	std_logic := ' 0 '
CntrBuf_valid	std_logic := ' 0 '
cntrs	std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
sglErrCntr	std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
dblErrCntr	std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
BC0mmCntr	std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
BcntMmCntr	std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
ResendCntr	std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
AcceptCntr	std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
CntrAcceptCntr	std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
TotalWordCntr	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
ACKcntr	std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
AbortCntr	std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
RxEventCntr	std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
RdEventCntr	std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
DataAbortCntr	std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
CntrAbortCntr	std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
BUSYCntr	std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
EvtEVNmmCntr	std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
EvtBCNmmCntr	std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
EvtOCNmmCntr	std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
ACKNUM_fullAbortCntr	std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
EventInfo_fullAbortCntr	std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
EventBuf_fullAbortCntr	std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
SEQAbortCntr	std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
CRCAbortCntr	std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
frameAbortCntr	std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
bad_KAbortCntr	std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
bad_EventLengthCntr	std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
BlockCntr	std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
badCRCCntr	std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
TTSCntr	std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
TTCCntr	std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
TTS_ERRcntr	std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
TTS_DCcntr	std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
TTS_OOScntr	std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
TTS_BSYcntr	std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
TTS_OFWcntr	std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
WordCntr	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
WordCntr_q	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
AllZero	std_logic := ' 0 '
zeroWordCntr	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
Cntr_ra	std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )
TTS_wa	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
TTS_wa0_SyncRegs	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
TTS_wa1_SyncRegs	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
TTS_InvalidCntr	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
TTS_UpdateCntr	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
RxNotInTableCntr	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
EofMissingCntr	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
WC11p	std_logic := ' 0 '
WC11	std_logic := ' 0 '
RxNotInTableErr	std_logic := ' 0 '
fake_CRC_q	std_logic := ' 0 '
fake_CRC_q2	std_logic := ' 0 '
AMCCRC_q	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
AMC_DATA_full	std_logic := ' 0 '
AMC_DATA_WrEn	std_logic := ' 0 '
AMC_DATA_Di	std_logic_vector ( 63 downto 0 ) := ( others = > ' 0 ' )
WRERR	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
RDERR	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
RDCOUNT	array8x12
WRCOUNT	array8x12
block32K	std_logic := ' 0 '
EventWC_carry	std_logic := ' 0 '
LengthInHeader	std_logic_vector ( 19 downto 0 ) := ( others = > ' 0 ' )
LengthInTrailer	std_logic_vector ( 19 downto 0 ) := ( others = > ' 0 ' )
Ready_i	std_logic := ' 0 '
TTS_wait	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
TTS_DC_cntr	std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
TTS_SL_cntr	std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
TTS_ERR_cntr	std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
critical_TTS	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
critical_TTS_cntr	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
GotMismatch	std_logic := ' 0 '
FirstMismatch	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
LiveTime	std_logic_vector ( 7 downto 0 ) := ( others = > ' 0 ' )
LiveTimeCntr	std_logic_vector ( 18 downto 0 ) := ( others = > ' 0 ' )

Instantiations
i_TTC_trigger	TTC_trigger <Entity TTC_trigger>
i_HammingDecode	HammingDecode <Entity HammingDecode>
i_RxCRC	crc16D16 <Entity crc16D16>
i_AMCCRC	EthernetCRCD16B <Entity EthernetCRCD16B>
i_AMC_DATA	AMC_DATA_FIFO <Entity AMC_DATA_FIFO>
i_TxCRC	crc16D16 <Entity crc16D16>

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Detailed Description

Definition at line 103 of file AMC_Link.vhd.

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The documentation for this class was generated from the following files:

• src/common/AMC_if/AMC_Link.vhd