AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
 All Classes Variables
AMC_Link.vhd
1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 15:55:15 07/09/2010
6 -- Design Name:
7 -- Module Name: AMC_Link - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 ----------------------------------------------------------------------------------
19 library IEEE;
20 use IEEE.STD_LOGIC_1164.ALL;
21 use IEEE.STD_LOGIC_ARITH.ALL;
22 use IEEE.STD_LOGIC_UNSIGNED.ALL;
23 use IEEE.std_logic_misc.all;
24 use work.amc13_pack.all;
25 
26 -- Uncomment the following library declaration if using
27 -- arithmetic functions with Signed or Unsigned values
28 --use IEEE.NUMERIC_STD.ALL;
29 
30 -- Uncomment the following library declaration if instantiating
31 -- any Xilinx primitives in this code.
32 library UNISIM;
33 use UNISIM.VComponents.all;
34 Library UNIMACRO;
35 use UNIMACRO.vcomponents.all;
36 
37 entity AMC_Link is
38  generic(N : integer := 14; simulation : boolean := false); -- M controls FIFO size, N controls timeout
39  port(
40  sysclk : in std_logic; -- 200MHz
41  reset : in std_logic;
42  resetCntr : in std_logic;
43  fifo_rst : in std_logic;
44  fifo_en : in std_logic;
45  test : in std_logic;
46  strobe2ms : in std_logic;
47  NoReSyncFake : in std_logic;
48  UsrClk : in std_logic;
49  Ready : out std_logic; -- Link to AMC established
50  AMC_ID : in STD_LOGIC_VECTOR(3 downto 0);
51  txfsmresetdone : in std_logic;
52  RxResetDone : in std_logic;
53  qpll_lock : in std_logic;
54  rxcommaalignen : out std_logic;
55  DATA_VALID : out std_logic;
56  RXDATA : in std_logic_vector(15 downto 0);
57  RXCHARISCOMMA : in std_logic_vector(1 downto 0);
58  RXCHARISK : in std_logic_vector(1 downto 0);
59  RXNOTINTABLE : in std_logic_vector(1 downto 0);
60  TXDATA : out std_logic_vector(15 downto 0);
61  TXCHARISK : out std_logic_vector(1 downto 0);
62 -------------
63  AMCinfo : out std_logic_vector(15 downto 0);
64  EventInfo : out std_logic_vector(31 downto 0);
65  EventInfo_dav : out std_logic;
66  AMC_en : in std_logic;
67  AMC_DATA_RdEn : in std_logic; -- enable reading AMC event
68  EventInfoRdDone : in std_logic; -- end of reading AMC event
69  AMC_DATA : out std_logic_vector(63 downto 0);
70  L1A_DATA : in std_logic_vector(15 downto 0);
71  L1A_WrEn : in std_logic;
72  fake_header : in std_logic;
73  fake_CRC : in std_logic;
74  fake_DATA : in std_logic_vector(15 downto 0);
75 -- fake_evn : in std_logic_vector(3 downto 0);
76  fake_WrEn : in std_logic;
77  fake_full : out std_logic;
78 -- fake_accept : in std_logic;
79  bad_AMC : out std_logic;
80  AMC_OK : out std_logic;
81 -- scan counters
82 -- Cntr_RdEn : in std_logic;
83 -- Cntr_RdEnp : in std_logic;
84  Cntr_ADDR : in std_logic_vector(11 downto 0);
85  Cntr_DATA : out std_logic_vector(15 downto 0);
86 -- ipbus read signals
87 -- ipb_addr : in std_logic_vector(15 downto 0);
88 -- ipb_rdata : out std_logic_vector(31 downto 0);
89  debug_out : out std_logic_vector(255 downto 0);
90 -- TTC & TTS signals
91  TTCclk : in std_logic;
92  BC0 : in std_logic; -- AMC13 BC0 delayed by four TTC_clk cycles
93  TTC_LOS : in std_logic;
94  TTS_disable : in std_logic;
95  TTC_status : out std_logic_vector(127 downto 0);
96  TrigData : out std_logic_vector(7 downto 0);
97 -- TTS is in the UsrClk domain
98  TTS_RQST : out std_logic_vector(2 downto 0);
99  TTS_coded : out std_logic_vector(4 downto 0)-- Disconnected, Error, Sync Lost, Busy and Overflow Warning
100  );
101 end AMC_Link;
102 
103 architecture Behavioral of AMC_Link is
104 COMPONENT HammingDecode
105  PORT(
106  clk : IN std_logic;
107  din_valid : IN std_logic;
108  din : IN std_logic_vector(23 downto 0);
109  dout_valid : OUT std_logic;
110  dout : OUT std_logic_vector(17 downto 0);
111  sgl_err : OUT std_logic;
112  dbl_err : OUT std_logic
113  );
114 END COMPONENT;
115 COMPONENT crc16D16
116  PORT(
117  clk : IN std_logic;
118  init_crc : IN std_logic;
119  we_crc : IN std_logic;
120  d : IN std_logic_vector(15 downto 0);
121  crc : OUT std_logic_vector(15 downto 0)
122  );
123 END COMPONENT;
124 COMPONENT EthernetCRCD16B
125  PORT(
126  clk : IN std_logic;
127  init : IN std_logic;
128  save : IN std_logic;
129  restore : IN std_logic;
130  ce : IN std_logic;
131  d : IN std_logic_vector(15 downto 0);
132  crc : OUT std_logic_vector(31 downto 0);
133  bad_crc : OUT std_logic
134  );
135 END COMPONENT;
136 COMPONENT AMC_DATA_FIFO
137  PORT(
138  wclk : IN std_logic;
139  rclk : IN std_logic;
140  reset : IN std_logic;
141  fifo_en : IN std_logic;
142  we : IN std_logic;
143  re : IN std_logic;
144  Di : IN std_logic_vector(63 downto 0);
145  Do : OUT std_logic_vector(63 downto 0);
146  WRERR_OUT : OUT std_logic_vector(7 downto 0);
147  RDERR_OUT : OUT std_logic_vector(7 downto 0);
148  full : OUT std_logic
149  );
150 END COMPONENT;
151 COMPONENT TTC_trigger
152  generic(simulation : boolean := false);
153  PORT(
154  reset : IN std_logic;
155  UsrClk : IN std_logic;
156  TTCclk : IN std_logic;
157  HammingData_in : IN std_logic_vector(17 downto 0);
158  HammingDataValid : IN std_logic;
159  BC0 : IN std_logic;
160  BcntMm : OUT std_logic;
161  TTC_lock : OUT std_logic;
162  BC0_lock : OUT std_logic;
163  TrigData : OUT std_logic_vector(7 downto 0)
164  );
165 END COMPONENT;
166 constant Acknowledge : std_logic_vector(7 downto 0) := x"12";
167 constant data : std_logic_vector(7 downto 0) := x"34";
168 constant InitRqst : std_logic_vector(7 downto 0) := x"56";
169 constant Counter : std_logic_vector(7 downto 0) := x"78";
170 constant K_word : std_logic_vector(15 downto 0) := x"3cbc"; -- sequence K28.5 K28.1
171 constant R_word : std_logic_vector(15 downto 0) := x"dcfb"; -- sequence K27.7 K28.6
172 constant eof_word : std_logic_vector(15 downto 0) := x"5cf7"; -- sequence K23.7 K28.2
173 constant IDLE : std_logic_vector(3 downto 0) := x"0"; -- TxState
174 constant SendK : std_logic_vector(3 downto 0) := x"1"; -- TxState sending comma
175 constant SendType : std_logic_vector(3 downto 0) := x"2"; -- TxState sending event data words
176 constant SendSEQ : std_logic_vector(3 downto 0) := x"3"; -- TxState sending sequence number
177 constant SendWC : std_logic_vector(3 downto 0) := x"4"; -- TxState sending payload word count
178 constant WaitCRC : std_logic_vector(3 downto 0) := x"5"; -- TxState same as IDLE
179 constant SendCRC : std_logic_vector(3 downto 0) := x"6"; -- TxState sending CRC
180 constant SendData : std_logic_vector(3 downto 0) := x"7"; -- TxState sending event data words
181 signal AMCRdy : std_logic := '0';
182 signal AMC_IDp1: std_logic_vector(3 downto 0) := (others => '0');
183 signal AMC_IDp4: std_logic_vector(3 downto 0) := (others => '0');
184 signal TxState: std_logic_vector(3 downto 0) := (others => '0');
185 signal InitLink : std_logic := '0';
186 signal RxResetDoneSyncRegs : std_logic_vector(2 downto 0) := (others => '0');
187 signal RXDATA_q : std_logic_vector(15 downto 0) := (others => '0');
188 signal TXDATA_i : std_logic_vector(15 downto 0) := (others => '0');
189 signal reset_SyncRegs : std_logic_vector(3 downto 0) := (others => '0');
190 signal fake_evn : std_logic_vector(3 downto 0) := (others => '0');
191 signal sgl_err : std_logic := '0';
192 signal dbl_err : std_logic := '0';
193 signal sel_TTC : std_logic := '0';
194 signal is_TTS : std_logic := '0';
195 signal update_TTS : std_logic := '0';
196 signal SendTTS : std_logic := '0';
197 signal TTS_in : std_logic_vector(3 downto 0) := (others => '0');
198 signal TTS_tmp : std_logic_vector(7 downto 0) := (others => '0');
199 signal TTS : std_logic_vector(7 downto 0) := (others => '0');
200 signal TTS_coded_i : std_logic_vector(4 downto 0) := (others => '0');
201 signal TTS_valid : std_logic := '0';
202 signal TTC_lock : std_logic := '0';
203 signal BC0_lock : std_logic := '0';
204 signal BcntMm : std_logic := '0';
205 signal BC0_link : std_logic := '0';
206 signal BC0_matchCntr : std_logic_vector(8 downto 0) := (others => '0');
207 signal TTC_missingCntr : std_logic_vector(3 downto 0) := (others => '0');
208 signal HammingOutValid : std_logic := '0';
209 signal bcnt_link : std_logic_vector(11 downto 0) := (others => '0');
210 signal ec_delta_BC0 : std_logic := '0';
211 signal delta_BC0 : std_logic_vector(3 downto 0) := (others => '0');
212 signal MmCntr : std_logic_vector(3 downto 0) := (others => '0');
213 signal TTC_DataValid : std_logic := '0';
214 signal TTC_Data : std_logic_vector(23 downto 0) := (others => '0');
215 signal TTC_FIFO_we : std_logic := '0';
216 signal HammingOut : std_logic_vector(17 downto 0) := (others => '0');
217 signal TTC_FIFO_Di : std_logic_vector(11 downto 0) := (others => '0');
218 signal TTC_FIFO_Do : std_logic_vector(11 downto 0) := (others => '0');
219 signal TTC_FIFO_Do_dl : std_logic_vector(8 downto 0) := (others => '0');
220 signal TTC_FIFO_DoValid : std_logic := '0';
221 signal TTC_FIFO_wa : std_logic_vector(4 downto 0) := (others => '0');
222 signal TTC_FIFO_wa0_SyncRegs : std_logic_vector(2 downto 0) := (others => '0');
223 signal TTC_FIFO_ra : std_logic_vector(4 downto 0) := (others => '0');
224 signal BC0_offset : std_logic_vector(3 downto 0) := (others => '0');
225 signal check_packet : std_logic := '0';
226 signal ACK : std_logic := '0';
227 signal Abort : std_logic := '0';
228 signal CntrAbort : std_logic := '0';
229 signal bad_K : std_logic := '0';
230 signal SEQ_OK : std_logic := '0';
231 signal CRC_OK : std_logic := '0';
232 signal frame_OK : std_logic := '0';
233 signal ACK_OK : std_logic := '0';
234 signal WC_OKp : std_logic := '0';
235 signal WC_OK : std_logic := '0';
236 signal TypeInit : std_logic := '0';
237 signal TypeACK : std_logic := '0';
238 signal TypeData : std_logic := '0';
239 signal TypeData_q : std_logic := '0';
240 signal TypeCntr : std_logic := '0';
241 signal Receiving : std_logic := '0';
242 signal Receiving_q : std_logic := '0';
243 signal Header2 : std_logic := '0';
244 signal IsACK : std_logic := '0';
245 signal ACKNUM_full : std_logic := '0';
246 signal ACKNUM_empty : std_logic := '0';
247 signal ACKNUM_IN : std_logic_vector(7 downto 0) := (others => '0');
248 signal RxSEQNUM : std_logic_vector(7 downto 0) :=(others => '0');
249 signal SEQNUM : std_logic_vector(7 downto 0) :=(others => '0');
250 signal NextSEQNUM : std_logic_vector(7 downto 0) :=(others => '0');
251 signal ACKNUM : std_logic_vector(7 downto 0) := (others => '0');
252 signal CntrACKNUM : std_logic_vector(7 downto 0) := (others => '0');
253 signal ACKNUM_MUX : std_logic_vector(7 downto 0) := (others => '0');
254 signal ACKNUM_l : std_logic_vector(7 downto 0) := (others => '0');
255 signal ACKNUM_a : std_logic_vector(1 downto 0) := (others => '1');
256 signal RxType : std_logic_vector(15 downto 0) := (others => '0');
257 signal RxWC : std_logic_vector(11 downto 0) := (others => '0');
258 signal LinkVersion : std_logic_vector(7 downto 0) := (others => '0');
259 signal accept : std_logic := '0';
260 signal CntrAccept : std_logic := '0';
261 signal we_ACKNUM : std_logic := '0';
262 signal save_start_addr : std_logic := '0';
263 signal eof : std_logic := '0';
264 signal got_eof : std_logic := '0';
265 signal fake_got_eof : std_logic := '0';
266 signal BOE : std_logic := '0';
267 signal AMCinfo_word : std_logic := '0';
268 signal saved_BOE : std_logic := '0';
269 signal dl_cntr : std_logic_vector(2 downto 0) := (others => '0');
270 signal we_rfifo : std_logic := '0';
271 signal rfifo : std_logic_vector(15 downto 0) := (others => '0');
272 signal rfifo_a : std_logic_vector(1 downto 0) := (others => '1');
273 signal EventBuf_ovf : std_logic := '0';
274 signal EventBuf_full : std_logic := '0';
275 signal ec_EventBuf_ra : std_logic := '0';
276 signal ec_EventBuf_ra_q : std_logic := '0';
277 signal evn_word : std_logic_vector(2 downto 0) := (others => '0');
278 signal get_evn : std_logic := '0';
279 signal evn_OK : std_logic_vector(5 downto 0) := (others => '0');
280 signal evn : std_logic_vector(7 downto 0) := (others => '0');
281 signal LengthMatch : std_logic := '0';
282 signal UnknownLength : std_logic := '0';
283 signal bad_EventLength : std_logic := '0';
284 signal bad_AMCCRC : std_logic := '0';
285 signal InitAMCCRC : std_logic := '0';
286 signal AMCCRC : std_logic_vector(31 downto 0) := (others => '0');
287 signal EventBuf_we : std_logic_vector(0 downto 0) := (others => '0');
288 signal EventBuf_start : std_logic_vector(12 downto 0) := (others => '0');
289 signal EventBuf_wa : std_logic_vector(12 downto 0) := (others => '0');
290 signal EventBuf_ra : std_logic_vector(10 downto 0) := (others => '0');
291 signal EventBuf_wc : std_logic_vector(10 downto 0) := (others => '0');
292 signal EventBuf_space : std_logic_vector(10 downto 0) := (others => '0');
293 signal EventBuf_Di : std_logic_vector(15 downto 0) := (others => '0');
294 signal EventBuf_Do : std_logic_vector(63 downto 0) := (others => '0');
295 signal EventWC : std_logic_vector(19 downto 0) := (others => '0');
296 signal EventWC_tmp : std_logic_vector(19 downto 0) := (others => '0');
297 signal AMCinfoDi : std_logic_vector(15 downto 0) := (others => '0');
298 signal EventInfoDi : std_logic_vector(31 downto 0) := (others => '0');
299 signal EventInfoDo : std_logic_vector(31 downto 0) := (others => '0');
300 signal EventInfo_a : std_logic_vector(3 downto 0) := (others => '1');
301 signal EventInfo_ovfl : std_logic_vector(1 downto 0) := (others => '1');
302 signal EventInfoToggleSyncRegs : std_logic_vector(3 downto 0) := (others => '0');
303 signal EventInfo_full : std_logic := '0';
304 signal EventInfo_dav_i : std_logic := '0';
305 signal we_EventInfo : std_logic := '0';
306 signal end_of_block : std_logic := '0';
307 signal end_of_event : std_logic := '0';
308 signal EventInfoToggle : std_logic := '0';
309 signal EventInfoToggle_q : std_logic := '0';
310 signal re_EventInfo : std_logic := '0';
311 signal EventInfoRdDoneToggle : std_logic := '0';
312 signal EventInfoRdDoneToggleSyncRegs : std_logic_vector(3 downto 0) := (others => '0');
313 signal we_RxCRC : std_logic := '0';
314 signal Init_RxCRC : std_logic := '0';
315 signal RxCRC : std_logic_vector(15 downto 0) := (others => '0');
316 signal L1Ainfo_we : std_logic_vector(0 downto 0) := (others => '0');
317 signal L1Ainfo_wa : std_logic_vector(9 downto 0) := (others => '0');
318 signal L1Ainfo_ra : std_logic_vector(9 downto 0) := (others => '0');
319 signal L1Ainfo_start : std_logic_vector(7 downto 0) := (others => '0');
320 signal L1AinfoDo : std_logic_vector(15 downto 0) := (others => '0');
321 signal L1Ainfo_wa2SyncRegs : std_logic_vector(3 downto 0) := (others => '0');
322 signal L1Ainfo_wap : std_logic_vector(7 downto 0) := (others => '0');
323 signal ec_L1Ainfo_ra : std_logic := '0';
324 signal re_L1AinfoDo : std_logic := '0';
325 signal L1Ainfo_empty : std_logic := '0';
326 signal timer : std_logic_vector(N downto 0) := (others => '0');
327 signal ReSend : std_logic := '0';
328 signal ReSend_l : std_logic := '0';
329 signal ReSendQueIn : std_logic_vector(15 downto 0) := (others => '0');
330 signal ReSendQueOut : std_logic_vector(15 downto 0) := (others => '0');
331 signal we_ReSendQue : std_logic := '0';
332 signal ReSendQue_a : std_logic_vector(1 downto 0) := (others => '1');
333 signal ReSendQue_empty : std_logic := '0';
334 signal ReSendQue_full : std_logic := '0';
335 signal got_comma : std_logic := '0';
336 signal GotCntr : std_logic := '0';
337 signal L1Asent : std_logic := '0';
338 signal TxType : std_logic_vector(7 downto 0) := (others => '0');
339 signal packet_wc : std_logic_vector(1 downto 0) := (others => '0');
340 signal we_TxCRC : std_logic := '0';
341 signal Init_TxCRC : std_logic := '0';
342 signal TxCRC : std_logic_vector(15 downto 0) := (others => '0');
343 signal TxIsK : std_logic := '0';
344 signal Cntr_RdEn : std_logic := '0';
345 signal we_CntrBuf : std_logic := '0';
346 signal CntrBuf_Di : std_logic_vector(15 downto 0) := (others => '0');
347 signal CntrBuf_Do : std_logic_vector(15 downto 0) := (others => '0');
348 signal CntrBuf_wa : std_logic_vector(5 downto 0) := (others => '0');
349 signal CntrBuf_ra : std_logic_vector(5 downto 0) := (others => '0');
350 signal we_CntrBuf2p : std_logic := '0';
351 signal we_CntrBuf2 : std_logic := '0';
352 signal CntrBuf2_Di : std_logic_vector(15 downto 0) := (others => '0');
353 signal CntrBuf2_SPO : std_logic_vector(15 downto 0) := (others => '0');
354 signal CntrBuf2_SPO_q : std_logic_vector(15 downto 0) := (others => '0');
355 signal CntrBuf2_Do : std_logic_vector(15 downto 0) := (others => '0');
356 signal CntrBuf2_wa : std_logic_vector(5 downto 0) := (others => '0');
357 signal resetCntrCycle : std_logic := '0';
358 signal CntrBuf_valid : std_logic := '0';
359 signal cntrs : std_logic_vector(6 downto 0) := (others => '0');
360 signal sglErrCntr : std_logic_vector(6 downto 0) := (others => '0');
361 signal dblErrCntr : std_logic_vector(6 downto 0) := (others => '0');
362 signal BC0mmCntr : std_logic_vector(6 downto 0) := (others => '0');
363 signal BcntMmCntr : std_logic_vector(6 downto 0) := (others => '0');
364 signal ResendCntr : std_logic_vector(6 downto 0) := (others => '0');
365 signal AcceptCntr : std_logic_vector(6 downto 0) := (others => '0');
366 signal CntrAcceptCntr : std_logic_vector(6 downto 0) := (others => '0');
367 signal TotalWordCntr : std_logic_vector(15 downto 0) := (others => '0');
368 signal ACKcntr : std_logic_vector(6 downto 0) := (others => '0');
369 signal AbortCntr : std_logic_vector(6 downto 0) := (others => '0');
370 signal RxEventCntr : std_logic_vector(6 downto 0) := (others => '0');
371 signal RdEventCntr : std_logic_vector(6 downto 0) := (others => '0');
372 signal DataAbortCntr : std_logic_vector(6 downto 0) := (others => '0');
373 signal CntrAbortCntr : std_logic_vector(6 downto 0) := (others => '0');
374 signal BUSYCntr : std_logic_vector(6 downto 0) := (others => '0');
375 signal EvtEVNmmCntr : std_logic_vector(6 downto 0) := (others => '0');
376 signal EvtBCNmmCntr : std_logic_vector(6 downto 0) := (others => '0');
377 signal EvtOCNmmCntr : std_logic_vector(6 downto 0) := (others => '0');
378 signal ACKNUM_fullAbortCntr : std_logic_vector(6 downto 0) := (others => '0');
379 signal EventInfo_fullAbortCntr : std_logic_vector(6 downto 0) := (others => '0');
380 signal EventBuf_fullAbortCntr : std_logic_vector(6 downto 0) := (others => '0');
381 signal SEQAbortCntr : std_logic_vector(6 downto 0) := (others => '0');
382 signal CRCAbortCntr : std_logic_vector(6 downto 0) := (others => '0');
383 signal frameAbortCntr : std_logic_vector(6 downto 0) := (others => '0');
384 signal bad_KAbortCntr : std_logic_vector(6 downto 0) := (others => '0');
385 signal bad_EventLengthCntr : std_logic_vector(6 downto 0) := (others => '0');
386 signal BlockCntr : std_logic_vector(6 downto 0) := (others => '0');
387 signal badCRCCntr : std_logic_vector(6 downto 0) := (others => '0');
388 signal TTSCntr : std_logic_vector(6 downto 0) := (others => '0');
389 signal TTCCntr : std_logic_vector(6 downto 0) := (others => '0');
390 signal TTS_ERRcntr : std_logic_vector(6 downto 0) := (others => '0');
391 signal TTS_DCcntr : std_logic_vector(6 downto 0) := (others => '0');
392 signal TTS_OOScntr : std_logic_vector(6 downto 0) := (others => '0');
393 signal TTS_BSYcntr : std_logic_vector(6 downto 0) := (others => '0');
394 signal TTS_OFWcntr : std_logic_vector(6 downto 0) := (others => '0');
395 signal WordCntr : std_logic_vector(15 downto 0) := (others => '0');
396 signal WordCntr_q : std_logic_vector(15 downto 0) := (others => '0');
397 signal AllZero : std_logic := '0';
398 signal zeroWordCntr : std_logic_vector(15 downto 0) := (others => '0');
399 signal Cntr_ra : std_logic_vector(8 downto 0) := (others => '0');
400 signal TTS_wa : std_logic_vector(1 downto 0) := (others =>'0');
401 signal TTS_wa0_SyncRegs : std_logic_vector(1 downto 0) := (others =>'0');
402 signal TTS_wa1_SyncRegs : std_logic_vector(1 downto 0) := (others =>'0');
403 signal TTS_InvalidCntr : std_logic_vector(15 downto 0) := (others =>'0');
404 signal TTS_UpdateCntr : std_logic_vector(15 downto 0) := (others =>'0');
405 signal RxNotInTableCntr : std_logic_vector(15 downto 0) := (others =>'0');
406 signal EofMissingCntr : std_logic_vector(15 downto 0) := (others =>'0');
407 signal WC11p : std_logic := '0';
408 signal WC11 : std_logic := '0';
409 signal RxNotInTableErr : std_logic := '0';
410 signal fake_CRC_q : std_logic := '0';
411 signal fake_CRC_q2 : std_logic := '0';
412 signal AMCCRC_q : std_logic_vector(15 downto 0) := (others => '0');
413 signal AMC_DATA_full : std_logic := '0';
414 signal AMC_DATA_WrEn : std_logic := '0';
415 signal AMC_DATA_Di : std_logic_vector(63 downto 0) := (others => '0');
416 signal WRERR : std_logic_vector(7 downto 0) := (others => '0');
417 signal RDERR : std_logic_vector(7 downto 0) := (others => '0');
418 signal RDCOUNT : array8x12;
419 signal WRCOUNT : array8x12;
420 signal block32K : std_logic := '0';
421 signal EventWC_carry : std_logic := '0';
422 signal LengthInHeader : std_logic_vector(19 downto 0) := (others => '0');
423 signal LengthInTrailer : std_logic_vector(19 downto 0) := (others => '0');
424 signal Ready_i : std_logic := '0';
425 signal TTS_wait : std_logic_vector(7 downto 0) := (others => '0');
426 signal TTS_DC_cntr : std_logic_vector(6 downto 0) := (others => '0');
427 signal TTS_SL_cntr : std_logic_vector(6 downto 0) := (others => '0');
428 signal TTS_ERR_cntr : std_logic_vector(6 downto 0) := (others => '0');
429 signal critical_TTS : std_logic_vector(1 downto 0) := (others =>'0');
430 signal critical_TTS_cntr : std_logic_vector(1 downto 0) := (others =>'0');
431 signal GotMismatch : std_logic := '0';
432 signal FirstMismatch : std_logic_vector(31 downto 0) := (others => '0');
433 signal LiveTime : std_logic_vector(7 downto 0) := (others => '0');
434 signal LiveTimeCntr : std_logic_vector(18 downto 0) := (others => '0');
435 begin
436 --debug_out(255 downto 83) <= (others => '0');
437 --debug_out(82) <= L1ASent;
438 --debug_out(81) <= AMC_DATA_WrEn;
439 --debug_out(80 downto 17) <= AMC_DATA_Di;
440 --debug_out(16) <= EventBuf_we(0);
441 --debug_out(15 downto 0) <= EventBuf_Di;
442 rxcommaalignen <= RxResetDoneSyncRegs(2);
443 TXDATA <= TXDATA_i;
444 EventInfo_dav <= EventInfo_dav_i;
445 AMC_OK <= AMCRdy;
446 Ready <= Ready_i;
447 TTC_status(0) <= BC0_lock when flavor = "HCAL" else '0';
448 TTC_status(1) <= TTC_lock when flavor = "HCAL" else '0';
449 --TTC_status(5 downto 2) <= TTC_FIFO_ra(3 downto 0);
450 --TTC_status(14 downto 6) <= TTC_FIFO_Di(8 downto 0);
451 --TTC_status(18 downto 15) <= TTC_FIFO_wa(3 downto 0);
452 --TTC_status(27 downto 19) <= TTC_FIFO_Do(8 downto 0);
453 --TTC_status(45 downto 28) <= HammingOut when HammingOutValid = '1' else (others => '0');
454 --TTC_status(49 downto 46) <= delta_BC0;
455 --TTC_status(53 downto 50) <= MmCntr;
456 --TTC_status(54) <= TTC_DataValid;
457 --TTC_status(78 downto 55) <= TTC_Data;
458 --TTC_status(79) <= TTC_FIFO_we;
459 --TTC_status(80) <= sgl_err;
460 --TTC_status(81) <= dbl_err;
461 --TTC_status(127 downto 82) <= (others => '0');
462 debug_out(0) <= EventInfoDi(21);
463 debug_out(6 downto 1) <= evn_OK;
464 debug_out(14 downto 7) <= evn;
465 debug_out(30 downto 15) <= RXDATA;
466 debug_out(32 downto 31) <= RXCHARISK;
467 debug_out(34 downto 33) <= RXCHARISCOMMA;
468 debug_out(35) <= check_packet;
469 debug_out(36) <= accept;
470 debug_out(37) <= eof;
471 debug_out(38) <= got_eof;
472 debug_out(39) <= get_evn;
473 debug_out(40) <= header2;
474 debug_out(41) <= end_of_event;
475 debug_out(42) <= end_of_block;
476 debug_out(43) <= we_EventInfo;
477 debug_out(44) <= TypeDATA;
478 debug_out(45) <= sel_TTC;
479 debug_out(46) <= Receiving;
480 debug_out(49 downto 47) <= evn_word;
481 debug_out(61 downto 50) <= RxWC;
482 debug_out(255 downto 62) <= (others => '0');
483 TTS_coded <= TTS_coded_i;
484 process(UsrClk)
485 variable c : std_logic_vector(3 downto 0);
486 variable s : std_logic_vector(3 downto 0);
487 begin
488  c(0) := RXDATA(8) xor RXDATA(9) xor RXDATA(11) xor RXDATA(12);
489  c(1) := RXDATA(8) xor RXDATA(10) xor RXDATA(11) xor RXDATA(13);
490  c(2) := RXDATA(9) xor RXDATA(10) xor RXDATA(11) xor RXDATA(14);
491  c(3) := not RXDATA(11) xor RXDATA(12) xor RXDATA(13) xor RXDATA(14) xor RXDATA(15);
492  s(0) := TTS_in(0) xor TTS_in(1) xor TTS_in(3);
493  s(1) := TTS_in(0) xor TTS_in(2) xor TTS_in(3);
494  s(2) := TTS_in(1) xor TTS_in(2) xor TTS_in(3);
495  s(3) := not TTS_in(0) xor TTS_in(1) xor TTS_in(2);
496  if(UsrClk'event and UsrClk = '1')then
497  if(AMC_en = '0' or TTS_disable = '1' or test = '1')then
498  TTS_coded_i <= "00000"; -- default is Ready
499  TTS_RQST <= "000";
500  elsif(Ready_i = '0')then
501  TTS_coded_i <= "00010"; -- default is Busy
502  TTS_RQST <= "000";
503  else
504  case TTS(3 downto 0) is
505  when x"0" | x"f" => TTS_coded_i(4 downto 0) <= "10000"; -- disconnected
506  when x"1" => TTS_coded_i <= "00001"; -- Overflow warning
507  when x"2" => TTS_coded_i <= "00100"; -- Out of Sync
508  when x"4" => TTS_coded_i <= "00010"; -- Busy
509  when x"c" => TTS_coded_i <= "01000"; -- error
510  when x"8" | x"9" | x"a" | x"b" => TTS_coded_i <= "00000"; -- ready
511  when others => null;
512  end case;
513  if(flavor /= "G2" and TTS(3 downto 2) = "10")then
514  TTS_RQST(2) <= TTS(1) and TTS(0);
515  TTS_RQST(1) <= TTS(1) and not TTS(0);
516  TTS_RQST(0) <= not TTS(1) and TTS(0);
517  else
518  TTS_RQST <= "000";
519  end if;
520  end if;
521 -- if(flavor /= "HCAL" and RXCHARISK = "01" and RXDATA(7 downto 0) = x"5c")then
522  if(RXCHARISK = "01" and RXDATA(7 downto 0) = x"5c")then
523  is_TTS <= '1';
524  else
525  is_TTS <= '0';
526  end if;
527  if(c(3) = '1' and or_reduce(c(2 downto 0)) = '1')then
528  TTS_valid <= '0';
529  else
530  TTS_valid <= '1';
531  end if;
532  if(c = x"3")then
533  TTS_in(0) <= not RXDATA(8);
534  else
535  TTS_in(0) <= RXDATA(8);
536  end if;
537  if(c = x"5")then
538  TTS_in(1) <= not RXDATA(9);
539  else
540  TTS_in(1) <= RXDATA(9);
541  end if;
542  if(c = x"6")then
543  TTS_in(2) <= not RXDATA(10);
544  else
545  TTS_in(2) <= RXDATA(10);
546  end if;
547  if(c = x"7")then
548  TTS_in(3) <= not RXDATA(11);
549  else
550  TTS_in(3) <= RXDATA(11);
551  end if;
552  if(is_TTS = '1' and TTS_valid = '1')then
553  case TTS_in is
554  when x"0" | x"2" | x"c" | x"f" => critical_TTS(0) <= '1';
555  when others => critical_TTS(0) <= '0';
556  end case;
557  else
558  critical_TTS(0) <= '0';
559  end if;
560  if(InitLink = '1' or Ready_i = '0')then
561  critical_TTS_cntr <= "00";
562  elsif(update_TTS = '1')then
563  if(critical_TTS = "00")then
564  critical_TTS_cntr <= "00";
565  else
566  critical_TTS_cntr <= critical_TTS_cntr + 1;
567  end if;
568  end if;
569  if(HammingOutValid = '1')then
570  case HammingOut(11 downto 8) is
571  when x"0" | x"2" | x"c" | x"f" => critical_TTS(1) <= '1';
572  when others => critical_TTS(1) <= '0';
573  end case;
574  else
575  critical_TTS(1) <= '0';
576  end if;
577  if((is_TTS = '1' and TTS_valid = '1') or HammingOutValid = '1')then
578  update_TTS <= '1';
579  else
580  update_TTS <= '0';
581  end if;
582  if(InitLink = '1' or Ready_i = '0')then
583  TTS <= x"64";
584  elsif(update_TTS = '1' and (critical_TTS = "00" or critical_TTS_cntr = "11"))then
585  TTS <= TTS_tmp;
586  end if;
587  if(is_TTS = '1' and TTS_valid = '1')then
588  TTS_tmp <= s & TTS_in;
589  elsif(HammingOutValid = '1')then
590  TTS_tmp(3 downto 0) <= HammingOut(11 downto 8);
591  end if;
592  if(strobe2ms = '1')then
593  LiveTime <= '0' & LiveTimeCntr(18 downto 12);
594  LiveTimeCntr <= (others => '0');
595  elsif(TTS_coded_i = "00000")then
596  LiveTimeCntr <= LiveTimeCntr + 1;
597  end if;
598  end if;
599 end process;
600 process(UsrClk,BC0_lock)
601 begin
602  if(BC0_lock = '0')then
603  BcntMmCntr <= (others => '0');
604  elsif(UsrClk'event and UsrClk = '1')then
605  if(resetCntr = '1')then
606  BcntMmCntr <= (others => '0');
607  elsif(BcntMm = '1')then
608  BcntMmCntr <= BcntMmCntr + 1;
609  end if;
610  end if;
611 end process;
612 AMC_IDp1 <= AMC_ID + 1;
613 AMC_IDp4(3) <= AMC_ID(3) or AMC_ID(2);
614 AMC_IDp4(2) <= not AMC_ID(2);
615 AMC_IDp4(1 downto 0) <= AMC_ID(1 downto 0);
616 process(UsrClk)
617 begin
618  if(UsrClk'event and UsrClk = '1')then
619  if(resetCntr = '1')then
620  BC0mmCntr <= (others => '0');
621  elsif(HammingOutValid = '1' and HammingOut(17) /= HammingOut(16))then
622  BC0mmCntr <= BC0mmCntr + 1;
623  end if;
624  if(AMC_en = '0')then
625  Cntr_RdEn <= '0';
626  elsif(Cntr_ADDR(11 downto 8) = AMC_ID or (Cntr_ADDR(11 downto 10) = "11" and Cntr_ADDR(8 downto 5) = AMC_IDp4))then
627  Cntr_RdEn <= '1';
628  else
629  Cntr_RdEn <= '0';
630  end if;
631  if(Cntr_ADDR(11 downto 8) /= AMC_ID and (Cntr_ADDR(11 downto 10) /= "11" or Cntr_ADDR(8 downto 5) /= AMC_IDp4))then
632  Cntr_ra <= (others => '0');
633  elsif(Cntr_ADDR(11 downto 10) = "11")then
634  Cntr_ra <= '1' & Cntr_ADDR(9) & "11" & Cntr_ADDR(4 downto 0);
635  else
636  Cntr_ra <= '0' & Cntr_ADDR(7 downto 2) & "00";
637  end if;
638  if(resetCntrCycle = '1' or Cntr_RdEn = '0')then
639  Cntr_DATA <= (others => '0');
640  elsif(Cntr_ra(8 downto 7) = "00")then
641  if(CntrBuf_valid = '1')then
642  Cntr_DATA <= CntrBuf_Do;
643  else
644  Cntr_DATA <= (others => '0');
645  end if;
646  elsif(Cntr_ra(8 downto 2) = "0100000")then
647  Cntr_DATA <= TotalWordCntr;
648  elsif(Cntr_ra(8 downto 7) = "10")then
649  case Cntr_ra(4 downto 0) is
650  when "00000" => Cntr_DATA <= "000" & EventBuf_wa;
651  when "00001" => Cntr_DATA <= "000" & EventBuf_ra & "00";
652  when "00010" => Cntr_DATA <= "000000" & L1Ainfo_wa;
653  when "00011" => Cntr_DATA <= "000000" & L1Ainfo_ra;
654  when "00100" => Cntr_DATA <= x"00" & L1Ainfo_wap;
655  when "00101" => Cntr_DATA <= ReSendQue_a & rfifo_a & ACKNUM_a & reset_SyncRegs(3) & AMCRdy & txfsmresetdone & RxResetDone & qpll_lock & InitLink & TxState;
656  when "00110" => Cntr_DATA <= EventInfo_a & "00000" & AMCRdy & EventInfo_ovfl & TTC_lock & BC0_lock & EventInfoRdDoneToggle & EventInfoToggle;
657  when "01000" => Cntr_DATA <= EventWC(15 downto 0);
658  when "01001" => Cntr_DATA <= block32K & AMC_DATA_full & "0000000000" & EventWC(19 downto 16);
659  when "01010" => Cntr_DATA <= WordCntr_q;
660  when "01011" => Cntr_DATA <= zeroWordCntr;
661  when "01100" => Cntr_DATA <= "000" & EventBuf_start;
662  when "01101" => Cntr_DATA <= "000" & EventBuf_wc & "00";
663  when "01110" => Cntr_DATA <= x"000" & TTS_tmp(3 downto 0);
664  when "10000" => Cntr_DATA <= x"00" & LinkVersion;
665  when "10001" => Cntr_DATA <= x"00" & CTRversion;
666  when "10010" => Cntr_DATA <= FirstMismatch(15 downto 0);
667  when "10011" => Cntr_DATA <= FirstMismatch(31 downto 16);
668  when "10100" => Cntr_DATA <= x"00" & WRERR;
669  when "10110" => Cntr_DATA <= x"00" & RDERR;
670  when "11000" => Cntr_DATA <= TTS_InvalidCntr;
671  when "11001" => Cntr_DATA <= TTS_UpdateCntr;
672  when "11010" => Cntr_DATA <= RxNotInTableCntr;
673  when "11011" => Cntr_DATA <= EofMissingCntr;
674  when "11100" => Cntr_DATA <= x"00" & LiveTime;
675  when others => Cntr_DATA <= x"0000";
676  end case;
677  else
678  Cntr_DATA <= CntrBuf2_Do;
679  end if;
680  if(resetCntr = '1')then
681  sglErrCntr <= (others => '0');
682  elsif(sgl_err = '1')then
683  sglErrCntr <= sglErrCntr + 1;
684  end if;
685  if(resetCntr = '1')then
686  dblErrCntr <= (others => '0');
687  elsif(dbl_err = '1')then
688  dblErrCntr <= dblErrCntr + 1;
689  end if;
690  if(resetCntr = '1')then
691  ResendCntr <= (others => '0');
692  elsif(Resend = '1')then
693  ResendCntr <= ResendCntr + 1;
694  end if;
695  if(resetCntr = '1')then
696  AcceptCntr <= (others => '0');
697  elsif(accept = '1')then
698  AcceptCntr <= AcceptCntr + 1;
699  end if;
700  if(resetCntr = '1')then
701  CntrAcceptCntr <= (others => '0');
702  elsif(CntrAccept = '1')then
703  CntrAcceptCntr <= CntrAcceptCntr + 1;
704  end if;
705  if(resetCntr = '1')then
706  ACKcntr <= (others => '0');
707  elsif(ACK = '1')then
708  ACKcntr <= ACKcntr + 1;
709  end if;
710  if(resetCntr = '1')then
711  TotalWordcntr <= (others => '0');
712  elsif(accept = '1')then
713  if(EventWC_carry = '1')then
714  TotalWordcntr <= TotalWordcntr + x"0200";
715  else
716  TotalWordcntr <= TotalWordcntr + EventWC(8 downto 0);
717  end if;
718  end if;
719  if(resetCntr = '1')then
720  RxEventCntr <= (others => '0');
721  elsif(end_of_event = '1')then
722  RxEventCntr <= RxEventCntr + 1;
723  end if;
724  if(resetCntr = '1')then
725  RdEventCntr <= (others => '0');
726  elsif(re_EventInfo = '1' and EventInfoDo(25) = '0')then
727  RdEventCntr <= RdEventCntr + 1;
728  end if;
729  TypeData_q <= TypeData;
730  if(resetCntr = '1')then
731  DataAbortCntr <= (others => '0');
732  elsif(Abort = '1')then
733  DataAbortCntr <= DataAbortCntr + 1;
734  end if;
735  if(resetCntr = '1')then
736  CntrAbortCntr <= (others => '0');
737  elsif(CntrAbort = '1')then
738  CntrAbortCntr <= CntrAbortCntr + 1;
739  end if;
740  if(resetCntr = '1')then
741  ACKNUM_fullAbortCntr <= (others => '0');
742  elsif(Abort = '1' and ACKNUM_full = '1')then
743  ACKNUM_fullAbortCntr <= ACKNUM_fullAbortCntr + 1;
744  end if;
745  if(resetCntr = '1')then
746  EventInfo_fullAbortCntr <= (others => '0');
747  elsif(Abort = '1' and EventInfo_full = '1')then
748  EventInfo_fullAbortCntr <= EventInfo_fullAbortCntr + 1;
749  end if;
750  if(resetCntr = '1')then
751  EventBuf_fullAbortCntr <= (others => '0');
752  elsif(Abort = '1' and EventBuf_full = '1')then
753  EventBuf_fullAbortCntr <= EventBuf_fullAbortCntr + 1;
754  end if;
755  if(resetCntr = '1')then
756  SEQAbortCntr <= (others => '0');
757  elsif((Abort = '1' or CntrAbort = '1') and SEQ_OK = '0')then
758  SEQAbortCntr <= SEQAbortCntr + 1;
759  end if;
760  if(resetCntr = '1')then
761  CRCAbortCntr <= (others => '0');
762  elsif((Abort = '1' or CntrAbort = '1') and CRC_OK = '0')then
763  CRCAbortCntr <= CRCAbortCntr + 1;
764  end if;
765  if(resetCntr = '1')then
766  frameAbortCntr <= (others => '0');
767  elsif((Abort = '1' or CntrAbort = '1') and frame_OK = '0')then
768  frameAbortCntr <= frameAbortCntr + 1;
769  end if;
770  if(resetCntr = '1')then
771  bad_KAbortCntr <= (others => '0');
772  elsif((Abort = '1' or CntrAbort = '1') and bad_K = '1')then
773  bad_KAbortCntr <= bad_KAbortCntr + 1;
774  end if;
775  if(resetCntr = '1')then
776  BlockCntr <= (others => '0');
777  elsif(we_EventInfo = '1')then
778  BlockCntr <= BlockCntr + 1;
779  end if;
780  if(resetCntr = '1')then
781  badCRCCntr <= (others => '0');
782  elsif(end_of_event = '1' and bad_AMCCRC = '1' and test = '0' and AMC_en = '1')then
783  badCRCCntr <= badCRCCntr + 1;
784  end if;
785  if(resetCntr = '1')then
786  TTSCntr <= (others => '0');
787  elsif(is_TTS = '1')then
788  TTSCntr <= TTSCntr + 1;
789  end if;
790  if(resetCntr = '1')then
791  TTS_DCcntr <= (others => '0');
792  TTS_ERRcntr <= (others => '0');
793  TTS_OOScntr <= (others => '0');
794  TTS_BSYcntr <= (others => '0');
795  TTS_OFWcntr <= (others => '0');
796  elsif(Ready_i = '1')then
797  if(TTS_coded_i(4) = '1')then
798  TTS_DCcntr <= TTS_DCcntr + 1;
799  end if;
800  if(TTS_coded_i(3) = '1')then
801  TTS_ERRcntr <= TTS_ERRcntr + 1;
802  end if;
803  if(TTS_coded_i(2) = '1')then
804  TTS_OOScntr <= TTS_OOScntr + 1;
805  end if;
806  if(TTS_coded_i(1) = '1')then
807  TTS_BSYcntr <= TTS_BSYcntr + 1;
808  end if;
809  if(TTS_coded_i(0) = '1')then
810  TTS_OFWcntr <= TTS_OFWcntr + 1;
811  end if;
812  end if;
813  if(resetCntr = '1')then
814  TTCCntr <= (others => '0');
815  elsif(TTC_DataValid = '1')then
816  TTCCntr <= TTCCntr + 1;
817  end if;
818  if(resetCntr = '1')then
819  bad_EventLengthCntr <= (others => '0');
820  elsif(end_of_event = '1' and bad_EventLength = '1')then
821  bad_EventLengthCntr <= bad_EventLengthCntr + 1;
822  end if;
823  if(resetCntr = '1' or test = '1' or AMC_en = '0')then
824  EvtEVNmmCntr <= (others => '0');
825  elsif(end_of_event = '1' and RxType(0) = '0')then
826  EvtEVNmmCntr <= EvtEVNmmCntr + 1;
827  end if;
828  if(resetCntr = '1' or test = '1' or AMC_en = '0')then
829  EvtBCNmmCntr <= (others => '0');
830  elsif(end_of_event = '1' and RxType(2) = '0')then
831  EvtBCNmmCntr <= EvtBCNmmCntr + 1;
832  end if;
833  if(resetCntr = '1' or test = '1' or AMC_en = '0')then
834  EvtOCNmmCntr <= (others => '0');
835  elsif(end_of_event = '1' and RxType(1) = '0')then
836  EvtOCNmmCntr <= EvtOCNmmCntr + 1;
837  end if;
838  if(reset = '1' or test = '1' or AMC_en = '0')then
839  FirstMismatch <= (others => '0');
840  GotMismatch <= '0';
841  elsif(end_of_event = '1' and GotMismatch = '0')then
842  FirstMismatch(31 downto 28) <= TTS(3 downto 0);
843  FirstMismatch(27 downto 25) <= RxType(2 downto 0);
844  FirstMismatch(24 downto 0) <= FirstMismatch(24 downto 0) + 1;
845  if(RxType(2 downto 0) /= "000")then
846  GotMismatch <= '1';
847  end if;
848  end if;
849  if(resetCntr = '1' or InitLink = '1')then
850  TTS_InvalidCntr <= (others => '0');
851  elsif(is_TTS = '1' and TTS_valid = '0')then
852  TTS_InvalidCntr <= TTS_InvalidCntr + 1;
853  end if;
854  if(resetCntr = '1' or InitLink = '1')then
855  TTS_UpdateCntr <= (others => '0');
856  elsif(update_TTS = '1')then
857  TTS_UpdateCntr <= TTS_UpdateCntr + 1;
858  end if;
859  if(Receiving = '1' and RxNotInTable /= "00")then
860  RxNotInTableErr <= '1';
861  else
862  RxNotInTableErr <= '0';
863  end if;
864  if(resetCntr = '1' or InitLink = '1')then
865  RxNotInTableCntr <= (others => '0');
866  elsif(RxNotInTableErr = '1')then
867  RxNotInTableCntr <= RxNotInTableCntr + 1;
868  end if;
869  if(resetCntr = '1' or InitLink = '1')then
870  EofMissingCntr <= (others => '0');
871  elsif(check_packet = '1' and eof = '0' and WC11 = '0')then
872  EofMissingCntr <= EofMissingCntr + 1;
873  end if;
874  if(resetCntr = '1' or Ready_i = '0')then
875  TTS_SL_cntr <= (others => '0');
876  elsif(update_TTS = '1' and TTS_tmp(3 downto 0) = x"2")then
877  TTS_SL_cntr <= TTS_SL_cntr + 1;
878  end if;
879  if(resetCntr = '1' or Ready_i = '0')then
880  TTS_DC_cntr <= (others => '0');
881  elsif(update_TTS = '1' and (TTS_tmp(3 downto 0) = x"0" or TTS_tmp(3 downto 0) = x"f"))then
882  TTS_DC_cntr <= TTS_DC_cntr + 1;
883  end if;
884  if(resetCntr = '1' or Ready_i = '0')then
885  TTS_ERR_cntr <= (others => '0');
886  elsif(update_TTS = '1' and TTS_tmp(3 downto 0) = x"c")then
887  TTS_ERR_cntr <= TTS_ERR_cntr + 1;
888  end if;
889  end if;
890 end process;
891 process(UsrClk)
892 begin
893  if(UsrClk'event and UsrClk = '1')then
894 -- if(flavor /= "HCAL" or RXCHARISK = "00")then
895  if(RXCHARISK = "00")then
896  sel_TTC <= '0';
897  elsif(RXCHARISK = "01" and RXDATA(7 downto 0) = x"bc")then
898  sel_TTC <= '1';
899  end if;
900  if(RXCHARISK(1) = '0')then
901  TTC_Data(23 downto 8) <= RXDATA;
902  TTC_Data(7 downto 0) <= TTC_Data(23 downto 16);
903  end if;
904  if(sel_TTC = '1' and RXCHARISK = "00" and AMCRdy = '1')then
905  TTC_DataValid <= '1';
906  else
907  TTC_DataValid <= '0';
908  end if;
909  end if;
910 end process;
911 i_TTC_trigger: TTC_trigger generic map(simulation => simulation) PORT MAP(
912  reset => reset,
913  UsrClk => UsrClk,
914  TTCclk => TTCclk,
915  HammingData_in => HammingOut,
916  HammingDataValid => HammingOutValid,
917  BC0 => BC0,
918  BcntMm => BcntMm,
919  TTC_lock => TTC_lock,
920  BC0_lock => BC0_lock,
921  TrigData => TrigData
922  );
923 i_HammingDecode: HammingDecode PORT MAP(
924  clk => UsrClk ,
925  din_valid => TTC_DataValid,
926  din => TTC_Data,
927  dout_valid => HammingOutValid,
928  dout => HammingOut,
929  sgl_err => sgl_err,
930  dbl_err => dbl_err
931  );
932 process(UsrClk,RxResetDone)
933 begin
934  if(RxResetDone = '0')then
935  RxResetDoneSyncRegs <= (others => '0');
936  AMCRdy <= '0';
937  elsif(UsrClk'event and UsrClk = '1')then
938  RxResetDoneSyncRegs <= RxResetDoneSyncRegs(1 downto 0) & '1';
939  if(txfsmresetdone = '1')then
940  AMCRdy <= '1';
941  end if;
942  end if;
943 end process;
944 process(UsrClk,reset,RxResetDone,txfsmresetdone,qpll_lock)
945 begin
946  if(reset = '1' or (test = '0' and (RxResetDone = '0' or txfsmresetdone = '0' or qpll_lock = '0')))then
947  reset_SyncRegs <= (others => '1');
948  EventInfoToggle <= '0';
949  EventInfoToggle_q <= '0';
950  elsif(UsrClk'event and UsrClk = '1')then
951  reset_SyncRegs <= reset_SyncRegs(2 downto 0) & '0';
952  if((we_EventInfo = '1' and EventInfo_a = x"f") or (re_EventInfo = '1' and (EventInfo_a /= x"0" or we_EventInfo = '1')))then
953  EventInfoToggle <= not EventInfoToggle;
954  end if;
955  EventInfoToggle_q <= EventInfoToggle;
956  end if;
957 end process;
958 process(UsrClk)
959 begin
960  if(UsrClk'event and UsrClk = '1')then
961  if(AMC_en = '0')then
962  EventInfo <= (others => '0');
963  else
964  EventInfo <= EventInfoDo;
965  end if;
966  if(RxResetDoneSyncRegs(2) = '0' or or_reduce(RxNotInTable) = '1' or bad_K = '1')then
967  DATA_VALID <= '0';
968  elsif(RXCHARISK(0) = '1' and RXDATA(7 downto 0) = x"bc")then
969  DATA_VALID <= '1';
970  end if;
971  if(InitLink = '1' or AMC_en = '0')then
972  Ready_i <= '0';
973  elsif(update_TTS = '1' or test = '1')then
974  Ready_i <= '1';
975  end if;
976  if(InitLink = '1' or Ready_i = '1' or TTS_wait(7) = '1')then
977  TTS_wait <= x"00";
978  else
979  TTS_wait <= TTS_wait + 1;
980  end if;
981  end if;
982 end process;
983 ReSend <= timer(N);
984 process(UsrClk)
985 begin
986  if(UsrClk'event and UsrClk = '1')then
987  if(timer(N) = '1' or ACK = '1' or (ReSendQue_empty = '1' and (got_comma = '0' or InitLink = '0')))then
988  timer <= (others => '0');
989  else
990  timer <= timer + 1;
991  end if;
992  if(ReSend = '1')then
993  ReSend_l <= '1';
994  elsif(TxState = SendSEQ)then
995  ReSend_l <= '0';
996  end if;
997 -- Comma ends a packet and after that, any D-word marks the beginning of a packet
998  if((RXCHARISCOMMA = "11" and RXDATA /= R_word) or test = '1' or AMCRdy = '0')then
999  Receiving <= '0';
1000  elsif(sel_TTC = '0' and RXCHARISK = "00")then
1001  Receiving <= '1';
1002  end if;
1003  if(sel_TTC = '0')then
1004  if(RxNotInTable /= "00")then
1005  bad_K <= '1';
1006  elsif(RXCHARISK = "00")then
1007  RXDATA_q <= RXDATA;
1008  if(Receiving = '0')then
1009  bad_K <= '0';
1010  RxSEQNUM <= RXDATA(15 downto 8);
1011  if(RXDATA(7 downto 0) = InitRqst and InitLink = '1')then
1012  TypeInit <= '1';
1013  else
1014  TypeInit <= '0';
1015  end if;
1016  if(RXDATA(7 downto 0) = Acknowledge)then
1017  TypeACK <= '1';
1018  else
1019  TypeACK <= '0';
1020  end if;
1021  if(RXDATA(7 downto 0) = data)then
1022  TypeData <= '1';
1023  else
1024  TypeData <= '0';
1025  end if;
1026  if(RXDATA(7 downto 0) = Counter)then
1027  TypeCntr <= '1';
1028  else
1029  TypeCntr <= '0';
1030  end if;
1031  Header2 <= '1';
1032  else
1033  Header2 <= '0';
1034  evn_word <= evn_word(1 downto 0) & Header2;
1035  if(evn_word(2) = '1' and get_evn = '1' and TypeData = '1')then
1036  evn <= RxData(7 downto 0);
1037  end if;
1038  if(Header2 = '1')then
1039  RxWC <= (others => '0');
1040  RxType <= RXDATA;
1041  else
1042  RxWC <= RxWC + 1;
1043  end if;
1044  if(RxWC(11 downto 2) = RxData(11 downto 2) and RxWC(1 downto 0) = "00")then
1045  WC_OKp <= '1';
1046  else
1047  WC_OKp <= '0';
1048  end if;
1049  WC_OK <= WC_OKp;
1050  WC11p <= RxData(11);
1051  WC11 <= WC11p;
1052  if(evn = RxData(15 downto 8))then
1053  evn_OK(0) <= '1';
1054  else
1055  evn_OK(0) <= '0';
1056  end if;
1057  evn_OK(4 downto 1) <= evn_OK(3 downto 0);
1058  end if;
1059  elsif(RXCHARISK = "10" or (RXCHARISK = "11" and RXDATA /= R_word and RXDATA /= eof_word and RXCHARISCOMMA /= "11") or (RXCHARISK = "01" and RXDATA(7 downto 0) /= x"5c" and RXDATA(7 downto 0) /= x"bc"))then
1060  bad_K <= '1';
1061  end if;
1062  end if;
1063  if((TypeACK = '1' or TypeInit = '1') and RXType(15 downto 8) = ReSendQueOut(15 downto 8) and ReSendQue_empty = '0' and ReSend = '0')then -- incoming acknowledge number is what waited for
1064  ACK_OK <= '1';
1065  else
1066  ACK_OK <= '0';
1067  end if;
1068  if(Receiving = '0')then
1069  ACKNUM_IN <= RxSEQNUM;
1070  end if;
1071  if(RxSEQNUM = NextSEQNUM)then -- incoming sequence number is what waited for
1072  SEQ_OK <= '1';
1073  else
1074  SEQ_OK <= '0';
1075  end if;
1076  if(or_reduce(RxCRC) = '0')then
1077  CRC_OK <= '1';
1078  else
1079  CRC_OK <= '0';
1080  end if;
1081  if(WC_OK = '1' and (((TypeData = '1' or TypeCntr = '1' or TypeACK = '1') and InitLink = '0') or (TypeInit = '1' and InitLink = '1')))then
1082  frame_OK <= '1';
1083  else
1084  frame_OK <= '0';
1085  end if;
1086  if(RXCHARISCOMMA = "11" and RXDATA /= R_word and Receiving = '1')then
1087  check_packet <= '1';
1088  else
1089  check_packet <= '0';
1090  end if;
1091  accept <= check_packet and SEQ_OK and CRC_OK and frame_OK and not EventInfo_full and not EventBuf_ovf and not bad_K and not ACKNUM_full and (eof or WC11) and TypeData;
1092  CntrAccept <= check_packet and SEQ_OK and CRC_OK and frame_OK and not bad_K and TypeCntr;
1093  we_ACKNUM <= check_packet and CRC_OK and frame_OK and not bad_K and not ACKNUM_full and not EventInfo_full and not EventBuf_ovf and (eof or WC11) and TypeData;
1094  ACK <= check_packet and ACK_OK and CRC_OK and frame_OK and not bad_K;
1095 -- Abort <= check_packet and (TypeData or TypeCntr) and not(SEQ_OK and CRC_OK and frame_OK and not bad_K and not((ACKNUM_full or EventInfo_full or EventBuf_ovf) and TypeData));
1096 -- Abort <= check_packet and (TypeData or TypeCntr) and not(SEQ_OK and CRC_OK and frame_OK and not bad_K and
1097 -- not((ACKNUM_full or EventInfo_full or EventBuf_ovf or (not eof and not WC11)) and TypeData));
1098  Abort <= check_packet and TypeData and not(SEQ_OK and CRC_OK and frame_OK and not bad_K and not ACKNUM_full and not EventInfo_full and not EventBuf_ovf and (eof or WC11));
1099  CntrAbort <= check_packet and TypeCntr and not(SEQ_OK and CRC_OK and frame_OK and not bad_K);
1100  if(InitLink = '1')then
1101  get_evn <= '1';
1102  elsif(accept = '1')then
1103  get_evn <= got_eof;
1104  end if;
1105  if(test = '1')then
1106  EventInfoDi(30 downto 27) <= fake_evn;
1107  elsif(accept = '1')then
1108  EventInfoDi(30 downto 27) <= evn(3 downto 0);
1109  end if;
1110  if(InitLink = '1' or (TxState = SendCRC and TxType = Counter))then
1111  GotCntr <= '0';
1112  elsif(CntrAccept = '1')then
1113  GotCntr <= '1';
1114  end if;
1115  if(InitLink = '1')then
1116  CntrACKNUM <= x"00";
1117  elsif(CntrAccept = '1')then
1118  CntrACKNUM <= RxSEQNUM;
1119  end if;
1120 -- if(reset_SyncRegs(3) = '1')then
1121  if(InitLink = '1')then
1122  ACKNUM_a <= (others => '1');
1123  elsif(we_ACKNUM = '1' and (TxState /= SendCRC or SendTTS = '1' or IsACK = '0'))then
1124  ACKNUM_a <= ACKNUM_a + 1;
1125  elsif(we_ACKNUM = '0' and TxState = SendCRC and IsACK = '1' and SendTTS = '0')then
1126  ACKNUM_a <= ACKNUM_a - 1;
1127  end if;
1128  if(ACKNUM_a = "11")then
1129  ACKNUM_empty <= '1';
1130  else
1131  ACKNUM_empty <= '0';
1132  end if;
1133  if(ACKNUM_a = "10")then
1134  ACKNUM_full <= '1';
1135  else
1136  ACKNUM_full <= '0';
1137  end if;
1138  if(InitLink = '1')then
1139  ACKNUM_l <= x"00";
1140  elsif(ACKNUM_a /= "11")then
1141  ACKNUM_l <= ACKNUM;
1142  end if;
1143  if(reset_SyncRegs(3) = '1')then
1144  NextSEQNUM <= x"00";
1145  elsif(accept = '1')then
1146  NextSEQNUM <= NextSEQNUM(6 downto 0) & not(NextSEQNUM(7) xor NextSEQNUM(5) xor NextSEQNUM(4) xor NextSEQNUM(3));
1147  end if;
1148 -- Receiving of eof K-word in a packet marks the end of the event
1149 -- if(Receiving = '0' or InitLink = '1')then
1150  if(check_packet = '1' or InitLink = '1')then
1151  eof <= '0';
1152  elsif(Receiving = '1' and RXCHARISK = "11" and RXDATA = eof_word)then
1153  eof <= '1';
1154  end if;
1155 -- latches eof signal
1156  if(check_packet = '1')then
1157  got_eof <= eof;
1158  end if;
1159 -- if buffer is getting full during packet receiving, buffer overflow error is set
1160  if(Receiving = '0')then
1161  EventBuf_ovf <= '0';
1162  elsif(EventBuf_full = '1')then
1163  EventBuf_ovf <= '1';
1164  end if;
1165  Receiving_q <= Receiving;
1166  if(InitLink = '1')then
1167  EventBuf_wa <= (others => '0');
1168  elsif(abort = '1')then
1169  EventBuf_wa <= EventBuf_start;
1170  elsif(EventBuf_we(0) = '1')then
1171  EventBuf_wa <= EventBuf_wa + 1;
1172  end if;
1173  if(InitLink = '1')then
1174  EventBuf_ra <= (others => '0');
1175  elsif(ec_EventBuf_ra = '1')then
1176  EventBuf_ra <= EventBuf_ra + 1;
1177  end if;
1178 -- packet starting write address is recorded before the first data is written to the buffer
1179  if(InitLink = '1')then
1180  EventBuf_start <= (others => '0');
1181  elsif(save_start_addr = '1')then
1182  EventBuf_start <= EventBuf_wa;
1183  end if;
1184 -- accepted data in EventBuf available for read out
1185  if(InitLink = '1')then
1186  EventBuf_wc <= (others => '0');
1187  elsif(ec_EventBuf_ra = '1')then
1188  EventBuf_wc <= EventBuf_wc - 1;
1189  else
1190  EventBuf_wc <= EventBuf_start(12 downto 2) - EventBuf_ra;
1191  end if;
1192  EventBuf_space <= EventBuf_wa(12 downto 2) - EventBuf_ra;
1193 -- buffer almost full
1194  if(and_reduce(EventBuf_space(10 downto 5)) = '1')then
1195  EventBuf_full <= '1';
1196  else
1197  EventBuf_full <= '0';
1198  end if;
1199  fake_full <= EventBuf_full or EventInfo_full;
1200  end if;
1201 end process;
1202 i_RxCRC: crc16D16 PORT MAP(
1203  clk => UsrClk ,
1204  init_crc => Init_RxCRC,
1205  we_crc => we_RxCRC,
1206  d => RXDATA ,
1207  crc => RxCRC
1208  );
1209 we_RxCRC <= '1' when RXCHARISK = "00" and sel_TTC = '0' else '0';
1210 Init_RxCRC <= '1' when RXCHARISCOMMA = "11" else '0';
1211 i_AMCCRC: EthernetCRCD16B PORT MAP(
1212  clk => UsrClk ,
1213  init => InitAMCCRC,
1214  save => accept ,
1215  restore => abort,
1216  ce => EventBuf_we(0),
1217  d => EventBuf_Di,
1218  crc => AMCCRC ,
1219  bad_crc => bad_AMCCRC
1220  );
1221 process(UsrClk)
1222 begin
1223  if(UsrClk'event and UsrClk = '1')then
1224  if(InitLink = '1' or end_of_event = '1')then
1225  InitAMCCRC <= '1';
1226  else
1227  InitAMCCRC <= '0';
1228  end if;
1229  end if;
1230 end process;
1231 g_ACKNUM : for i in 0 to 7 generate
1232  i_ACKNUM : SRL16E
1233  port map (
1234  Q => ACKNUM(i), -- SRL data output
1235  A0 => ACKNUM_a(0), -- Select[0] input
1236  A1 => ACKNUM_a(1), -- Select[1] input
1237  A2 => '0', -- Select[2] input
1238  A3 => '0', -- Select[3] input
1239  CE => we_ACKNUM, -- Clock enable input
1240  CLK => UsrClk, -- Clock input
1241  D => ACKNUM_IN(i) -- SRL data input
1242  );
1243 end generate;
1244 -- this fifo is used to hold the last couple of received data words before writing to the data buffer.
1245 -- this is because 1. word count and CRC of the packet should not be written to the buffer and more importantly,
1246 -- if the packet is the last packet of the event, the last data word must be properly marked with the LinkCtrl
1247 -- before being written to the buffer. 3. next packet data may arrive before a decision being made to accept or reject a packet.
1248 g_rfifo: for i in 0 to 15 generate
1249  i_rfifo : SRL16E
1250  port map (
1251  Q => rfifo(i), -- SRL data output
1252  A0 => '1', -- Select[0] input
1253  A1 => '0', -- Select[1] input
1254  A2 => '0', -- Select[2] input
1255  A3 => '0', -- Select[3] input
1256  CE => we_rfifo, -- Clock enable input
1257  CLK => UsrClk, -- Clock input
1258  D => RXDATA_q(i) -- SRL data input
1259  );
1260 end generate;
1261 process(UsrClk)
1262 begin
1263  if(UsrClk'event and UsrClk = '1')then
1264  if(sel_TTC = '0' and RXCHARISK = "00")then
1265  we_rfifo <= '1';
1266  else
1267  we_rfifo <= '0';
1268  end if;
1269  if(InitLink = '1' or check_packet = '1')then
1270  dl_cntr <= "000";
1271  elsif(we_rfifo = '1')then
1272  dl_cntr(2) <= dl_cntr(2) or (dl_cntr(1) and dl_cntr(0));
1273  dl_cntr(1) <= dl_cntr(1) xor dl_cntr(0);
1274  dl_cntr(0) <= not dl_cntr(2) and not dl_cntr(0);
1275  end if;
1276  end if;
1277 end process;
1278 g_EventBuffer : for i in 0 to 3 generate
1279  i_EventBuffer : BRAM_SDP_MACRO
1280  generic map (
1281  BRAM_SIZE => "36Kb", -- Target BRAM, "18Kb" or "36Kb"
1282  DEVICE => "7SERIES", -- Target device: "VIRTEX5", "VIRTEX6", "7SERIES", "SPARTAN6"
1283  WRITE_WIDTH => 4, -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
1284  READ_WIDTH => 16, -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
1285  DO_REG => 1, -- Optional output register (0 or 1)
1286  SIM_COLLISION_CHECK => "NONE") -- Collision check enable "ALL", "WARNING_ONLY",
1287  -- "GENERATE_X_ONLY" or "NONE"
1288  port map (
1289  DO => EventBuf_Do(i*16+15 downto i*16), -- Output read data port, width defined by READ_WIDTH parameter
1290  DI => EventBuf_Di(i*4+3 downto i*4), -- Input write data port, width defined by WRITE_WIDTH parameter
1291  RDADDR => EventBuf_ra, -- Input read address, width defined by read port depth
1292  RDCLK => UsrClk, -- 1-bit input read clock
1293  RDEN => '1', -- 1-bit input read port enable
1294  REGCE => '1', -- 1-bit input read output register enable
1295  RST => '0', -- 1-bit input reset
1296  WE => "1", -- Input write enable, width defined by write port depth
1297  WRADDR => EventBuf_wa, -- Input write address, width defined by write port depth
1298  WRCLK => UsrClk, -- 1-bit input write clock
1299  WREN => EventBuf_we(0) -- 1-bit input write port enable
1300  );
1301 end generate;
1302 g_MC_DATA_Di : for i in 0 to 3 generate
1303  g_AMC_DATA_Dij: for j in 0 to 3 generate
1304  AMC_DATA_Di(i*16+j*4+3 downto i*16+j*4) <= EventBuf_Do(i*4+j*16+3 downto i*4+j*16);
1305  end generate;
1306 end generate;
1307 i_AMC_DATA: AMC_DATA_FIFO PORT MAP(
1308  wclk => UsrClk ,
1309  rclk => sysclk ,
1310  reset => fifo_rst,
1311  fifo_en => fifo_en,
1312  we => AMC_DATA_WrEn,
1313  re => AMC_DATA_RdEn,
1314  Di => AMC_DATA_Di,
1315  Do => AMC_DATA,
1316  WRERR_OUT => WRERR,
1317  RDERR_OUT => RDERR,
1318  full => AMC_DATA_full
1319  );
1320 --AMC_DATA_WrEn <= fifo_en and not AMC_DATA_full(0) and AMC_DATA_Di_vld;
1321 process(UsrClk)
1322 begin
1323  if(UsrClk'event and UsrClk = '1')then
1324  if(reset_SyncRegs(3) = '1' or fifo_en = '0' or AMC_DATA_full = '1')then
1325  ec_EventBuf_ra <= '0';
1326  elsif(or_reduce(EventBuf_wc(10 downto 1)) = '0' and (EventBuf_wc(0) = '0' or ec_EventBuf_ra = '1'))then
1327  ec_EventBuf_ra <= '0';
1328  else
1329  ec_EventBuf_ra <= '1';
1330  end if;
1331  ec_EventBuf_ra_q <= fifo_en and ec_EventBuf_ra;
1332  AMC_DATA_WrEn <= fifo_en and ec_EventBuf_ra_q;
1333  end if;
1334 end process;
1335 process(UsrClk)
1336 begin
1337  if(UsrClk'event and UsrClk = '1')then
1338  if(InitLink = '1' or (test = '1' and fake_got_eof = '1') or (test = '0' and ((abort = '1' and saved_BOE = '1') or (accept = '1' and got_eof = '1'))))then
1339  BOE <= '1';
1340  elsif(EventBuf_we(0) = '1' and EventBuf_wa(0) = '1')then
1341  BOE <= '0';
1342  end if;
1343  if(InitLink = '1' or accept = '1')then
1344  saved_BOE <= '0';
1345  elsif(BOE = '1')then
1346  saved_BOE <= '1';
1347  end if;
1348  if(BOE = '1')then
1349  AMCinfo_word <= '1';
1350  elsif(AMCinfo_word = '1' and EventBuf_we(0) = '1' and EventBuf_wa(1 downto 0) = "00")then
1351  AMCinfo_word <= '0';
1352  AMCinfoDi <= EventBuf_Di;
1353  end if;
1354 -- if(InitLink = '1' or end_of_block = '1' or end_of_event = '1')then
1355  if(InitLink = '1' or ((accept = '1' or test = '1') and end_of_block = '1') or end_of_event = '1')then
1356  block32K <= '0';
1357  elsif(EventWC_carry = '1' and EventWC(11 downto 9) = "111" and(test = '1' or accept = '1'))then
1358  block32K <= '1';
1359  end if;
1360 -- if(InitLink = '0' and AMC_en = '1' and block32K = '1' and end_of_block = '0' and and_reduce(EventWC(9 downto 1)) = '1' and EventBuf_we(0) = '1')then
1361 -- end_of_block <= '1';
1362 -- else
1363 -- end_of_block <= '0';
1364 -- end if;
1365  if(block32K = '0' or (test = '1' and end_of_block = '1'))then
1366  end_of_block <= '0';
1367  elsif(EventBuf_we(0) = '1' and and_reduce(EventWC(9 downto 1)) = '1')then
1368  end_of_block <= '1';
1369  end if;
1370  if(InitLink = '0' and ((test = '1' and fake_got_eof = '1') or (test = '0' and accept = '1' and got_eof = '1')))then
1371  end_of_event <= '1';
1372  else
1373  end_of_event <= '0';
1374  end if;
1375 -- we_EventInfo <= not InitLink and not(NoReSyncFake and EventInfoDi(31)) and (end_of_block or end_of_event);
1376  if(InitLink = '1' or (NoReSyncFake = '1' and EventInfoDi(31) = '1') or AMC_en = '0')then
1377  we_EventInfo <= '0';
1378  elsif((accept = '1' or test = '1') and end_of_block = '1')then
1379  we_EventInfo <= '1';
1380  elsif(end_of_event = '1')then
1381  we_EventInfo <= '1';
1382  else
1383  we_EventInfo <= '0';
1384  end if;
1385  if(InitLink = '1' or (test = '0' and abort = '1') or end_of_event = '1')then
1386  EventWC(8 downto 0) <= (others => '0');
1387  elsif(EventBuf_we(0) = '1' and EventBuf_wa(1 downto 0) = "11")then
1388  EventWC(8 downto 0) <= EventWC(8 downto 0) + 1;
1389  end if;
1390  if(InitLink = '1' or (test = '0' and (abort = '1' or accept = '1')) or (test = '1' and EventWC_carry = '1'))then
1391  EventWC_carry <= '0';
1392  elsif(EventBuf_we(0) = '1' and EventBuf_wa(1 downto 0) = "11" and and_reduce(EventWC(8 downto 0)) = '1')then
1393  EventWC_carry <= '1';
1394  end if;
1395  if(InitLink = '1' or end_of_event = '1')then
1396  EventWC_tmp(19 downto 9) <= (others => '0');
1397  elsif(EventBuf_we(0) = '1' and EventBuf_wa(1 downto 0) = "11")then
1398  if(and_reduce(EventWC(8 downto 0)) = '1')then
1399  EventWC_tmp(19 downto 9) <= EventWC(19 downto 9) + 1;
1400  else
1401  EventWC_tmp(19 downto 9) <= EventWC(19 downto 9);
1402  end if;
1403  end if;
1404  if(EventBuf_we(0) = '1' and EventBuf_wa(1 downto 0) = "00")then
1405  LengthInTrailer(15 downto 0) <= EventBuf_Di;
1406  end if;
1407  if(EventBuf_we(0) = '1' and EventBuf_wa(1 downto 0) = "01")then
1408  LengthInTrailer(19 downto 16) <= EventBuf_Di(3 downto 0);
1409  end if;
1410  if(InitLink = '1' or end_of_event = '1')then
1411  EventWC(19 downto 9) <= (others => '0');
1412 -- elsif(EventWC_carry = '1' and(test = '1' or accept = '1'))then
1413 -- EventWC(19 downto 9) <= EventWC(19 downto 9) + 1;
1414  elsif(test = '1' or accept = '1')then
1415  EventWC(19 downto 9) <= EventWC_tmp(19 downto 9);
1416  end if;
1417  UnknownLength <= and_reduce(LengthInHeader);
1418  if(LengthInHeader = LengthInTrailer or UnknownLength = '1')then
1419  LengthMatch <= '1';
1420  else
1421  LengthMatch <= '0';
1422  end if;
1423  if(EventWC_tmp = LengthInTrailer and LengthMatch = '1')then
1424  bad_EventLength <= '0';
1425  else
1426  bad_EventLength <= '1';
1427  end if;
1428  if(end_of_event = '1')then
1429  EventInfoDi(19 downto 0) <= "0000000" & block32K & EventWC(11 downto 0);
1430  EventInfoDi(25) <= '0';-- M bit
1431  EventInfoDi(26) <= bad_EventLength;-- EventLengthErr
1432  elsif(BOE = '1' and EventBuf_we(0) = '1')then
1433  if(EventBuf_wa(0) = '0')then
1434  EventInfoDi(15 downto 0) <= EventBuf_Di;
1435  LengthInHeader(15 downto 0) <= EventBuf_Di;
1436  else
1437  EventInfoDi(19 downto 16) <= EventBuf_Di(3 downto 0);
1438  LengthInHeader(19 downto 16) <= EventBuf_Di(3 downto 0);
1439  end if;
1440  EventInfoDi(24) <= '0';-- S bit
1441  EventInfoDi(25) <= '1';-- M bit
1442  EventInfoDi(26) <= '0';-- EventLengthErr
1443  elsif(we_EventInfo = '1')then
1444  EventInfoDi(19 downto 0) <= x"01000";
1445  EventInfoDi(24) <= '1';-- S bit
1446  EventInfoDi(25) <= '1';-- M bit
1447  end if;
1448 -- if(InitLink = '1' or we_EventInfo = '1')then
1449 -- EventInfoDi(20) <= '0';
1450 -- elsif(end_of_event = '1')then
1451 -- EventInfoDi(20) <= (not bad_AMCCRC or test) and AMC_en;
1452 -- end if;
1453  if(end_of_event = '1')then
1454  EventInfoDi(20) <= (not bad_AMCCRC or test) and AMC_en;
1455  else
1456  EventInfoDi(20) <= '0';
1457  end if;
1458  if(AMC_en = '0' or test = '1')then
1459  bad_AMC <= '0';
1460  LinkVersion <= x"00";
1461  elsif(InitLink = '1')then
1462  if(ACK = '1' and CTRversion = RxType(7 downto 0))then
1463  bad_AMC <= '0';
1464  else
1465  bad_AMC <= '1';
1466  end if;
1467  if(ACK = '1')then
1468  LinkVersion <= RxType(7 downto 0);
1469  end if;
1470  end if;
1471  if(check_packet = '1')then
1472  evn_OK(5) <= evn_OK(4) or not eof;
1473  end if;
1474 -- EventInfoDi(21) <= not(RxType(2) and RxType(1) and RxType(0)) and not test and AMC_en;
1475  EventInfoDi(31) <= RxType(3) and AMC_en and not test; -- got faked data during ReSync
1476  EventInfoDi(21) <= ((RxType(2) and RxType(1) and RxType(0) and evn_OK(5)) or test) and AMC_en;
1477  EventInfoDi(22) <= AMC_en;
1478  EventInfoDi(23) <= AMC_en;
1479  fake_CRC_q <= not InitLink and AMC_en and fake_CRC;
1480  fake_CRC_q2 <= not InitLink and fake_CRC_q;
1481  AMCCRC_q <= AMCCRC(31 downto 16);
1482  if(test = '1')then
1483  if(fake_header = '1')then
1484  EventBuf_Di <= x"0" & AMC_IDp1 & fake_DATA(7 downto 0);
1485  fake_evn <= fake_DATA(3 downto 0);
1486  elsif(fake_CRC_q = '1')then
1487  EventBuf_Di <= AMCCRC(15 downto 0);
1488  elsif(fake_CRC_q2 = '1')then
1489  EventBuf_Di <= AMCCRC_q;
1490  else
1491  EventBuf_Di <= fake_DATA;
1492  end if;
1493  else
1494  EventBuf_Di <= rfifo;
1495  end if;
1496  if(test = '1')then
1497  EventBuf_we(0) <= (fake_WrEn or fake_CRC_q2) and not fake_CRC and AMC_en;
1498  elsif(we_rfifo = '1' and dl_cntr(2) = '1' and TypeData = '1' and abort = '0' and EventBuf_full = '0')then
1499  EventBuf_we(0) <= '1';
1500  else
1501  EventBuf_we(0) <= '0';
1502  end if;
1503  if(test = '1' or (InitLink = '0' and accept = '1'))then
1504  save_start_addr <= '1';
1505  else
1506  save_start_addr <= '0';
1507  end if;
1508  if(InitLink = '1')then
1509  EventInfo_a <= (others => '1');
1510  EventInfo_ovfl <= (others => '0');
1511  elsif(we_EventInfo = '1' and re_EventInfo = '0')then
1512  EventInfo_a <= EventInfo_a + 1;
1513  if(EventInfo_a = x"e")then
1514  EventInfo_ovfl(0) <= '1';
1515  end if;
1516  elsif(we_EventInfo = '0' and re_EventInfo = '1')then
1517  EventInfo_a <= EventInfo_a - 1;
1518  if(EventInfo_a = x"f")then
1519  EventInfo_ovfl(1) <= '1';
1520  end if;
1521  end if;
1522  if(EventInfo_a = x"d" or EventInfo_a = x"e" or (test = '1' and EventInfo_a(3) = '1' and EventInfo_a(2 downto 0) /= "111"))then
1523  EventInfo_full <= '1';
1524  else
1525  EventInfo_full <= '0';
1526  end if;
1527  re_EventInfo <= not InitLink and (EventInfoRdDoneToggleSyncRegs(3) xor EventInfoRdDoneToggleSyncRegs(2));
1528  if(InitLink = '1')then
1529  EventInfoRdDoneToggleSyncRegs <= (others => '0');
1530  else
1531  EventInfoRdDoneToggleSyncRegs <= EventInfoRdDoneToggleSyncRegs(2 downto 0) & EventInfoRdDoneToggle;
1532  end if;
1533  if(resetCntrCycle = '1')then
1534  CntrBuf_Di <= (others => '0');
1535  we_CntrBuf <= '1';
1536  else
1537  CntrBuf_Di <= rfifo;
1538  we_CntrBuf <= we_rfifo and dl_cntr(2) and TypeCntr and not Cntrabort;
1539  end if;
1540  if(Receiving = '0')then
1541  CntrBuf_wa(4 downto 0) <= (others => '0');
1542  elsif(we_CntrBuf = '1')then
1543  CntrBuf_wa(4 downto 0) <= CntrBuf_wa(4 downto 0) + 1;
1544  end if;
1545  if(InitLink = '1')then
1546  CntrBuf_wa(5) <= '0';
1547  elsif(CntrAccept = '1')then
1548  CntrBuf_wa(5) <= not CntrBuf_wa(5);
1549  end if;
1550  if(InitLink = '1' or resetCntr = '1')then
1551  CntrBuf_valid <= '0';
1552  elsif(CntrAccept = '1')then
1553  CntrBuf_valid <= '1';
1554  end if;
1555  end if;
1556 end process;
1557 EventWC_tmp(8 downto 0) <= EventWC(8 downto 0);
1558 i_fake_got_eof : SRL16E
1559  port map (
1560  Q => fake_got_eof, -- SRL data output
1561  A0 => '0', -- Select[0] input
1562  A1 => '1', -- Select[1] input
1563  A2 => '0', -- Select[2] input
1564  A3 => '0', -- Select[3] input
1565  CE => '1', -- Clock enable input
1566  CLK => UsrClk, -- Clock input
1567  D => fake_CRC_q -- SRL data input
1568  );
1569 g_AMCinfo : for i in 0 to 15 generate
1570  i_AMCinfo : SRL16E
1571  port map (
1572  Q => AMCinfo(i), -- SRL data output
1573  A0 => EventInfo_a(0), -- Select[0] input
1574  A1 => EventInfo_a(1), -- Select[1] input
1575  A2 => EventInfo_a(2), -- Select[2] input
1576  A3 => EventInfo_a(3), -- Select[3] input
1577  CE => we_EventInfo, -- Clock enable input
1578  CLK => UsrClk, -- Clock input
1579  D => AMCinfoDi(i) -- SRL data input
1580  );
1581 end generate;
1582 g_EventInfo : for i in 0 to 31 generate
1583  i_EventInfo : SRL16E
1584  port map (
1585  Q => EventInfoDo(i), -- SRL data output
1586  A0 => EventInfo_a(0), -- Select[0] input
1587  A1 => EventInfo_a(1), -- Select[1] input
1588  A2 => EventInfo_a(2), -- Select[2] input
1589  A3 => EventInfo_a(3), -- Select[3] input
1590  CE => we_EventInfo, -- Clock enable input
1591  CLK => UsrClk, -- Clock input
1592  D => EventInfoDi(i) -- SRL data input
1593  );
1594 end generate;
1595 g_CntrBuf : for i in 0 to 15 generate
1596  i_CntrBuf : RAM64X1D
1597  port map (
1598  DPO => CntrBuf_Do(i), -- Read-only 1-bit data output
1599  SPO => open, -- R/W 1-bit data output
1600  A0 => CntrBuf_wa(0), -- R/W address[0] input bit
1601  A1 => CntrBuf_wa(1), -- R/W address[1] input bit
1602  A2 => CntrBuf_wa(2), -- R/W address[2] input bit
1603  A3 => CntrBuf_wa(3), -- R/W address[3] input bit
1604  A4 => CntrBuf_wa(4), -- R/W address[4] input bit
1605  A5 => CntrBuf_wa(5), -- R/W address[5] input bit
1606  D => CntrBuf_Di(i), -- Write 1-bit data input
1607  DPRA0 => CntrBuf_ra(0), -- Read-only address[0] input bit
1608  DPRA1 => CntrBuf_ra(1), -- Read-only address[1] input bit
1609  DPRA2 => CntrBuf_ra(2), -- Read-only address[2] input bit
1610  DPRA3 => CntrBuf_ra(3), -- Read-only address[3] input bit
1611  DPRA4 => CntrBuf_ra(4), -- Read-only address[4] input bit
1612  DPRA5 => CntrBuf_ra(5), -- Read-only address[5] input bit
1613  WCLK => UsrClk, -- Write clock input
1614  WE => we_CntrBuf -- Write enable input
1615  );
1616 end generate;
1617 CntrBuf_ra <= not CntrBuf_wa(5) & Cntr_ra(6 downto 2);
1618 g_CntrBuf2 : for i in 0 to 15 generate
1619  i_CntrBuf2 : RAM64X1D
1620  port map (
1621  DPO => CntrBuf2_Do(i), -- Read-only 1-bit data output
1622  SPO => CntrBuf2_SPO(i), -- R/W 1-bit data output
1623  A0 => CntrBuf2_wa(0), -- R/W address[0] input bit
1624  A1 => CntrBuf2_wa(1), -- R/W address[1] input bit
1625  A2 => CntrBuf2_wa(2), -- R/W address[2] input bit
1626  A3 => CntrBuf2_wa(3), -- R/W address[3] input bit
1627  A4 => CntrBuf2_wa(4), -- R/W address[4] input bit
1628  A5 => CntrBuf2_wa(5), -- R/W address[5] input bit
1629  D => CntrBuf2_Di(i), -- Write 1-bit data input
1630  DPRA0 => Cntr_ra(2), -- Read-only address[0] input bit
1631  DPRA1 => Cntr_ra(3), -- Read-only address[1] input bit
1632  DPRA2 => Cntr_ra(4), -- Read-only address[2] input bit
1633  DPRA3 => Cntr_ra(5), -- Read-only address[3] input bit
1634  DPRA4 => Cntr_ra(6), -- Read-only address[4] input bit
1635  DPRA5 => Cntr_ra(8), -- Read-only address[5] input bit
1636  WCLK => UsrClk, -- Write clock input
1637  WE => we_CntrBuf2 -- Write enable input
1638  );
1639 end generate;
1640 process(UsrClk)
1641 begin
1642  if(UsrClk'event and UsrClk = '1')then
1643  if(resetCntr = '1')then
1644  zeroWordCntr <= (others => '0');
1645  elsif(or_reduce(EventBuf_Di) = '0' and EventBuf_wa(1 downto 0) = "11" and AllZero = '1' and EventBuf_we(0) = '1')then
1646  zeroWordCntr <= zeroWordCntr + 1;
1647  end if;
1648  if(resetCntr = '1')then
1649  AllZero <= '1';
1650  elsif(EventBuf_we(0) = '1')then
1651  if(EventBuf_wa(1 downto 0) = "11")then
1652  AllZero <= '1';
1653  elsif(or_reduce(EventBuf_Di) = '1')then
1654  AllZero <= '0';
1655  end if;
1656  end if;
1657  we_CntrBuf2p <= not we_CntrBuf2;
1658  we_CntrBuf2 <= we_CntrBuf2p and not we_CntrBuf2;
1659  if(resetCntr = '1')then
1660  CntrBuf2_wa <= "111000";
1661  elsif(we_CntrBuf2 = '1')then
1662  if(CntrBuf2_wa = "011111")then -- 40 counters time 3 is 120 < 128 and 7 bit counters won't overflow
1663  CntrBuf2_wa <= "111000";
1664  else
1665  CntrBuf2_wa <= CntrBuf2_wa + 1;
1666  end if;
1667  end if;
1668  if(resetCntr = '1')then
1669  resetCntrCycle <= '1';
1670  elsif(we_CntrBuf2 = '1' and CntrBuf2_wa = "011111")then
1671  resetCntrCycle <= '0';
1672  end if;
1673  if(CntrBuf2_wa(5) = '1')then
1674  case CntrBuf2_wa(2 downto 0) is
1675  when "000" => Cntrs <= TTS_OFWcntr;
1676  when "001" => Cntrs <= TTS_BSYcntr;
1677  when "010" => Cntrs <= TTS_OOScntr;
1678  when "011" => Cntrs <= TTS_ERRcntr;
1679  when "100" => Cntrs <= TTS_DCcntr;
1680  when others => Cntrs <= (others=> '0');
1681  end case;
1682  elsif(CntrBuf2_wa(4) = '0')then
1683  case CntrBuf2_wa(3 downto 0) is
1684  when x"1" => Cntrs <= sglErrCntr;
1685  when x"2" => Cntrs <= dblErrCntr;
1686  when x"3" => Cntrs <= BC0mmCntr;
1687  when x"4" => Cntrs <= BcntMmCntr;
1688  when x"5" => Cntrs <= ResendCntr;
1689  when x"6" => Cntrs <= AcceptCntr;
1690  when x"7" => Cntrs <= CntrAcceptCntr;
1691  when x"8" => Cntrs <= ACKcntr;
1692  when x"9" => Cntrs <= RxEventCntr;
1693  when x"a" => Cntrs <= RdEventCntr;
1694  when x"b" => Cntrs <= DataAbortCntr;
1695  when x"c" => Cntrs <= CntrAbortCntr;
1696  when x"d" => Cntrs <= ACKNUM_fullAbortCntr;
1697  when x"e" => Cntrs <= EventBuf_fullAbortCntr;
1698  when others => Cntrs <= EventInfo_fullAbortCntr;
1699  end case;
1700  else
1701  case CntrBuf2_wa(3 downto 0) is
1702  when x"0" => Cntrs <= SEQAbortCntr;
1703  when x"1" => Cntrs <= CRCAbortCntr;
1704  when x"2" => Cntrs <= frameAbortCntr;
1705  when x"3" => Cntrs <= bad_KAbortCntr;
1706  when x"4" => Cntrs <= BUSYCntr;
1707  when x"5" => Cntrs <= EvtEVNmmCntr;
1708  when x"6" => Cntrs <= EvtBCNmmCntr;
1709  when x"7" => Cntrs <= EvtOCNmmCntr;
1710  when x"8" => Cntrs <= bad_EventLengthCntr;
1711  when x"9" => Cntrs <= BlockCntr; -- we_EventInfo count
1712  when x"a" => Cntrs <= TTSCntr; -- IS_TTS count
1713  when x"b" => Cntrs <= TTCCntr; -- TTC_DataValid count
1714  when x"c" => Cntrs <= badCRCCntr; -- bad AMC event CRC count
1715  when x"d" => Cntrs <= TTS_ERR_cntr; -- TTC_DataValid count
1716  when x"e" => Cntrs <= TTS_SL_cntr; -- bad AMC event CRC count
1717  when others => Cntrs <= TTS_DC_cntr;
1718  end case;
1719  end if;
1720  CntrBuf2_SPO_q <= CntrBuf2_SPO;
1721  if(resetCntrCycle = '1')then
1722  CntrBuf2_Di(15 downto 7) <= (others => '0');
1723  elsif(Cntrs < CntrBuf2_SPO_q(6 downto 0))then
1724  CntrBuf2_Di(15 downto 7) <= CntrBuf2_SPO_q(15 downto 7) + 1;
1725  else
1726  CntrBuf2_Di(15 downto 7) <= CntrBuf2_SPO_q(15 downto 7);
1727  end if;
1728  if(resetCntrCycle = '1')then
1729  CntrBuf2_Di(6 downto 0) <= (others => '0');
1730  else
1731  CntrBuf2_Di(6 downto 0) <= Cntrs;
1732  end if;
1733  end if;
1734 end process;
1735 process(sysclk,resetCntr)
1736 begin
1737  if(resetCntr = '1')then
1738  WordCntr <= (others => '0');
1739  WordCntr_q <= (others => '0');
1740  elsif(sysclk'event and sysclk = '1')then
1741  if(AMC_DATA_RdEn = '1')then
1742  WordCntr <= WordCntr + 1;
1743  end if;
1744  if(Cntr_RdEn = '0' or Cntr_ra(8 downto 7) /= "10")then
1745  WordCntr_q <= WordCntr;
1746  end if;
1747  end if;
1748 end process;
1749 process(sysclk,InitLink)
1750 begin
1751  if(InitLink = '1')then
1752  EventInfoRdDoneToggle <= '0';
1753  EventInfo_dav_i <= '0';
1754  EventInfoToggleSyncRegs <= (others => '0');
1755  L1Ainfo_wa <= (others => '0');
1756  elsif(sysclk'event and sysclk = '1')then
1757  if(reset = '1')then
1758  EventInfoRdDoneToggle <= '0';
1759  EventInfo_dav_i <= '0';
1760  EventInfoToggleSyncRegs <= (others => '0');
1761  L1Ainfo_wa <= (others => '0');
1762  else
1763  if(EventInfoRdDone = '1')then
1764  EventInfoRdDoneToggle <= not EventInfoRdDoneToggle;
1765  end if;
1766  if(AMC_en = '0' or EventInfoRdDone = '1')then
1767  EventInfo_dav_i <= '0';
1768  elsif(EventInfoToggleSyncRegs(3) /= EventInfoToggleSyncRegs(2))then
1769  EventInfo_dav_i <= '1';
1770  end if;
1771  EventInfoToggleSyncRegs <= EventInfoToggleSyncRegs(2 downto 0) & EventInfoToggle;
1772  if(L1A_WrEn = '1' and AMC_en = '1')then
1773  L1Ainfo_wa <= L1Ainfo_wa + 1;
1774  end if;
1775  end if;
1776  end if;
1777 end process;
1778 i_L1Ainfo : BRAM_SDP_MACRO
1779  generic map (
1780  BRAM_SIZE => "18Kb", -- Target BRAM, "18Kb" or "36Kb"
1781  DEVICE => "7SERIES", -- Target device: "VIRTEX5", "VIRTEX6", "7SERIES", "SPARTAN6"
1782  WRITE_WIDTH => 16, -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
1783  READ_WIDTH => 16, -- Valid values are 1-72 (37-72 only valid when BRAM_SIZE="36Kb")
1784  DO_REG => 1, -- Optional output register (0 or 1)
1785  SIM_COLLISION_CHECK => "NONE", -- Collision check enable "ALL", "WARNING_ONLY",
1786  -- "GENERATE_X_ONLY" or "NONE"
1787  WRITE_MODE => "WRITE_FIRST", -- Specify "READ_FIRST" for same clock or synchronous clocks
1788  -- Specify "WRITE_FIRST for asynchrononous clocks on ports
1789  INIT => X"000000000000000000") -- Initial values on output port
1790  port map (
1791  DO => L1AinfoDo, -- Output read data port, width defined by READ_WIDTH parameter
1792  DI => L1A_DATA, -- Input write data port, width defined by WRITE_WIDTH parameter
1793  RDADDR => L1Ainfo_ra, -- Input read address, width defined by read port depth
1794  RDCLK => UsrClk, -- 1-bit input read clock
1795  RDEN => re_L1AinfoDo, -- 1-bit input read port enable
1796  REGCE => re_L1AinfoDo, -- 1-bit input read output register enable
1797  RST => '0', -- 1-bit input reset
1798  WE => "11", -- Input write enable, width defined by write port depth
1799  WRADDR => L1Ainfo_wa, -- Input write address, width defined by write port depth
1800  WRCLK => sysclk, -- 1-bit input write clock
1801  WREN => L1A_WrEn -- 1-bit input write port enable
1802  );
1803 re_L1AinfoDo <= not SendTTS;
1804 g_ReSendQueue : for i in 0 to 15 generate
1805  i_ReSendQueue : SRL16E
1806  port map (
1807  Q => ReSendQueOut(i), -- SRL data output
1808  A0 => ReSendQue_a(0), -- Select[0] input
1809  A1 => ReSendQue_a(1), -- Select[1] input
1810  A2 => '0', -- Select[2] input
1811  A3 => '0', -- Select[3] input
1812  CE => we_ReSendQue, -- Clock enable input
1813  CLK => UsrClk, -- Clock input
1814  D => ReSendQueIn(i) -- SRL data input
1815  );
1816 end generate;
1817 ReSendQueIn <= SEQNUM & L1Ainfo_start;
1818 -- Tx logic
1819 process(UsrClk)
1820 begin
1821  if(UsrClk'event and UsrClk = '1')then
1822  if(InitLink = '1')then
1823  L1Ainfo_ra <= (others => '0');
1824  elsif(ReSend = '1')then
1825  L1Ainfo_ra <= ReSendQueOut(7 downto 0) & "00";
1826  elsif(ec_L1Ainfo_ra = '1' and SendTTS = '0')then
1827  L1Ainfo_ra <= L1Ainfo_ra + 1;
1828  end if;
1829  if(InitLink = '1')then
1830  L1Ainfo_start <= (others => '0');
1831  elsif(ReSend = '1')then
1832  L1Ainfo_start <= ReSendQueOut(7 downto 0);
1833  elsif(we_ReSendQue = '1')then
1834  L1Ainfo_start <= L1Ainfo_ra(9 downto 2);
1835  end if;
1836  if(InitLink = '1')then
1837  L1Ainfo_wa2SyncRegs <= (others => '0');
1838  else
1839  L1Ainfo_wa2SyncRegs <= L1Ainfo_wa2SyncRegs(2 downto 0) & L1Ainfo_wa(2);
1840  end if;
1841  if(InitLink = '1')then
1842  L1Ainfo_wap <= (others => '0');
1843  elsif(L1Ainfo_wa2SyncRegs(3) /= L1Ainfo_wa2SyncRegs(2))then
1844  L1Ainfo_wap <= L1Ainfo_wap + 1;
1845  end if;
1846  if(InitLink = '1' or L1Ainfo_wap = L1Ainfo_ra(9 downto 2))then
1847  L1Ainfo_empty <= '1';
1848  else
1849  L1Ainfo_empty <= '0';
1850  end if;
1851  if(reset_SyncRegs(3) = '1')then
1852  InitLink <= '1';
1853  elsif(ACK = '1' or test = '1')then
1854  InitLink <= '0';
1855  end if;
1856  if(reset_SyncRegs(3) = '1' or ReSend = '1')then
1857  ReSendQue_a <= (others => '1');
1858  elsif(we_ReSendQue = '1' and ACK = '0')then
1859  ReSendQue_a <= ReSendQue_a + 1;
1860  elsif(we_ReSendQue = '0' and ACK = '1' and ReSendQue_a /= "11")then
1861  ReSendQue_a <= ReSendQue_a - 1;
1862  end if;
1863  if(TxState = SendWC and Resend = '0'and SendTTS = '0' and (L1ASent = '1' or InitLink = '1'))then
1864  we_ReSendQue <= '1';
1865  else
1866  we_ReSendQue <= '0';
1867  end if;
1868  if(ReSendQue_a = "10")then
1869  ReSendQue_full <= '1';
1870  else
1871  ReSendQue_full <= '0';
1872  end if;
1873  if(reset_SyncRegs(3) = '1' or ReSend = '1')then
1874  ReSendQue_empty <= '1';
1875  elsif(we_ReSendQue = '1')then
1876  ReSendQue_empty <= '0';
1877  elsif(ACK = '1' and ReSendQue_a = "00")then
1878  ReSendQue_empty <= '1';
1879  end if;
1880  if(InitLink = '1')then
1881  SEQNUM <= x"01";
1882  elsif(ReSend = '1')then
1883  SEQNUM <= ReSendQueOut(15 downto 8);
1884  elsif(we_ReSendQue = '1')then
1885  SEQNUM <= SEQNUM(6 downto 0) & not(SEQNUM(7) xor SEQNUM(5) xor SEQNUM(4) xor SEQNUM(3));
1886  end if;
1887  if(reset_SyncRegs(3) = '1')then
1888  got_comma <= '0';
1889  elsif(RXCHARISCOMMA = "11")then
1890  got_comma <= '1';
1891  end if;
1892  if(AMCRdy = '0' or reset_SyncRegs(3) = '1' or ReSend = '1')then
1893  TxState <= IDLE;
1894  ec_L1Ainfo_ra <= '0';
1895  elsif(SendTTS = '0')then
1896  case TxState is
1897  when IDLE => -- send R_word (idle)
1898  TxState <= SendK;
1899  ec_L1Ainfo_ra <= '0';
1900  when SendK => -- send K_word
1901  if((ReSend_l = '1' and InitLink = '1') or (ReSendQue_full = '0' and L1Ainfo_empty = '0') or ACKNUM_empty = '0' or GotCntr = '1')then
1902  TxState <= SendSEQ;
1903  else
1904  TxState <= IDLE;
1905  end if;
1906  if(InitLink = '1')then
1907  L1ASent <= '0';
1908  IsACK <= '0';
1909  TxType <= InitRqst;
1910  elsif(GotCntr = '1')then
1911  L1ASent <= '0';
1912  IsACK <= '0';
1913  TxType <= Counter;
1914  elsif(ReSendQue_full = '0' and L1Ainfo_empty = '0')then
1915  L1ASent <= '1';
1916  ec_L1Ainfo_ra <= '1';
1917  IsACK <= '0';
1918  TxType <= data;
1919  else
1920  L1ASent <= '0';
1921  IsACK <= '1';
1922  TxType <= Acknowledge;
1923  end if;
1924  when SendSEQ => -- send packet type
1925  TxState <= SendType;
1926  if(IsACK = '0')then
1927  ACKNUM_MUX <= CntrACKNUM;
1928  else
1929  ACKNUM_MUX <= ACKNUM_l;
1930  end if;
1931  when SendType => -- send packet_seq
1932  if(L1Asent = '0')then
1933  TxState <= SendWC;
1934  else
1935  TxState <= SendData;
1936  end if;
1937  when SendWC => -- send packet_wc
1938  TxState <= WaitCRC;
1939  when WaitCRC => -- wait for CRC
1940  TxState <= SendCRC;
1941  when SendData => -- send L1A info
1942  if(packet_wc = "11")then
1943  TxState <= SendWC;
1944  end if;
1945  if(packet_wc = "01")then
1946  ec_L1Ainfo_ra <= '0';
1947  end if;
1948  when others => TxState <= IDLE;
1949  end case;
1950  end if;
1951  if(TxState = SendK)then
1952  packet_wc <= (others => '0');
1953  elsif(TxState = SendData and SendTTS = '0')then
1954  packet_wc(1) <= packet_wc(1) xor packet_wc(0);
1955  packet_wc(0) <= not packet_wc(0);
1956  end if;
1957  if(is_TTS = '1' or TTS_wait(7) = '1' or (InitLink = '1' and ACK = '1'))then
1958  SendTTS <= '1';
1959  else
1960  SendTTS <= '0';
1961  end if;
1962  if(SendTTS = '1')then
1963  TXDATA_i <= TTS & x"5c";
1964  TxIsK <= '1';
1965  TXCHARISK <= "01";
1966  else
1967  case TxState is
1968  when SendK => TXDATA_i <= K_word;
1969  when SendData => TXDATA_i <= L1AinfoDo;
1970  when SendSEQ => TXDATA_i <= SEQNUM & TxType;
1971  when SendType => TXDATA_i <= ACKNUM_MUX & x"0" & AMC_IDp1;
1972  when SendWC => TXDATA_i <= x"000" & '0' & L1Asent & "00";
1973  when SendCRC => TXDATA_i <= TxCRC;
1974  when others => TXDATA_i <= R_word;
1975  end case;
1976  case TxState is
1977  when IDLE | SendK | WaitCRC => TxIsK <= '1';
1978  TXCHARISK <= "11";
1979  when others => TxIsK <= '0';
1980  TXCHARISK <= "00";
1981  end case;
1982  end if;
1983  if(TxState = IDLE or TxState = SendK)then
1984  Init_TxCRC <= '1';
1985  else
1986  Init_TxCRC <= '0';
1987  end if;
1988  end if;
1989 end process;
1990 i_TxCRC: crc16D16 PORT MAP(
1991  clk => UsrClk ,
1992  init_crc => Init_TxCRC,
1993  we_crc => we_TxCRC,
1994  d => TXDATA_i,
1995  crc => TxCRC
1996  );
1997 we_TxCRC <= not TxIsK;
1998 end Behavioral;
1999 
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