AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
 All Classes Variables
uhtr_trig_init.vhd
1 ------------------------------------------------------------------------------
2 -- ____ ____
3 -- / /\/ /
4 -- /___/ \ / Vendor: Xilinx
5 -- \ \ \/ Version : 2.7
6 -- \ \ Application : 7 Series FPGAs Transceivers Wizard
7 -- / / Filename : uhtr_trig_init.vhd
8 -- /___/ /\
9 -- \ \ / \
10 -- \___\/\___\
11 --
12 -- Description : This module instantiates the modules required for
13 -- reset and initialisation of the Transceiver
14 --
15 -- Module uHTR_trig_init
16 -- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
17 --
18 --
19 -- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
20 --
21 -- This file contains confidential and proprietary information
22 -- of Xilinx, Inc. and is protected under U.S. and
23 -- international copyright and other intellectual property
24 -- laws.
25 --
26 -- DISCLAIMER
27 -- This disclaimer is not a license and does not grant any
28 -- rights to the materials distributed herewith. Except as
29 -- otherwise provided in a valid license issued to you by
30 -- Xilinx, and to the maximum extent permitted by applicable
31 -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
32 -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
33 -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
34 -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
35 -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
36 -- (2) Xilinx shall not be liable (whether in contract or tort,
37 -- including negligence, or under any other theory of
38 -- liability) for any loss or damage of any kind or nature
39 -- related to, arising under or in connection with these
40 -- materials, including for any direct, or any indirect,
41 -- special, incidental, or consequential loss or damage
42 -- (including loss of data, profits, goodwill, or any type of
43 -- loss or damage suffered as a result of any action brought
44 -- by a third party) even if such damage or loss was
45 -- reasonably foreseeable or Xilinx had been advised of the
46 -- possibility of the same.
47 --
48 -- CRITICAL APPLICATIONS
49 -- Xilinx products are not designed or intended to be fail-
50 -- safe, or for use in any application requiring fail-safe
51 -- performance, such as life-support or safety devices or
52 -- systems, Class III medical devices, nuclear facilities,
53 -- applications related to the deployment of airbags, or any
54 -- other applications that could lead to death, personal
55 -- injury, or severe property or environmental damage
56 -- (individually and collectively, "Critical
57 -- Applications"). Customer assumes the sole risk and
58 -- liability of any use of Xilinx products in Critical
59 -- Applications, subject only to applicable laws and
60 -- regulations governing limitations on product liability.
61 --
62 -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
63 -- PART OF THIS FILE AT ALL TIMES.
64 
65 
66 library ieee;
67 use ieee.std_logic_1164.all;
68 use ieee.numeric_std.all;
69 use ieee.std_logic_unsigned.all;
70 library UNISIM;
71 use UNISIM.VCOMPONENTS.ALL;
72 
73 --***********************************Entity Declaration************************
74 
75 entity uHTR_trig_init is
76 generic
77 (
78  EXAMPLE_SIM_GTRESET_SPEEDUP : string := "TRUE"; -- simulation setting for GT SecureIP model
79  EXAMPLE_SIMULATION : integer := 0; -- Set to 1 for simulation
80  STABLE_CLOCK_PERIOD : integer := 20; --Period of the stable clock driving this state-machine, unit is [ns]
81  EXAMPLE_USE_CHIPSCOPE : integer := 0 -- Set to 1 to use Chipscope to drive resets
82 
83 );
84 port
85 (
86  SYSCLK_IN : in std_logic;
87  SOFT_RESET_IN : in std_logic;
88  DONT_RESET_ON_DATA_ERROR_IN : in std_logic;
89  GT0_TX_FSM_RESET_DONE_OUT : out std_logic;
90  GT0_RX_FSM_RESET_DONE_OUT : out std_logic;
91  GT0_DATA_VALID_IN : in std_logic;
92 
93  --_________________________________________________________________________
94  --GT0 (X1Y12)
95  --____________________________CHANNEL PORTS________________________________
96  --------------------------------- CPLL Ports -------------------------------
97  GT0_CPLLFBCLKLOST_OUT : out std_logic;
98  GT0_CPLLLOCK_OUT : out std_logic;
99  GT0_CPLLLOCKDETCLK_IN : in std_logic;
100  GT0_CPLLRESET_IN : in std_logic;
101  -------------------------- Channel - Clocking Ports ------------------------
102  GT0_GTREFCLK0_IN : in std_logic;
103  ---------------------------- Channel - DRP Ports --------------------------
104  GT0_DRPADDR_IN : in std_logic_vector(8 downto 0);
105  GT0_DRPCLK_IN : in std_logic;
106  GT0_DRPDI_IN : in std_logic_vector(15 downto 0);
107  GT0_DRPDO_OUT : out std_logic_vector(15 downto 0);
108  GT0_DRPEN_IN : in std_logic;
109  GT0_DRPRDY_OUT : out std_logic;
110  GT0_DRPWE_IN : in std_logic;
111  --------------------- RX Initialization and Reset Ports --------------------
112  GT0_RXUSERRDY_IN : in std_logic;
113  -------------------------- RX Margin Analysis Ports ------------------------
114  GT0_EYESCANDATAERROR_OUT : out std_logic;
115  ------------------------- Receive Ports - CDR Ports ------------------------
116  GT0_RXCDRLOCK_OUT : out std_logic;
117  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
118  GT0_RXUSRCLK_IN : in std_logic;
119  GT0_RXUSRCLK2_IN : in std_logic;
120  ------------------ Receive Ports - FPGA RX interface Ports -----------------
121  GT0_RXDATA_OUT : out std_logic_vector(31 downto 0);
122  ------------------- Receive Ports - Pattern Checker Ports ------------------
123  GT0_RXPRBSERR_OUT : out std_logic;
124  GT0_RXPRBSSEL_IN : in std_logic_vector(2 downto 0);
125  ------------------- Receive Ports - Pattern Checker ports ------------------
126  GT0_RXPRBSCNTRESET_IN : in std_logic;
127  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
128  GT0_RXDISPERR_OUT : out std_logic_vector(3 downto 0);
129  GT0_RXNOTINTABLE_OUT : out std_logic_vector(3 downto 0);
130  --------------------------- Receive Ports - RX AFE -------------------------
131  GT0_GTXRXP_IN : in std_logic;
132  ------------------------ Receive Ports - RX AFE Ports ----------------------
133  GT0_GTXRXN_IN : in std_logic;
134  ------------- Receive Ports - RX Initialization and Reset Ports ------------
135  GT0_GTRXRESET_IN : in std_logic;
136  GT0_RXPMARESET_IN : in std_logic;
137  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
138  GT0_RXCHARISK_OUT : out std_logic_vector(3 downto 0);
139  -------------- Receive Ports -RX Initialization and Reset Ports ------------
140  GT0_RXRESETDONE_OUT : out std_logic;
141  --------------------- TX Initialization and Reset Ports --------------------
142  GT0_GTTXRESET_IN : in std_logic;
143  GT0_TXUSERRDY_IN : in std_logic;
144  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
145  GT0_TXUSRCLK_IN : in std_logic;
146  GT0_TXUSRCLK2_IN : in std_logic;
147  ------------------ Transmit Ports - TX Data Path interface -----------------
148  GT0_TXDATA_IN : in std_logic_vector(31 downto 0);
149  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
150  GT0_GTXTXN_OUT : out std_logic;
151  GT0_GTXTXP_OUT : out std_logic;
152  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
153  GT0_TXOUTCLK_OUT : out std_logic;
154  GT0_TXOUTCLKFABRIC_OUT : out std_logic;
155  GT0_TXOUTCLKPCS_OUT : out std_logic;
156  --------------------- Transmit Ports - TX Gearbox Ports --------------------
157  GT0_TXCHARISK_IN : in std_logic_vector(3 downto 0);
158  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
159  GT0_TXRESETDONE_OUT : out std_logic;
160  ------------------ Transmit Ports - pattern Generator Ports ----------------
161  GT0_TXPRBSSEL_IN : in std_logic_vector(2 downto 0);
162 
163 
164  --____________________________COMMON PORTS________________________________
165  ---------------------- Common Block - Ref Clock Ports ---------------------
166  GT0_GTREFCLK0_COMMON_IN : in std_logic;
167  ------------------------- Common Block - QPLL Ports ------------------------
168  GT0_QPLLLOCK_OUT : out std_logic;
169  GT0_QPLLLOCKDETCLK_IN : in std_logic;
170  GT0_QPLLRESET_IN : in std_logic
171 
172 
173 );
174 
175 end uHTR_trig_init;
176 
177 architecture RTL of uHTR_trig_init is
178 
179 --**************************Component Declarations*****************************
180 
181 
182 component uHTR_trig
183 generic
184 (
185  -- Simulation attributes
186  WRAPPER_SIM_GTRESET_SPEEDUP : string := "FALSE" -- Set to 1 to speed up sim reset
187 
188 );
189 port
190 (
191 
192  --_________________________________________________________________________
193  --_________________________________________________________________________
194  --GT0 (X1Y12)
195  --____________________________CHANNEL PORTS________________________________
196  --------------------------------- CPLL Ports -------------------------------
197  GT0_CPLLFBCLKLOST_OUT : out std_logic;
198  GT0_CPLLLOCK_OUT : out std_logic;
199  GT0_CPLLLOCKDETCLK_IN : in std_logic;
200  GT0_CPLLREFCLKLOST_OUT : out std_logic;
201  GT0_CPLLRESET_IN : in std_logic;
202  -------------------------- Channel - Clocking Ports ------------------------
203  GT0_GTREFCLK0_IN : in std_logic;
204  ---------------------------- Channel - DRP Ports --------------------------
205  GT0_DRPADDR_IN : in std_logic_vector(8 downto 0);
206  GT0_DRPCLK_IN : in std_logic;
207  GT0_DRPDI_IN : in std_logic_vector(15 downto 0);
208  GT0_DRPDO_OUT : out std_logic_vector(15 downto 0);
209  GT0_DRPEN_IN : in std_logic;
210  GT0_DRPRDY_OUT : out std_logic;
211  GT0_DRPWE_IN : in std_logic;
212  --------------------- RX Initialization and Reset Ports --------------------
213  GT0_RXUSERRDY_IN : in std_logic;
214  -------------------------- RX Margin Analysis Ports ------------------------
215  GT0_EYESCANDATAERROR_OUT : out std_logic;
216  ------------------------- Receive Ports - CDR Ports ------------------------
217  GT0_RXCDRLOCK_OUT : out std_logic;
218  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
219  GT0_RXUSRCLK_IN : in std_logic;
220  GT0_RXUSRCLK2_IN : in std_logic;
221  ------------------ Receive Ports - FPGA RX interface Ports -----------------
222  GT0_RXDATA_OUT : out std_logic_vector(31 downto 0);
223  ------------------- Receive Ports - Pattern Checker Ports ------------------
224  GT0_RXPRBSERR_OUT : out std_logic;
225  GT0_RXPRBSSEL_IN : in std_logic_vector(2 downto 0);
226  ------------------- Receive Ports - Pattern Checker ports ------------------
227  GT0_RXPRBSCNTRESET_IN : in std_logic;
228  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
229  GT0_RXDISPERR_OUT : out std_logic_vector(3 downto 0);
230  GT0_RXNOTINTABLE_OUT : out std_logic_vector(3 downto 0);
231  --------------------------- Receive Ports - RX AFE -------------------------
232  GT0_GTXRXP_IN : in std_logic;
233  ------------------------ Receive Ports - RX AFE Ports ----------------------
234  GT0_GTXRXN_IN : in std_logic;
235  -------------------- Receive Ports - RX Equailizer Ports -------------------
236  GT0_RXLPMHFHOLD_IN : in std_logic;
237  GT0_RXLPMLFHOLD_IN : in std_logic;
238  --------------- Receive Ports - RX Fabric Output Control Ports -------------
239  GT0_RXOUTCLK_OUT : out std_logic;
240  ------------- Receive Ports - RX Initialization and Reset Ports ------------
241  GT0_GTRXRESET_IN : in std_logic;
242  GT0_RXPMARESET_IN : in std_logic;
243  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
244  GT0_RXCHARISK_OUT : out std_logic_vector(3 downto 0);
245  -------------- Receive Ports -RX Initialization and Reset Ports ------------
246  GT0_RXRESETDONE_OUT : out std_logic;
247  --------------------- TX Initialization and Reset Ports --------------------
248  GT0_GTTXRESET_IN : in std_logic;
249  GT0_TXUSERRDY_IN : in std_logic;
250  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
251  GT0_TXUSRCLK_IN : in std_logic;
252  GT0_TXUSRCLK2_IN : in std_logic;
253  ------------------ Transmit Ports - TX Data Path interface -----------------
254  GT0_TXDATA_IN : in std_logic_vector(31 downto 0);
255  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
256  GT0_GTXTXN_OUT : out std_logic;
257  GT0_GTXTXP_OUT : out std_logic;
258  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
259  GT0_TXOUTCLK_OUT : out std_logic;
260  GT0_TXOUTCLKFABRIC_OUT : out std_logic;
261  GT0_TXOUTCLKPCS_OUT : out std_logic;
262  --------------------- Transmit Ports - TX Gearbox Ports --------------------
263  GT0_TXCHARISK_IN : in std_logic_vector(3 downto 0);
264  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
265  GT0_TXRESETDONE_OUT : out std_logic;
266  ------------------ Transmit Ports - pattern Generator Ports ----------------
267  GT0_TXPRBSSEL_IN : in std_logic_vector(2 downto 0);
268 
269 
270  --____________________________COMMON PORTS________________________________
271  ---------------------- Common Block - Ref Clock Ports ---------------------
272  GT0_GTREFCLK0_COMMON_IN : in std_logic;
273  ------------------------- Common Block - QPLL Ports ------------------------
274  GT0_QPLLLOCK_OUT : out std_logic;
275  GT0_QPLLLOCKDETCLK_IN : in std_logic;
276  GT0_QPLLREFCLKLOST_OUT : out std_logic;
277  GT0_QPLLRESET_IN : in std_logic
278 
279 
280 );
281 end component;
282 
283 component uHTR_trig_TX_STARTUP_FSM
284  Generic(
285  GT_TYPE : string := "GTX";
286  STABLE_CLOCK_PERIOD : integer range 4 to 250 := 8; --Period of the stable clock driving this state-machine, unit is [ns]
287  RETRY_COUNTER_BITWIDTH : integer range 2 to 8 := 8;
288  TX_QPLL_USED : boolean := False; -- the TX and RX Reset FSMs must
289  RX_QPLL_USED : boolean := False; -- share these two generic values
290  PHASE_ALIGNMENT_MANUAL : boolean := True -- Decision if a manual phase-alignment is necessary or the automatic
291  -- is enough. For single-lane applications the automatic alignment is
292  -- sufficient
293  );
294  Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB
295  --or reference-clock present at startup.
296  TXUSERCLK : in STD_LOGIC; --TXUSERCLK as used in the design
297  SOFT_RESET : in STD_LOGIC; --User Reset, can be pulled any time
298  QPLLREFCLKLOST : in STD_LOGIC; --QPLL Reference-clock for the GT is lost
299  CPLLREFCLKLOST : in STD_LOGIC; --CPLL Reference-clock for the GT is lost
300  QPLLLOCK : in STD_LOGIC; --Lock Detect from the QPLL of the GT
301  CPLLLOCK : in STD_LOGIC; --Lock Detect from the CPLL of the GT
302  TXRESETDONE : in STD_LOGIC;
303  MMCM_LOCK : in STD_LOGIC;
304  GTTXRESET : out STD_LOGIC:='0';
305  MMCM_RESET : out STD_LOGIC:='0';
306  QPLL_RESET : out STD_LOGIC:='0'; --Reset QPLL
307  CPLL_RESET : out STD_LOGIC:='0'; --Reset CPLL
308  TX_FSM_RESET_DONE : out STD_LOGIC:='0'; --Reset-sequence has sucessfully been finished.
309  TXUSERRDY : out STD_LOGIC:='0';
310  RUN_PHALIGNMENT : out STD_LOGIC:='0';
311  RESET_PHALIGNMENT : out STD_LOGIC:='0';
312  PHALIGNMENT_DONE : in STD_LOGIC;
313 
314  RETRY_COUNTER : out STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of
315  -- Retries it took to get the transceiver up and running
316  );
317 end component;
318 
319 component uHTR_trig_RX_STARTUP_FSM
320  Generic(
321  EXAMPLE_SIMULATION : integer := 0;
322  EQ_MODE : string := "DFE";
323  GT_TYPE : string := "GTX";
324  STABLE_CLOCK_PERIOD : integer range 4 to 250 := 8; --Period of the stable clock driving this state-machine, unit is [ns]
325  RETRY_COUNTER_BITWIDTH : integer range 2 to 8 := 8;
326  TX_QPLL_USED : boolean := False; -- the TX and RX Reset FSMs must
327  RX_QPLL_USED : boolean := False; -- share these two generic values
328  PHASE_ALIGNMENT_MANUAL : boolean := True -- Decision if a manual phase-alignment is necessary or the automatic
329  -- is enough. For single-lane applications the automatic alignment is
330  -- sufficient
331  );
332  Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB
333  --or reference-clock present at startup.
334  RXUSERCLK : in STD_LOGIC; --RXUSERCLK as used in the design
335  SOFT_RESET : in STD_LOGIC; --User Reset, can be pulled any time
336  QPLLREFCLKLOST : in STD_LOGIC; --QPLL Reference-clock for the GT is lost
337  CPLLREFCLKLOST : in STD_LOGIC; --CPLL Reference-clock for the GT is lost
338  QPLLLOCK : in STD_LOGIC; --Lock Detect from the QPLL of the GT
339  CPLLLOCK : in STD_LOGIC; --Lock Detect from the CPLL of the GT
340  RXRESETDONE : in STD_LOGIC;
341  MMCM_LOCK : in STD_LOGIC;
342  RECCLK_STABLE : in STD_LOGIC;
343  RECCLK_MONITOR_RESTART : in STD_LOGIC;
344  DATA_VALID : in STD_LOGIC;
345  TXUSERRDY : in STD_LOGIC; --TXUSERRDY from GT
346  DONT_RESET_ON_DATA_ERROR : in STD_LOGIC;
347  GTRXRESET : out STD_LOGIC:='0';
348  MMCM_RESET : out STD_LOGIC:='0';
349  QPLL_RESET : out STD_LOGIC:='0'; --Reset QPLL (only if RX uses QPLL)
350  CPLL_RESET : out STD_LOGIC:='0'; --Reset CPLL (only if RX uses CPLL)
351  RX_FSM_RESET_DONE : out STD_LOGIC:='0'; --Reset-sequence has sucessfully been finished.
352  RXUSERRDY : out STD_LOGIC:='0';
353  RUN_PHALIGNMENT : out STD_LOGIC;
354  PHALIGNMENT_DONE : in STD_LOGIC;
355  RESET_PHALIGNMENT : out STD_LOGIC:='0';
356  RXDFEAGCHOLD : out STD_LOGIC;
357  RXDFELFHOLD : out STD_LOGIC;
358  RXLPMLFHOLD : out STD_LOGIC;
359  RXLPMHFHOLD : out STD_LOGIC;
360  RETRY_COUNTER : out STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of
361  -- Retries it took to get the transceiver up and running
362  );
363 end component;
364 
365 
366 
367 
368 
369 
370  function get_cdrlock_time(is_sim : in integer) return integer is
371  variable lock_time: integer;
372  begin
373  if (is_sim = 1) then
374  lock_time := 1000;
375  else
376  lock_time := 50000 / integer(1.6); --Typical CDR lock time is 50,000UI as per DS183
377  end if;
378  return lock_time;
379  end function;
380 
381 
382 --***********************************Parameter Declarations********************
383 
384  constant DLY : time := 1 ns;
385  constant RX_CDRLOCK_TIME : integer := get_cdrlock_time(EXAMPLE_SIMULATION); -- 200us
386  constant WAIT_TIME_CDRLOCK : integer := RX_CDRLOCK_TIME / STABLE_CLOCK_PERIOD; -- 200 us time-out
387 
388  -------------------------- GT Wrapper Wires ------------------------------
389  signal gt0_cpllreset_i : std_logic;
390  signal gt0_cpllreset_t : std_logic;
391  signal gt0_cpllrefclklost_i : std_logic;
392  signal gt0_cplllock_i : std_logic;
393  signal gt0_txresetdone_i : std_logic;
394  signal gt0_rxresetdone_i : std_logic;
395  signal gt0_gttxreset_i : std_logic;
396  signal gt0_gttxreset_t : std_logic;
397  signal gt0_gtrxreset_i : std_logic;
398  signal gt0_gtrxreset_t : std_logic;
399  signal gt0_rxdfelpmreset_i : std_logic;
400  signal gt0_txuserrdy_i : std_logic;
401  signal gt0_txuserrdy_t : std_logic;
402  signal gt0_rxuserrdy_i : std_logic;
403  signal gt0_rxuserrdy_t : std_logic;
404 
405  signal gt0_rxdfeagchold_i : std_logic;
406  signal gt0_rxdfelfhold_i : std_logic;
407  signal gt0_rxlpmlfhold_i : std_logic;
408  signal gt0_rxlpmhfhold_i : std_logic;
409 
410 
411 
412  signal gt0_qpllreset_i : std_logic;
413  signal gt0_qpllreset_t : std_logic;
414  signal gt0_qpllrefclklost_i : std_logic;
415  signal gt0_qplllock_i : std_logic;
416 
417 
418  ------------------------------- Global Signals -----------------------------
419  signal tied_to_ground_i : std_logic;
420  signal tied_to_vcc_i : std_logic;
421 
422  signal gt0_rxoutclk_i : std_logic;
423  signal gt0_recclk_stable_i : std_logic;
424 
425 
426 
427 
428 
429 
430  signal rx_cdrlock_counter : integer range 0 to WAIT_TIME_CDRLOCK:= 0 ;
431  signal rx_cdrlocked : std_logic;
432 
433 
434 
435 
436 
437 --**************************** Main Body of Code *******************************
438 begin
439  -- Static signal Assigments
440  tied_to_ground_i <= '0';
441  tied_to_vcc_i <= '1';
442 
443  ----------------------------- The GT Wrapper -----------------------------
444 
445  -- Use the instantiation template in the example directory to add the GT wrapper to your design.
446  -- In this example, the wrapper is wired up for basic operation with a frame generator and frame
447  -- checker. The GTs will reset, then attempt to align and transmit data. If channel bonding is
448  -- enabled, bonding should occur after alignment.
449 
450 
451  uHTR_trig_i : uHTR_trig
452  generic map
453  (
454  WRAPPER_SIM_GTRESET_SPEEDUP => EXAMPLE_SIM_GTRESET_SPEEDUP
455  )
456  port map
457  (
458 
459  --_____________________________________________________________________
460  --_____________________________________________________________________
461  --GT0 (X1Y12)
462 
463  --------------------------------- CPLL Ports -------------------------------
464  GT0_CPLLFBCLKLOST_OUT => GT0_CPLLFBCLKLOST_OUT ,
465  GT0_CPLLLOCK_OUT => gt0_cplllock_i,
466  GT0_CPLLLOCKDETCLK_IN => GT0_CPLLLOCKDETCLK_IN ,
467  GT0_CPLLREFCLKLOST_OUT => gt0_cpllrefclklost_i ,
468  GT0_CPLLRESET_IN => gt0_cpllreset_i,
469  -------------------------- Channel - Clocking Ports ------------------------
470  GT0_GTREFCLK0_IN => GT0_GTREFCLK0_IN,
471  ---------------------------- Channel - DRP Ports --------------------------
472  GT0_DRPADDR_IN => GT0_DRPADDR_IN,
473  GT0_DRPCLK_IN => GT0_DRPCLK_IN,
474  GT0_DRPDI_IN => GT0_DRPDI_IN,
475  GT0_DRPDO_OUT => GT0_DRPDO_OUT,
476  GT0_DRPEN_IN => GT0_DRPEN_IN,
477  GT0_DRPRDY_OUT => GT0_DRPRDY_OUT,
478  GT0_DRPWE_IN => GT0_DRPWE_IN,
479  --------------------- RX Initialization and Reset Ports --------------------
480  GT0_RXUSERRDY_IN => gt0_rxuserrdy_i,
481  -------------------------- RX Margin Analysis Ports ------------------------
482  GT0_EYESCANDATAERROR_OUT => GT0_EYESCANDATAERROR_OUT,
483  ------------------------- Receive Ports - CDR Ports ------------------------
484  GT0_RXCDRLOCK_OUT => GT0_RXCDRLOCK_OUT,
485  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
486  GT0_RXUSRCLK_IN => GT0_RXUSRCLK_IN,
487  GT0_RXUSRCLK2_IN => GT0_RXUSRCLK2_IN,
488  ------------------ Receive Ports - FPGA RX interface Ports -----------------
489  GT0_RXDATA_OUT => GT0_RXDATA_OUT,
490  ------------------- Receive Ports - Pattern Checker Ports ------------------
491  GT0_RXPRBSERR_OUT => GT0_RXPRBSERR_OUT,
492  GT0_RXPRBSSEL_IN => GT0_RXPRBSSEL_IN,
493  ------------------- Receive Ports - Pattern Checker ports ------------------
494  GT0_RXPRBSCNTRESET_IN => GT0_RXPRBSCNTRESET_IN ,
495  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
496  GT0_RXDISPERR_OUT => GT0_RXDISPERR_OUT,
497  GT0_RXNOTINTABLE_OUT => GT0_RXNOTINTABLE_OUT ,
498  --------------------------- Receive Ports - RX AFE -------------------------
499  GT0_GTXRXP_IN => GT0_GTXRXP_IN,
500  ------------------------ Receive Ports - RX AFE Ports ----------------------
501  GT0_GTXRXN_IN => GT0_GTXRXN_IN,
502  -------------------- Receive Ports - RX Equailizer Ports -------------------
503  GT0_RXLPMHFHOLD_IN => gt0_rxlpmhfhold_i,
504  GT0_RXLPMLFHOLD_IN => gt0_rxlpmlfhold_i,
505  --------------- Receive Ports - RX Fabric Output Control Ports -------------
506  GT0_RXOUTCLK_OUT => gt0_rxoutclk_i,
507  ------------- Receive Ports - RX Initialization and Reset Ports ------------
508  GT0_GTRXRESET_IN => gt0_gtrxreset_i,
509  GT0_RXPMARESET_IN => GT0_RXPMARESET_IN,
510  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
511  GT0_RXCHARISK_OUT => GT0_RXCHARISK_OUT,
512  -------------- Receive Ports -RX Initialization and Reset Ports ------------
513  GT0_RXRESETDONE_OUT => gt0_rxresetdone_i,
514  --------------------- TX Initialization and Reset Ports --------------------
515  GT0_GTTXRESET_IN => gt0_gttxreset_i,
516  GT0_TXUSERRDY_IN => gt0_txuserrdy_i,
517  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
518  GT0_TXUSRCLK_IN => GT0_TXUSRCLK_IN,
519  GT0_TXUSRCLK2_IN => GT0_TXUSRCLK2_IN,
520  ------------------ Transmit Ports - TX Data Path interface -----------------
521  GT0_TXDATA_IN => GT0_TXDATA_IN,
522  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
523  GT0_GTXTXN_OUT => GT0_GTXTXN_OUT,
524  GT0_GTXTXP_OUT => GT0_GTXTXP_OUT,
525  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
526  GT0_TXOUTCLK_OUT => GT0_TXOUTCLK_OUT,
527  GT0_TXOUTCLKFABRIC_OUT => GT0_TXOUTCLKFABRIC_OUT ,
528  GT0_TXOUTCLKPCS_OUT => GT0_TXOUTCLKPCS_OUT ,
529  --------------------- Transmit Ports - TX Gearbox Ports --------------------
530  GT0_TXCHARISK_IN => GT0_TXCHARISK_IN,
531  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
532  GT0_TXRESETDONE_OUT => gt0_txresetdone_i,
533  ------------------ Transmit Ports - pattern Generator Ports ----------------
534  GT0_TXPRBSSEL_IN => GT0_TXPRBSSEL_IN,
535 
536 
537 
538 
539  --____________________________COMMON PORTS________________________________
540  ---------------------- Common Block - Ref Clock Ports ---------------------
541  GT0_GTREFCLK0_COMMON_IN => GT0_GTREFCLK0_COMMON_IN ,
542  ------------------------- Common Block - QPLL Ports ------------------------
543  GT0_QPLLLOCK_OUT => gt0_qplllock_i,
544  GT0_QPLLLOCKDETCLK_IN => GT0_QPLLLOCKDETCLK_IN ,
545  GT0_QPLLREFCLKLOST_OUT => gt0_qpllrefclklost_i ,
546  GT0_QPLLRESET_IN => gt0_qpllreset_i
547 
548  );
549 
550 
551  gt0_rxdfelpmreset_i <= tied_to_ground_i;
552 
553 
554 
555 
556  GT0_CPLLLOCK_OUT <= gt0_cplllock_i;
557  GT0_TXRESETDONE_OUT <= gt0_txresetdone_i;
558  GT0_RXRESETDONE_OUT <= gt0_rxresetdone_i;
559  GT0_QPLLLOCK_OUT <= gt0_qplllock_i;
560 
561 chipscope : if EXAMPLE_USE_CHIPSCOPE = 1 generate
562  gt0_cpllreset_i <= GT0_CPLLRESET_IN or gt0_cpllreset_t;
563  gt0_gttxreset_i <= GT0_GTTXRESET_IN or gt0_gttxreset_t;
564  gt0_gtrxreset_i <= GT0_GTRXRESET_IN or gt0_gtrxreset_t;
565  gt0_txuserrdy_i <= GT0_TXUSERRDY_IN or gt0_txuserrdy_t;
566  gt0_rxuserrdy_i <= GT0_RXUSERRDY_IN or gt0_rxuserrdy_t;
567  gt0_qpllreset_i <= GT0_QPLLRESET_IN or gt0_qpllreset_t;
568 end generate chipscope;
569 
570 no_chipscope : if EXAMPLE_USE_CHIPSCOPE = 0 generate
571  gt0_cpllreset_i <= gt0_cpllreset_t;
572  gt0_gttxreset_i <= gt0_gttxreset_t;
573  gt0_gtrxreset_i <= gt0_gtrxreset_t;
574  gt0_txuserrdy_i <= gt0_txuserrdy_t;
575  gt0_rxuserrdy_i <= gt0_rxuserrdy_t;
576  gt0_qpllreset_i <= gt0_qpllreset_t;
577 end generate no_chipscope;
578 
579 
580 gt0_txresetfsm_i: uHTR_trig_TX_STARTUP_FSM
581 
582  generic map(
583  GT_TYPE => "GTX", --GTX or GTH or GTP
584  STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, -- Period of the stable clock driving this state-machine, unit is [ns]
585  RETRY_COUNTER_BITWIDTH => 8,
586  TX_QPLL_USED => FALSE , -- the TX and RX Reset FSMs must
587  RX_QPLL_USED => FALSE, -- share these two generic values
588  PHASE_ALIGNMENT_MANUAL => FALSE -- Decision if a manual phase-alignment is necessary or the automatic
589  -- is enough. For single-lane applications the automatic alignment is
590  -- sufficient
591  )
592  port map (
593  STABLE_CLOCK => SYSCLK_IN,
594  TXUSERCLK => GT0_TXUSRCLK_IN,
595  SOFT_RESET => SOFT_RESET_IN,
596  QPLLREFCLKLOST => tied_to_ground_i,
597  CPLLREFCLKLOST => gt0_cpllrefclklost_i ,
598  QPLLLOCK => tied_to_vcc_i,
599  CPLLLOCK => gt0_cplllock_i,
600  TXRESETDONE => gt0_txresetdone_i,
601  MMCM_LOCK => tied_to_vcc_i,
602  GTTXRESET => gt0_gttxreset_t,
603  MMCM_RESET => open,
604  QPLL_RESET => open,
605  CPLL_RESET => gt0_cpllreset_t,
606  TX_FSM_RESET_DONE => GT0_TX_FSM_RESET_DONE_OUT ,
607  TXUSERRDY => gt0_txuserrdy_t,
608  RUN_PHALIGNMENT => open,
609  RESET_PHALIGNMENT => open,
610  PHALIGNMENT_DONE => tied_to_vcc_i,
611  RETRY_COUNTER => open
612  );
613 
614 
615 
616 
617 
618 
619 gt0_rxresetfsm_i: uHTR_trig_RX_STARTUP_FSM
620 
621  generic map(
622  EXAMPLE_SIMULATION => EXAMPLE_SIMULATION,
623  GT_TYPE => "GTX", --GTX or GTH or GTP
624  EQ_MODE => "LPM", --Rx Equalization Mode - Set to DFE or LPM
625  STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, --Period of the stable clock driving this state-machine, unit is [ns]
626  RETRY_COUNTER_BITWIDTH => 8,
627  TX_QPLL_USED => FALSE , -- the TX and RX Reset FSMs must
628  RX_QPLL_USED => FALSE, -- share these two generic values
629  PHASE_ALIGNMENT_MANUAL => FALSE -- Decision if a manual phase-alignment is necessary or the automatic
630  -- is enough. For single-lane applications the automatic alignment is
631  -- sufficient
632  )
633  port map (
634  STABLE_CLOCK => SYSCLK_IN,
635  RXUSERCLK => GT0_RXUSRCLK_IN,
636  SOFT_RESET => SOFT_RESET_IN,
637  DONT_RESET_ON_DATA_ERROR => DONT_RESET_ON_DATA_ERROR_IN,
638  QPLLREFCLKLOST => tied_to_ground_i,
639  CPLLREFCLKLOST => gt0_cpllrefclklost_i ,
640  QPLLLOCK => tied_to_vcc_i,
641  CPLLLOCK => gt0_cplllock_i,
642  RXRESETDONE => gt0_rxresetdone_i,
643  MMCM_LOCK => tied_to_vcc_i,
644  RECCLK_STABLE => gt0_recclk_stable_i ,
645  RECCLK_MONITOR_RESTART => tied_to_ground_i,
646  DATA_VALID => GT0_DATA_VALID_IN,
647  TXUSERRDY => gt0_txuserrdy_i,
648  GTRXRESET => gt0_gtrxreset_t,
649  MMCM_RESET => open,
650  QPLL_RESET => open,
651  CPLL_RESET => open,
652  RX_FSM_RESET_DONE => GT0_RX_FSM_RESET_DONE_OUT ,
653  RXUSERRDY => gt0_rxuserrdy_t,
654  RUN_PHALIGNMENT => open,
655  RESET_PHALIGNMENT => open,
656  PHALIGNMENT_DONE => tied_to_vcc_i,
657  RXDFEAGCHOLD => gt0_rxdfeagchold_i ,
658  RXDFELFHOLD => gt0_rxdfelfhold_i,
659  RXLPMLFHOLD => gt0_rxlpmlfhold_i,
660  RXLPMHFHOLD => gt0_rxlpmhfhold_i,
661  RETRY_COUNTER => open
662  );
663 
664 
665 
666  cdrlock_timeout:process(SYSCLK_IN)
667  begin
668  if rising_edge(SYSCLK_IN) then
669  if(gt0_gtrxreset_i = '1') then
670  rx_cdrlocked <= '0';
671  rx_cdrlock_counter <= 0 after DLY;
672  elsif (rx_cdrlock_counter = WAIT_TIME_CDRLOCK) then
673  rx_cdrlocked <= '1';
674  rx_cdrlock_counter <= rx_cdrlock_counter after DLY;
675  else
676  rx_cdrlock_counter <= rx_cdrlock_counter + 1 after DLY;
677  end if;
678  end if;
679  end process;
680 
681 gt0_recclk_stable_i <= rx_cdrlocked;
682 
683 
684 
685 
686 
687 
688 
689 end RTL;
690 
691 
Generated on Wed Apr 18 2018 10:55:28 for AMC13 by   doxygen 1.8.1