AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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sysmon_if.vhd
1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 10:32:29 01/28/2012
6 -- Design Name:
7 -- Module Name: sysmon_if - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 library IEEE;
21 use IEEE.STD_LOGIC_1164.ALL;
22 use work.amc13_pack.all;
23 
24 -- Uncomment the following library declaration if using
25 -- arithmetic functions with Signed or Unsigned values
26 --use IEEE.NUMERIC_STD.ALL;
27 
28 -- Uncomment the following library declaration if instantiating
29 -- any Xilinx primitives in this code.
30 library UNISIM;
31 use UNISIM.VComponents.all;
32 
33 entity sysmon_if is
34  Port ( DRPclk : in STD_LOGIC; -- 50MHz
35  DB_cmd : in STD_LOGIC;
36  SN : in STD_LOGIC_VECTOR (8 downto 0);
37  VAUXN_IN : in STD_LOGIC_VECTOR (12 downto 0);
38  VAUXP_IN : in STD_LOGIC_VECTOR (12 downto 0);
39  addr : in STD_LOGIC_VECTOR (15 downto 0);
40  data : out STD_LOGIC_VECTOR (31 downto 0);
41  device_temp : out STD_LOGIC_VECTOR (11 downto 0);
42  ALM : out STD_LOGIC_VECTOR (7 downto 0);
43  OT : out std_logic);
44 end sysmon_if;
45 
46 architecture Behavioral of sysmon_if is
47 constant C : std_logic_vector(47 downto 0) := x"FFFFFF554800";
48 signal VAUXN : std_logic_vector(15 downto 0) := (others => '0');
49 signal VAUXP : std_logic_vector(15 downto 0) := (others => '0');
50 signal DADDR : std_logic_vector(6 downto 0) := (others => '0');
51 signal DO : std_logic_vector(15 downto 0) := (others => '0');
52 signal DRDY : std_logic := '0';
53 signal we_RAM : std_logic := '0';
54 signal DB_cmd_l : std_logic := '0';
55 signal re_ram : std_logic := '0';
56 signal EOC : std_logic := '0';
57 signal ram_wa : std_logic_vector(4 downto 0) := (others => '0');
58 signal RSTP : std_logic := '0';
59 signal OPMODE : std_logic_vector(6 downto 0) := (others => '0');
60 signal A : std_logic_vector(29 downto 0) := (others => '0');
61 signal B : std_logic_vector(17 downto 0) := (others => '0');
62 signal P : std_logic_vector(47 downto 0) := (others => '0');
63 begin
64 g_ram: for i in 0 to 13 generate
65  i_ram : RAM64X1D_1
66  generic map (
67  INIT => X"0000000000000000") -- Initial contents of RAM
68  port map (
69  DPO => data(i), -- Read-only 1-bit data output
70  SPO => open, -- R/W 1-bit data output
71  A0 => ram_wa(0), -- R/W address[0] input bit
72  A1 => ram_wa(1), -- R/W address[1] input bit
73  A2 => ram_wa(2), -- R/W address[2] input bit
74  A3 => ram_wa(3), -- R/W address[3] input bit
75  A4 => ram_wa(4), -- R/W address[4] input bit
76  A5 => '1', -- R/W address[5] input bit
77  D => P(i+12), -- Write 1-bit data input
78  DPRA0 => addr(0), -- Read-only address[0] input bit
79  DPRA1 => addr(1), -- Read-only address[1] input bit
80  DPRA2 => addr(2), -- Read-only address[2] input bit
81  DPRA3 => addr(3), -- Read-only address[3] input bit
82  DPRA4 => addr(15), -- Read-only address[4] input bit
83  DPRA5 => re_ram, -- Read-only address[5] input bit
84  WCLK => DRPclk, -- Write clock input
85  WE => we_ram -- Write enable input
86  );
87 end generate;
88 re_ram <= '1' when addr(14 downto 4) = sysmon_addr(14 downto 4) else '0';
89 data(31 downto 14) <= (others => '0');
90 I_DSP48E1 : DSP48E1
91  generic map (
92  -- Feature Control Attributes: Data Path Selection
93  A_INPUT => "DIRECT", -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port)
94  B_INPUT => "DIRECT", -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port)
95  USE_DPORT => FALSE, -- Select D port usage (TRUE or FALSE)
96  USE_MULT => "MULTIPLY", -- Select multiplier usage ("MULTIPLY", "DYNAMIC", or "NONE")
97  -- Pattern Detector Attributes: Pattern Detection Configuration
98  AUTORESET_PATDET => "NO_RESET", -- "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH"
99  MASK => X"3fffffffffff", -- 48-bit mask value for pattern detect (1=ignore)
100  PATTERN => X"000000000000", -- 48-bit pattern match for pattern detect
101  SEL_MASK => "MASK", -- "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2"
102  SEL_PATTERN => "PATTERN", -- Select pattern value ("PATTERN" or "C")
103  USE_PATTERN_DETECT => "NO_PATDET", -- Enable pattern detect ("PATDET" or "NO_PATDET")
104  -- Register Control Attributes: Pipeline Register Configuration
105  ACASCREG => 1, -- Number of pipeline stages between A/ACIN and ACOUT (0, 1 or 2)
106  ADREG => 1, -- Number of pipeline stages for pre-adder (0 or 1)
107  ALUMODEREG => 0, -- Number of pipeline stages for ALUMODE (0 or 1)
108  AREG => 1, -- Number of pipeline stages for A (0, 1 or 2)
109  BCASCREG => 1, -- Number of pipeline stages between B/BCIN and BCOUT (0, 1 or 2)
110  BREG => 1, -- Number of pipeline stages for B (0, 1 or 2)
111  CARRYINREG => 1, -- Number of pipeline stages for CARRYIN (0 or 1)
112  CARRYINSELREG => 1, -- Number of pipeline stages for CARRYINSEL (0 or 1)
113  CREG => 1, -- Number of pipeline stages for C (0 or 1)
114  DREG => 1, -- Number of pipeline stages for D (0 or 1)
115  INMODEREG => 1, -- Number of pipeline stages for INMODE (0 or 1)
116  MREG => 1, -- Number of multiplier pipeline stages (0 or 1)
117  OPMODEREG => 1, -- Number of pipeline stages for OPMODE (0 or 1)
118  PREG => 1, -- Number of pipeline stages for P (0 or 1)
119  USE_SIMD => "ONE48" -- SIMD selection ("ONE48", "TWO24", "FOUR12")
120  )
121  port map (
122  -- Cascade: 30-bit (each) output: Cascade Ports
123  ACOUT => open, -- 30-bit output: A port cascade output
124  BCOUT => open, -- 18-bit output: B port cascade output
125  CARRYCASCOUT => open, -- 1-bit output: Cascade carry output
126  MULTSIGNOUT => open, -- 1-bit output: Multiplier sign cascade output
127  PCOUT => open, -- 48-bit output: Cascade output
128  -- Control: 1-bit (each) output: Control Inputs/Status Bits
129  OVERFLOW => open, -- 1-bit output: Overflow in add/acc output
130  PATTERNBDETECT => open, -- 1-bit output: Pattern bar detect output
131  PATTERNDETECT => open, -- 1-bit output: Pattern detect output
132  UNDERFLOW => open, -- 1-bit output: Underflow in add/acc output
133  -- Data: 4-bit (each) output: Data Ports
134  CARRYOUT => open, -- 4-bit output: Carry output
135  P => P, -- 48-bit output: Primary data output
136  -- Cascade: 30-bit (each) input: Cascade Ports
137  ACIN => (others => '0'), -- 30-bit input: A cascade data input
138  BCIN => (others => '0'), -- 18-bit input: B cascade input
139  CARRYCASCIN => '0', -- 1-bit input: Cascade carry input
140  MULTSIGNIN => '0', -- 1-bit input: Multiplier sign input
141  PCIN => (others => '0'), -- 48-bit input: P cascade input
142  -- Control: 4-bit (each) input: Control Inputs/Status Bits
143  ALUMODE => x"0", -- 4-bit input: ALU control input
144  CARRYINSEL => "000", -- 3-bit input: Carry select input
145  CEINMODE => '1', -- 1-bit input: Clock enable input for INMODEREG
146  CLK => DRPclk, -- 1-bit input: Clock input
147  INMODE => "10001", -- 5-bit input: INMODE control input
148  OPMODE => OPMODE , -- 7-bit input: Operation mode input
149  RSTINMODE => '0', -- 1-bit input: Reset input for INMODEREG
150  -- Data: 30-bit (each) input: Data Ports
151  A => A, -- 30-bit input: A data input
152  B => B, -- 18-bit input: B data input
153  C => C, -- 48-bit input: C data input
154  CARRYIN => '0', -- 1-bit input: Carry input signal
155  D => (others => '0'), -- 25-bit input: D data input
156  -- Reset/Clock Enable: 1-bit (each) input: Reset/Clock Enable Inputs
157  CEA1 => '1', -- 1-bit input: Clock enable input for 1st stage AREG
158  CEA2 =>'1', -- 1-bit input: Clock enable input for 2nd stage AREG
159  CEAD => '1', -- 1-bit input: Clock enable input for ADREG
160  CEALUMODE => '1', -- 1-bit input: Clock enable input for ALUMODERE
161  CEB1 => '1', -- 1-bit input: Clock enable input for 1st stage BREG
162  CEB2 => '1', -- 1-bit input: Clock enable input for 2nd stage BREG
163  CEC => '1', -- 1-bit input: Clock enable input for CREG
164  CECARRYIN => '1', -- 1-bit input: Clock enable input for CARRYINREG
165  CECTRL => '1', -- 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
166  CED => '1', -- 1-bit input: Clock enable input for DREG
167  CEM => '1', -- 1-bit input: Clock enable input for MREG
168  CEP => '1', -- 1-bit input: Clock enable input for PREG
169  RSTA => '0', -- 1-bit input: Reset input for AREG
170  RSTALLCARRYIN => '0', -- 1-bit input: Reset input for CARRYINREG
171  RSTALUMODE => '0', -- 1-bit input: Reset input for ALUMODEREG
172  RSTB => '0', -- 1-bit input: Reset input for BREG
173  RSTC => '0', -- 1-bit input: Reset input for CREG
174  RSTCTRL => '0', -- 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
175  RSTD => '0', -- 1-bit input: Reset input for DREG and ADREG
176  RSTM => '0', -- 1-bit input: Reset input for MREG
177  RSTP => RSTP -- 1-bit input: Reset input for PREG
178  );
179 RSTP <= '1' when SN(8 downto 4) = "11111" and DADDR(4) = '1' else '0';
180 OPMODE <= "0110101" when DADDR(4 downto 0) = "00000" else "0000101";
181 A(29 downto 12) <= (others => '0');
182 A(11 downto 0) <= DO(15 downto 4);
183 B(17 downto 16) <= (others => '0');
184 i_we_ram : SRL16E
185  generic map (
186  INIT => X"0000")
187  port map (
188  Q => we_ram, -- SRL data output
189  A0 => '0', -- Select[0] input
190  A1 => '1', -- Select[1] input
191  A2 => '0', -- Select[2] input
192  A3 => '0', -- Select[3] input
193  CE => '1', -- Clock enable input
194  CLK => DRPclk, -- Clock input
195  D => DRDY -- SRL data input
196  );
197 process(DRPclk)
198 begin
199  if(DRPclk'event and DRPclk = '1')then
200  if(DADDR(4 downto 0) = "00000" and DRDY = '1')then
201  device_temp <= DO(15 downto 4);
202  end if;
203  if(DB_cmd = '1')then
204  DB_cmd_l <= '1';
205  elsif(we_ram = '1' and DADDR(4 downto 0) = "11100")then
206  DB_cmd_l <= '0';
207  end if;
208  if(we_ram = '1' and DADDR(4 downto 0) = "11100")then
209  ram_wa(4) <= DB_cmd_l;
210  end if;
211  end if;
212 end process;
213 process(DADDR)
214 begin
215  case DADDR(4 downto 0) is
216  when "00000" => ram_wa(3 downto 0) <= x"0"; -- temperature
217  when "00001" => ram_wa(3 downto 0) <= x"3"; -- 1V0 Vccint
218  when "00010" => ram_wa(3 downto 0) <= x"d"; -- 1V8 VccAux
219  when "00110" => ram_wa(3 downto 0) <= x"e"; -- 1V0 VccBRAM
220  when "10000" => ram_wa(3 downto 0) <= x"4"; -- 1V5
221  when "10010" => ram_wa(3 downto 0) <= x"2"; -- 1V2A
222  when "10011" => ram_wa(3 downto 0) <= x"b"; -- DDR3_VTT
223  when "10100" => ram_wa(3 downto 0) <= x"8"; -- 12V
224  when "10101" => ram_wa(3 downto 0) <= x"9"; -- 1V8A VccAuxGTX
225  when "11000" => ram_wa(3 downto 0) <= x"a"; -- 2V0 VccAuxIO
226  when "11001" => ram_wa(3 downto 0) <= x"1"; -- 1V0A
227  when "11010" => ram_wa(3 downto 0) <= x"6"; -- 3V3
228  when "11011" => ram_wa(3 downto 0) <= x"5"; -- 2V5
229  when "11100" => ram_wa(3 downto 0) <= x"c"; -- DDR3_VREF
230  when others => ram_wa(3 downto 0) <= x"f";
231  end case;
232 end process;
233 process(DADDR)
234 begin
235  case DADDR(4 downto 0) is
236  when "00000" => B(15 downto 0) <= x"13B0";
237  when "00001" | "00010" | "00110" => B(15 downto 0) <= x"0BB8";
238  when "10000" => B(15 downto 0) <= x"0654";
239  when "10010" => B(15 downto 0) <= x"0514";
240  when "10011" => B(15 downto 0) <= x"03E8";
241  when "10100" => B(15 downto 0) <= x"411A";
242  when "10101" => B(15 downto 0) <= x"07D0";
243  when "11000" => B(15 downto 0) <= x"0852";
244  when "11001" => B(15 downto 0) <= x"044C";
245  when "11010" => B(15 downto 0) <= x"0DDE";
246  when "11011" => B(15 downto 0) <= x"0A28";
247  when "11100" => B(15 downto 0) <= x"03E8";
248  when others => B(15 downto 0) <= x"0000";
249  end case;
250 end process;
251 I_XADC : XADC
252  generic map (
253  -- INIT_40 - INIT_42: XADC configuration registers
254  INIT_40 => X"0000",
255  INIT_41 => X"2ef0",
256  INIT_42 => X"0400",
257  -- INIT_48 - INIT_4F: Sequence Registers
258  INIT_48 => X"4701",
259  INIT_49 => X"1f3d",
260  INIT_4A => X"0000",
261  INIT_4B => X"0000",
262  INIT_4C => X"0000",
263  INIT_4D => X"0000",
264  INIT_4F => X"0000",
265  INIT_4E => X"0000", -- Sequence register 6
266  -- INIT_50 - INIT_58, INIT5C: Alarm Limit Registers
267  INIT_50 => X"b5ed",
268  INIT_51 => X"5999",
269  INIT_52 => X"a147",
270  INIT_53 => X"dddd",
271  INIT_54 => X"767a",
272  INIT_55 => X"5111",
273  INIT_56 => X"91eb",
274  INIT_57 => X"ae4e",
275  INIT_58 => X"5999",
276  INIT_5C => X"5111",
277  -- Simulation attributes: Set for proepr simulation behavior
278  SIM_DEVICE => "7SERIES", -- Select target device (values)
279  SIM_MONITOR_FILE => "design.txt" -- Analog simulation data file name
280  )
281  port map (
282  -- ALARMS: 8-bit (each) output: ALM, OT
283  ALM => ALM, -- 8-bit output: Output alarm for temp, Vccint, Vccaux and Vccbram
284  OT => OT, -- 1-bit output: Over-Temperature alarm
285  -- Dynamic Reconfiguration Port (DRP): 16-bit (each) output: Dynamic Reconfiguration Ports
286  DO => DO, -- 16-bit output: DRP output data bus
287  DRDY => DRDY, -- 1-bit output: DRP data ready
288  -- STATUS: 1-bit (each) output: XADC status ports
289  BUSY => open, -- 1-bit output: ADC busy output
290  CHANNEL => DADDR(4 downto 0), -- 5-bit output: Channel selection outputs
291  EOC => EOC, -- 1-bit output: End of Conversion
292  EOS => open, -- 1-bit output: End of Sequence
293  JTAGBUSY => open, -- 1-bit output: JTAG DRP transaction in progress output
294  JTAGLOCKED => open, -- 1-bit output: JTAG requested DRP port lock
295  JTAGMODIFIED => open, -- 1-bit output: JTAG Write to the DRP has occurred
296  MUXADDR => open, -- 5-bit output: External MUX channel decode
297  -- Auxiliary Analog-Input Pairs: 16-bit (each) input: VAUXP[15:0], VAUXN[15:0]
298  VAUXN => VAUXN, -- 16-bit input: N-side auxiliary analog input
299  VAUXP => VAUXP, -- 16-bit input: P-side auxiliary analog input
300  -- CONTROL and CLOCK: 1-bit (each) input: Reset, conversion start and clock inputs
301  CONVST => '0', -- 1-bit input: Convert start input
302  CONVSTCLK => '0', -- 1-bit input: Convert start input
303  RESET => '0', -- 1-bit input: Active-high reset
304  -- Dedicated Analog Input Pair: 1-bit (each) input: VP/VN
305  VN => '0', -- 1-bit input: N-side analog input
306  VP => '0', -- 1-bit input: P-side analog input
307  -- Dynamic Reconfiguration Port (DRP): 7-bit (each) input: Dynamic Reconfiguration Ports
308  DADDR => DADDR, -- 7-bit input: DRP address bus
309  DCLK => DRPclk, -- 1-bit input: DRP clock
310  DEN => EOC, -- 1-bit input: DRP enable signal
311  DI => x"0000", -- 16-bit input: DRP input data bus
312  DWE => '0' -- 1-bit input: DRP write enable
313  );
314 DADDR(6 downto 5) <= "00";
315 VAUXN <= "000" & VAUXN_IN(12 downto 8) & "00" & VAUXN_IN(5 downto 2) & '0' & VAUXN_IN(0);
316 VAUXP <= "000" & VAUXP_IN(12 downto 8) & "00" & VAUXP_IN(5 downto 2) & '0' & VAUXP_IN(0);
317 end Behavioral;
318 
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