AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
 All Classes Variables
serdes5gpdprod_gt.vhd
1 -------------------------------------------------------------------------------
2 -- ____ ____
3 -- / /\/ /
4 -- /___/ \ / Vendor: Xilinx
5 -- \ \ \/ Version : 2.7
6 -- \ \ Application : 7 Series FPGAs Transceivers Wizard
7 -- / / Filename : serdes5gpdprod_gt.vhd
8 -- /___/ /\
9 -- \ \ / \
10 -- \___\/\___\
11 --
12 --
13 -- Module serdes5GpdProd_GT (a GT Wrapper)
14 -- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
15 --
16 --
17 -- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
18 --
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62 
63 
64 library ieee;
65 use ieee.std_logic_1164.all;
66 use ieee.numeric_std.all;
67 library UNISIM;
68 use UNISIM.VCOMPONENTS.ALL;
69 
70 --***************************** Entity Declaration ****************************
71 
72 entity serdes5GpdProd_GT is
73 generic
74 (
75  -- Simulation attributes
76  GT_SIM_GTRESET_SPEEDUP : string := "FALSE"; -- Set to "true" to speed up sim reset
77  RX_DFE_KL_CFG2_IN : bit_vector := X"301148AC";
78  PMA_RSV_IN : bit_vector := x"001E7080";
79  PCS_RSVD_ATTR_IN : bit_vector := X"000000000000"
80 );
81 port
82 (
83  ---------------------------- Channel - DRP Ports --------------------------
84  DRPADDR_IN : in std_logic_vector(8 downto 0);
85  DRPCLK_IN : in std_logic;
86  DRPDI_IN : in std_logic_vector(15 downto 0);
87  DRPDO_OUT : out std_logic_vector(15 downto 0);
88  DRPEN_IN : in std_logic;
89  DRPRDY_OUT : out std_logic;
90  DRPWE_IN : in std_logic;
91  ------------------------------- Clocking Ports -----------------------------
92  QPLLCLK_IN : in std_logic;
93  QPLLREFCLK_IN : in std_logic;
94  ------------------------------ Power-Down Ports ----------------------------
95  RXPD_IN : in std_logic_vector(1 downto 0);
96  TXPD_IN : in std_logic_vector(1 downto 0);
97  --------------------- RX Initialization and Reset Ports --------------------
98  RXUSERRDY_IN : in std_logic;
99  -------------------------- RX Margin Analysis Ports ------------------------
100  EYESCANDATAERROR_OUT : out std_logic;
101  ------------------------- Receive Ports - CDR Ports ------------------------
102  RXCDRLOCK_OUT : out std_logic;
103  ------------------- Receive Ports - Clock Correction Ports -----------------
104  RXCLKCORCNT_OUT : out std_logic_vector(1 downto 0);
105  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
106  RXUSRCLK_IN : in std_logic;
107  RXUSRCLK2_IN : in std_logic;
108  ------------------ Receive Ports - FPGA RX interface Ports -----------------
109  RXDATA_OUT : out std_logic_vector(31 downto 0);
110  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
111  RXDISPERR_OUT : out std_logic_vector(3 downto 0);
112  RXNOTINTABLE_OUT : out std_logic_vector(3 downto 0);
113  --------------------------- Receive Ports - RX AFE -------------------------
114  GTXRXP_IN : in std_logic;
115  ------------------------ Receive Ports - RX AFE Ports ----------------------
116  GTXRXN_IN : in std_logic;
117  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
118  RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
119  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
120  RXBYTEISALIGNED_OUT : out std_logic;
121  RXBYTEREALIGN_OUT : out std_logic;
122  RXCOMMADET_OUT : out std_logic;
123  RXMCOMMAALIGNEN_IN : in std_logic;
124  RXPCOMMAALIGNEN_IN : in std_logic;
125  --------------------- Receive Ports - RX Equalizer Ports -------------------
126  RXDFEAGCHOLD_IN : in std_logic;
127  RXDFELFHOLD_IN : in std_logic;
128  --------------- Receive Ports - RX Fabric Output Control Ports -------------
129  RXOUTCLK_OUT : out std_logic;
130  ------------- Receive Ports - RX Initialization and Reset Ports ------------
131  GTRXRESET_IN : in std_logic;
132  RXPMARESET_IN : in std_logic;
133  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
134  RXCHARISCOMMA_OUT : out std_logic_vector(3 downto 0);
135  RXCHARISK_OUT : out std_logic_vector(3 downto 0);
136  -------------- Receive Ports -RX Initialization and Reset Ports ------------
137  RXRESETDONE_OUT : out std_logic;
138  --------------------- TX Initialization and Reset Ports --------------------
139  GTTXRESET_IN : in std_logic;
140  TXUSERRDY_IN : in std_logic;
141  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
142  TXUSRCLK_IN : in std_logic;
143  TXUSRCLK2_IN : in std_logic;
144  ------------------ Transmit Ports - TX Data Path interface -----------------
145  TXDATA_IN : in std_logic_vector(31 downto 0);
146  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
147  GTXTXN_OUT : out std_logic;
148  GTXTXP_OUT : out std_logic;
149  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
150  TXOUTCLK_OUT : out std_logic;
151  TXOUTCLKFABRIC_OUT : out std_logic;
152  TXOUTCLKPCS_OUT : out std_logic;
153  --------------------- Transmit Ports - TX Gearbox Ports --------------------
154  TXCHARISK_IN : in std_logic_vector(3 downto 0);
155  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
156  TXRESETDONE_OUT : out std_logic
157 
158 
159 );
160 
161 
162 end serdes5GpdProd_GT;
163 
164 architecture RTL of serdes5GpdProd_GT is
165 
166 --**************************** Signal Declarations ****************************
167 
168  -- ground and tied_to_vcc_i signals
169  signal tied_to_ground_i : std_logic;
170  signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
171  signal tied_to_vcc_i : std_logic;
172 
173 
174 
175  -- RX Datapath signals
176  signal rxdata_i : std_logic_vector(63 downto 0);
177  signal rxchariscomma_float_i : std_logic_vector(3 downto 0);
178  signal rxcharisk_float_i : std_logic_vector(3 downto 0);
179  signal rxdisperr_float_i : std_logic_vector(3 downto 0);
180  signal rxnotintable_float_i : std_logic_vector(3 downto 0);
181  signal rxrundisp_float_i : std_logic_vector(3 downto 0);
182 
183 
184 
185  -- TX Datapath signals
186  signal txdata_i : std_logic_vector(63 downto 0);
187  signal txkerr_float_i : std_logic_vector(3 downto 0);
188  signal txrundisp_float_i : std_logic_vector(3 downto 0);
189  signal rxstartofseq_float_i : std_logic;
190 
191 --******************************** Main Body of Code***************************
192 
193 begin
194 
195  --------------------------- Static signal Assignments ---------------------
196 
197  tied_to_ground_i <= '0';
198  tied_to_ground_vec_i(63 downto 0) <= (others => '0');
199  tied_to_vcc_i <= '1';
200 
201  ------------------- GT Datapath byte mapping -----------------
202 
203  -- The GT provides little endian data (first byte received on RXDATA(7 downto 0))
204  RXDATA_OUT <= rxdata_i(31 downto 0);
205 
206  txdata_i <= (tied_to_ground_vec_i(31 downto 0) & TXDATA_IN);
207 
208 
209 
210  ----------------------------- GTXE2 Instance --------------------------
211 
212  gtxe2_i :GTXE2_CHANNEL
213  generic map
214  (
215 
216  --_______________________ Simulation-Only Attributes ___________________
217 
218  SIM_RECEIVER_DETECT_PASS => ("TRUE"),
219  SIM_RESET_SPEEDUP => (GT_SIM_GTRESET_SPEEDUP),
220  SIM_TX_EIDLE_DRIVE_LEVEL => ("X"),
221  SIM_CPLLREFCLK_SEL => ("001"),
222  SIM_VERSION => ("4.0"),
223 
224 
225  ------------------RX Byte and Word Alignment Attributes---------------
226  ALIGN_COMMA_DOUBLE => ("FALSE"),
227  ALIGN_COMMA_ENABLE => ("1111111111"),
228  ALIGN_COMMA_WORD => (2),
229  ALIGN_MCOMMA_DET => ("TRUE"),
230  ALIGN_MCOMMA_VALUE => ("1010000011"),
231  ALIGN_PCOMMA_DET => ("TRUE"),
232  ALIGN_PCOMMA_VALUE => ("0101111100"),
233  SHOW_REALIGN_COMMA => ("TRUE"),
234  RXSLIDE_AUTO_WAIT => (7),
235  RXSLIDE_MODE => ("OFF"),
236  RX_SIG_VALID_DLY => (10),
237 
238  ------------------RX 8B/10B Decoder Attributes---------------
239  RX_DISPERR_SEQ_MATCH => ("TRUE"),
240  DEC_MCOMMA_DETECT => ("TRUE"),
241  DEC_PCOMMA_DETECT => ("TRUE"),
242  DEC_VALID_COMMA_ONLY => ("FALSE"),
243 
244  ------------------------RX Clock Correction Attributes----------------------
245  CBCC_DATA_SOURCE_SEL => ("DECODED"),
246  CLK_COR_SEQ_2_USE => ("FALSE"),
247  CLK_COR_KEEP_IDLE => ("FALSE"),
248  CLK_COR_MAX_LAT => (51),
249  CLK_COR_MIN_LAT => (44),
250  CLK_COR_PRECEDENCE => ("TRUE"),
251  CLK_COR_REPEAT_WAIT => (0),
252  CLK_COR_SEQ_LEN => (4),
253  CLK_COR_SEQ_1_ENABLE => ("1111"),
254  CLK_COR_SEQ_1_1 => ("0100011100"),
255  CLK_COR_SEQ_1_2 => ("0111011100"),
256  CLK_COR_SEQ_1_3 => ("0110111100"),
257  CLK_COR_SEQ_1_4 => ("0101111100"),
258  CLK_CORRECT_USE => ("TRUE"),
259  CLK_COR_SEQ_2_ENABLE => ("1111"),
260  CLK_COR_SEQ_2_1 => ("0000000000"),
261  CLK_COR_SEQ_2_2 => ("0000000000"),
262  CLK_COR_SEQ_2_3 => ("0000000000"),
263  CLK_COR_SEQ_2_4 => ("0000000000"),
264 
265  ------------------------RX Channel Bonding Attributes----------------------
266  CHAN_BOND_KEEP_ALIGN => ("FALSE"),
267  CHAN_BOND_MAX_SKEW => (1),
268  CHAN_BOND_SEQ_LEN => (1),
269  CHAN_BOND_SEQ_1_1 => ("0000000000"),
270  CHAN_BOND_SEQ_1_2 => ("0000000000"),
271  CHAN_BOND_SEQ_1_3 => ("0000000000"),
272  CHAN_BOND_SEQ_1_4 => ("0000000000"),
273  CHAN_BOND_SEQ_1_ENABLE => ("1111"),
274  CHAN_BOND_SEQ_2_1 => ("0000000000"),
275  CHAN_BOND_SEQ_2_2 => ("0000000000"),
276  CHAN_BOND_SEQ_2_3 => ("0000000000"),
277  CHAN_BOND_SEQ_2_4 => ("0000000000"),
278  CHAN_BOND_SEQ_2_ENABLE => ("1111"),
279  CHAN_BOND_SEQ_2_USE => ("FALSE"),
280  FTS_DESKEW_SEQ_ENABLE => ("1111"),
281  FTS_LANE_DESKEW_CFG => ("1111"),
282  FTS_LANE_DESKEW_EN => ("FALSE"),
283 
284  ---------------------------RX Margin Analysis Attributes----------------------------
285  ES_CONTROL => ("000000"),
286  ES_ERRDET_EN => ("FALSE"),
287  ES_EYE_SCAN_EN => ("TRUE"),
288  ES_HORZ_OFFSET => (x"000"),
289  ES_PMA_CFG => ("0000000000"),
290  ES_PRESCALE => ("00000"),
291  ES_QUALIFIER => (x"00000000000000000000"),
292  ES_QUAL_MASK => (x"00000000000000000000"),
293  ES_SDATA_MASK => (x"00000000000000000000"),
294  ES_VERT_OFFSET => ("000000000"),
295 
296  -------------------------FPGA RX Interface Attributes-------------------------
297  RX_DATA_WIDTH => (40),
298 
299  ---------------------------PMA Attributes----------------------------
300  OUTREFCLK_SEL_INV => ("11"),
301  PMA_RSV => (PMA_RSV_IN),
302  PMA_RSV2 => (x"2050"),
303  PMA_RSV3 => ("00"),
304  PMA_RSV4 => (x"00000000"),
305  RX_BIAS_CFG => ("000000000100"),
306  DMONITOR_CFG => (x"000A00"),
307  RX_CM_SEL => ("11"),
308  RX_CM_TRIM => ("010"),
309  RX_DEBUG_CFG => ("000000000000"),
310  RX_OS_CFG => ("0000010000000"),
311  TERM_RCAL_CFG => ("10000"),
312  TERM_RCAL_OVRD => ('0'),
313  TST_RSV => (x"00000000"),
314  RX_CLK25_DIV => (5),
315  TX_CLK25_DIV => (5),
316  UCODEER_CLR => ('0'),
317 
318  ---------------------------PCI Express Attributes----------------------------
319  PCS_PCIE_EN => ("FALSE"),
320 
321  ---------------------------PCS Attributes----------------------------
322  PCS_RSVD_ATTR => (PCS_RSVD_ATTR_IN),
323 
324  -------------RX Buffer Attributes------------
325  RXBUF_ADDR_MODE => ("FULL"),
326  RXBUF_EIDLE_HI_CNT => ("1000"),
327  RXBUF_EIDLE_LO_CNT => ("0000"),
328  RXBUF_EN => ("TRUE"),
329  RX_BUFFER_CFG => ("000000"),
330  RXBUF_RESET_ON_CB_CHANGE => ("TRUE"),
331  RXBUF_RESET_ON_COMMAALIGN => ("FALSE"),
332  RXBUF_RESET_ON_EIDLE => ("FALSE"),
333  RXBUF_RESET_ON_RATE_CHANGE => ("TRUE"),
334  RXBUFRESET_TIME => ("00001"),
335  RXBUF_THRESH_OVFLW => (61),
336  RXBUF_THRESH_OVRD => ("FALSE"),
337  RXBUF_THRESH_UNDFLW => (4),
338  RXDLY_CFG => (x"001F"),
339  RXDLY_LCFG => (x"030"),
340  RXDLY_TAP_CFG => (x"0000"),
341  RXPH_CFG => (x"000000"),
342  RXPHDLY_CFG => (x"084020"),
343  RXPH_MONITOR_SEL => ("00000"),
344  RX_XCLK_SEL => ("RXREC"),
345  RX_DDI_SEL => ("000000"),
346  RX_DEFER_RESET_BUF_EN => ("TRUE"),
347 
348  -----------------------CDR Attributes-------------------------
349 
350  --For GTX only: Display Port, HBR/RBR- set RXCDR_CFG=72'h0380008bff40200008
351 
352  --For GTX only: Display Port, HBR2 - set RXCDR_CFG=72'h038C008bff20200010
353  RXCDR_CFG => (x"03800023ff40200020"),
354  RXCDR_FR_RESET_ON_EIDLE => ('0'),
355  RXCDR_HOLD_DURING_EIDLE => ('0'),
356  RXCDR_PH_RESET_ON_EIDLE => ('0'),
357  RXCDR_LOCK_CFG => ("010101"),
358 
359  -------------------RX Initialization and Reset Attributes-------------------
360  RXCDRFREQRESET_TIME => ("00001"),
361  RXCDRPHRESET_TIME => ("00001"),
362  RXISCANRESET_TIME => ("00001"),
363  RXPCSRESET_TIME => ("00001"),
364  RXPMARESET_TIME => ("00011"),
365 
366  -------------------RX OOB Signaling Attributes-------------------
367  RXOOB_CFG => ("0000110"),
368 
369  -------------------------RX Gearbox Attributes---------------------------
370  RXGEARBOX_EN => ("FALSE"),
371  GEARBOX_MODE => ("000"),
372 
373  -------------------------PRBS Detection Attribute-----------------------
374  RXPRBS_ERR_LOOPBACK => ('0'),
375 
376  -------------Power-Down Attributes----------
377  PD_TRANS_TIME_FROM_P2 => (x"03c"),
378  PD_TRANS_TIME_NONE_P2 => (x"19"),
379  PD_TRANS_TIME_TO_P2 => (x"64"),
380 
381  -------------RX OOB Signaling Attributes----------
382  SAS_MAX_COM => (64),
383  SAS_MIN_COM => (36),
384  SATA_BURST_SEQ_LEN => ("1111"),
385  SATA_BURST_VAL => ("100"),
386  SATA_EIDLE_VAL => ("100"),
387  SATA_MAX_BURST => (8),
388  SATA_MAX_INIT => (21),
389  SATA_MAX_WAKE => (7),
390  SATA_MIN_BURST => (4),
391  SATA_MIN_INIT => (12),
392  SATA_MIN_WAKE => (4),
393 
394  -------------RX Fabric Clock Output Control Attributes----------
395  TRANS_TIME_RATE => (x"0E"),
396 
397  --------------TX Buffer Attributes----------------
398  TXBUF_EN => ("TRUE"),
399  TXBUF_RESET_ON_RATE_CHANGE => ("TRUE"),
400  TXDLY_CFG => (x"001F"),
401  TXDLY_LCFG => (x"030"),
402  TXDLY_TAP_CFG => (x"0000"),
403  TXPH_CFG => (x"0780"),
404  TXPHDLY_CFG => (x"084020"),
405  TXPH_MONITOR_SEL => ("00000"),
406  TX_XCLK_SEL => ("TXOUT"),
407 
408  -------------------------FPGA TX Interface Attributes-------------------------
409  TX_DATA_WIDTH => (40),
410 
411  -------------------------TX Configurable Driver Attributes-------------------------
412  TX_DEEMPH0 => ("00000"),
413  TX_DEEMPH1 => ("00000"),
414  TX_EIDLE_ASSERT_DELAY => ("110"),
415  TX_EIDLE_DEASSERT_DELAY => ("100"),
416  TX_LOOPBACK_DRIVE_HIZ => ("FALSE"),
417  TX_MAINCURSOR_SEL => ('0'),
418  TX_DRIVE_MODE => ("DIRECT"),
419  TX_MARGIN_FULL_0 => ("1001110"),
420  TX_MARGIN_FULL_1 => ("1001001"),
421  TX_MARGIN_FULL_2 => ("1000101"),
422  TX_MARGIN_FULL_3 => ("1000010"),
423  TX_MARGIN_FULL_4 => ("1000000"),
424  TX_MARGIN_LOW_0 => ("1000110"),
425  TX_MARGIN_LOW_1 => ("1000100"),
426  TX_MARGIN_LOW_2 => ("1000010"),
427  TX_MARGIN_LOW_3 => ("1000000"),
428  TX_MARGIN_LOW_4 => ("1000000"),
429 
430  -------------------------TX Gearbox Attributes--------------------------
431  TXGEARBOX_EN => ("FALSE"),
432 
433  -------------------------TX Initialization and Reset Attributes--------------------------
434  TXPCSRESET_TIME => ("00001"),
435  TXPMARESET_TIME => ("00001"),
436 
437  -------------------------TX Receiver Detection Attributes--------------------------
438  TX_RXDETECT_CFG => (x"1832"),
439  TX_RXDETECT_REF => ("100"),
440 
441  ----------------------------CPLL Attributes----------------------------
442  CPLL_CFG => (x"BC07DC"),
443  CPLL_FBDIV => (4),
444  CPLL_FBDIV_45 => (5),
445  CPLL_INIT_CFG => (x"00001E"),
446  CPLL_LOCK_CFG => (x"01E8"),
447  CPLL_REFCLK_DIV => (1),
448  RXOUT_DIV => (2),
449  TXOUT_DIV => (2),
450  SATA_CPLL_CFG => ("VCO_3000MHZ"),
451 
452  --------------RX Initialization and Reset Attributes-------------
453  RXDFELPMRESET_TIME => ("0001111"),
454 
455  --------------RX Equalizer Attributes-------------
456  RXLPM_HF_CFG => ("00000011110000"),
457  RXLPM_LF_CFG => ("00000011110000"),
458  RX_DFE_GAIN_CFG => (x"020FEA"),
459  RX_DFE_H2_CFG => ("000000000000"),
460  RX_DFE_H3_CFG => ("000001000000"),
461  RX_DFE_H4_CFG => ("00011110000"),
462  RX_DFE_H5_CFG => ("00011100000"),
463  RX_DFE_KL_CFG => ("0000011111110"),
464  RX_DFE_LPM_CFG => (x"0954"),
465  RX_DFE_LPM_HOLD_DURING_EIDLE => ('0'),
466  RX_DFE_UT_CFG => ("10001111000000000"),
467  RX_DFE_VP_CFG => ("00011111100000011"),
468 
469  -------------------------Power-Down Attributes-------------------------
470  RX_CLKMUX_PD => ('1'),
471  TX_CLKMUX_PD => ('1'),
472 
473  -------------------------FPGA RX Interface Attribute-------------------------
474  RX_INT_DATAWIDTH => (1),
475 
476  -------------------------FPGA TX Interface Attribute-------------------------
477  TX_INT_DATAWIDTH => (1),
478 
479  ------------------TX Configurable Driver Attributes---------------
480  TX_QPI_STATUS_EN => ('0'),
481 
482  -------------------------RX Equalizer Attributes--------------------------
483  RX_DFE_KL_CFG2 => (RX_DFE_KL_CFG2_IN),
484  RX_DFE_XYD_CFG => ("0000000000000"),
485 
486  -------------------------TX Configurable Driver Attributes--------------------------
487  TX_PREDRIVER_MODE => ('0')
488 
489 
490  )
491  port map
492  (
493  --------------------------------- CPLL Ports -------------------------------
494  CPLLFBCLKLOST => open,
495  CPLLLOCK => open,
496  CPLLLOCKDETCLK => tied_to_ground_i,
497  CPLLLOCKEN => tied_to_vcc_i,
498  CPLLPD => tied_to_vcc_i,
499  CPLLREFCLKLOST => open,
500  CPLLREFCLKSEL => "001",
501  CPLLRESET => tied_to_ground_i,
502  GTRSVD => "0000000000000000",
503  PCSRSVDIN => "0000000000000000",
504  PCSRSVDIN2 => "00000",
505  PMARSVDIN => "00000",
506  PMARSVDIN2 => "00000",
507  TSTIN => "11111111111111111111" ,
508  TSTOUT => open,
509  ---------------------------------- Channel ---------------------------------
510  CLKRSVD => "0000",
511  -------------------------- Channel - Clocking Ports ------------------------
512  GTGREFCLK => tied_to_ground_i,
513  GTNORTHREFCLK0 => tied_to_ground_i,
514  GTNORTHREFCLK1 => tied_to_ground_i,
515  GTREFCLK0 => tied_to_ground_i,
516  GTREFCLK1 => tied_to_ground_i,
517  GTSOUTHREFCLK0 => tied_to_ground_i,
518  GTSOUTHREFCLK1 => tied_to_ground_i,
519  ---------------------------- Channel - DRP Ports --------------------------
520  DRPADDR => DRPADDR_IN,
521  DRPCLK => DRPCLK_IN ,
522  DRPDI => DRPDI_IN,
523  DRPDO => DRPDO_OUT ,
524  DRPEN => DRPEN_IN,
525  DRPRDY => DRPRDY_OUT,
526  DRPWE => DRPWE_IN,
527  ------------------------------- Clocking Ports -----------------------------
528  GTREFCLKMONITOR => open,
529  QPLLCLK => QPLLCLK_IN,
530  QPLLREFCLK => QPLLREFCLK_IN,
531  RXSYSCLKSEL => "11",
532  TXSYSCLKSEL => "11",
533  --------------------------- Digital Monitor Ports --------------------------
534  DMONITOROUT => open,
535  ----------------- FPGA TX Interface Datapath Configuration ----------------
536  TX8B10BEN => tied_to_vcc_i,
537  ------------------------------- Loopback Ports -----------------------------
538  LOOPBACK => tied_to_ground_vec_i (2 downto 0),
539  ----------------------------- PCI Express Ports ----------------------------
540  PHYSTATUS => open,
541  RXRATE => tied_to_ground_vec_i (2 downto 0),
542  RXVALID => open,
543  ------------------------------ Power-Down Ports ----------------------------
544  RXPD => RXPD_IN,
545  TXPD => TXPD_IN,
546  -------------------------- RX 8B/10B Decoder Ports -------------------------
547  SETERRSTATUS => tied_to_ground_i,
548  --------------------- RX Initialization and Reset Ports --------------------
549  EYESCANRESET => tied_to_ground_i,
550  RXUSERRDY => RXUSERRDY_IN,
551  -------------------------- RX Margin Analysis Ports ------------------------
552  EYESCANDATAERROR => EYESCANDATAERROR_OUT ,
553  EYESCANMODE => tied_to_ground_i,
554  EYESCANTRIGGER => tied_to_ground_i,
555  ------------------------- Receive Ports - CDR Ports ------------------------
556  RXCDRFREQRESET => tied_to_ground_i,
557  RXCDRHOLD => tied_to_ground_i,
558  RXCDRLOCK => RXCDRLOCK_OUT,
559  RXCDROVRDEN => tied_to_ground_i,
560  RXCDRRESET => tied_to_ground_i,
561  RXCDRRESETRSV => tied_to_ground_i,
562  ------------------- Receive Ports - Clock Correction Ports -----------------
563  RXCLKCORCNT => RXCLKCORCNT_OUT,
564  ---------- Receive Ports - FPGA RX Interface Datapath Configuration --------
565  RX8B10BEN => tied_to_vcc_i,
566  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
567  RXUSRCLK => RXUSRCLK_IN,
568  RXUSRCLK2 => RXUSRCLK2_IN,
569  ------------------ Receive Ports - FPGA RX interface Ports -----------------
570  RXDATA => rxdata_i,
571  ------------------- Receive Ports - Pattern Checker Ports ------------------
572  RXPRBSERR => open,
573  RXPRBSSEL => tied_to_ground_vec_i (2 downto 0),
574  ------------------- Receive Ports - Pattern Checker ports ------------------
575  RXPRBSCNTRESET => tied_to_ground_i,
576  -------------------- Receive Ports - RX Equalizer Ports -------------------
577  RXDFEXYDEN => tied_to_vcc_i,
578  RXDFEXYDHOLD => tied_to_ground_i,
579  RXDFEXYDOVRDEN => tied_to_ground_i,
580  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
581  RXDISPERR(7 downto 4) => rxdisperr_float_i,
582  RXDISPERR(3 downto 0) => RXDISPERR_OUT,
583  RXNOTINTABLE(7 downto 4) => rxnotintable_float_i,
584  RXNOTINTABLE(3 downto 0) => RXNOTINTABLE_OUT,
585  --------------------------- Receive Ports - RX AFE -------------------------
586  GTXRXP => GTXRXP_IN ,
587  ------------------------ Receive Ports - RX AFE Ports ----------------------
588  GTXRXN => GTXRXN_IN ,
589  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
590  RXBUFRESET => tied_to_ground_i,
591  RXBUFSTATUS => RXBUFSTATUS_OUT,
592  RXDDIEN => tied_to_ground_i,
593  RXDLYBYPASS => tied_to_vcc_i,
594  RXDLYEN => tied_to_ground_i,
595  RXDLYOVRDEN => tied_to_ground_i,
596  RXDLYSRESET => tied_to_ground_i,
597  RXDLYSRESETDONE => open,
598  RXPHALIGN => tied_to_ground_i,
599  RXPHALIGNDONE => open,
600  RXPHALIGNEN => tied_to_ground_i,
601  RXPHDLYPD => tied_to_ground_i,
602  RXPHDLYRESET => tied_to_ground_i,
603  RXPHMONITOR => open,
604  RXPHOVRDEN => tied_to_ground_i,
605  RXPHSLIPMONITOR => open,
606  RXSTATUS => open,
607  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
608  RXBYTEISALIGNED => RXBYTEISALIGNED_OUT ,
609  RXBYTEREALIGN => RXBYTEREALIGN_OUT,
610  RXCOMMADET => RXCOMMADET_OUT,
611  RXCOMMADETEN => tied_to_vcc_i,
612  RXMCOMMAALIGNEN => RXMCOMMAALIGNEN_IN,
613  RXPCOMMAALIGNEN => RXPCOMMAALIGNEN_IN,
614  ------------------ Receive Ports - RX Channel Bonding Ports ----------------
615  RXCHANBONDSEQ => open,
616  RXCHBONDEN => tied_to_ground_i,
617  RXCHBONDLEVEL => tied_to_ground_vec_i (2 downto 0),
618  RXCHBONDMASTER => tied_to_ground_i,
619  RXCHBONDO => open,
620  RXCHBONDSLAVE => tied_to_ground_i,
621  ----------------- Receive Ports - RX Channel Bonding Ports ----------------
622  RXCHANISALIGNED => open,
623  RXCHANREALIGN => open,
624  -------------------- Receive Ports - RX Equailizer Ports -------------------
625  RXLPMHFHOLD => tied_to_ground_i,
626  RXLPMHFOVRDEN => tied_to_ground_i,
627  RXLPMLFHOLD => tied_to_ground_i,
628  --------------------- Receive Ports - RX Equalizer Ports -------------------
629  RXDFEAGCHOLD => RXDFEAGCHOLD_IN,
630  RXDFEAGCOVRDEN => tied_to_ground_i,
631  RXDFECM1EN => tied_to_ground_i,
632  RXDFELFHOLD => RXDFELFHOLD_IN,
633  RXDFELFOVRDEN => tied_to_vcc_i,
634  RXDFELPMRESET => tied_to_ground_i,
635  RXDFETAP2HOLD => tied_to_ground_i,
636  RXDFETAP2OVRDEN => tied_to_ground_i,
637  RXDFETAP3HOLD => tied_to_ground_i,
638  RXDFETAP3OVRDEN => tied_to_ground_i,
639  RXDFETAP4HOLD => tied_to_ground_i,
640  RXDFETAP4OVRDEN => tied_to_ground_i,
641  RXDFETAP5HOLD => tied_to_ground_i,
642  RXDFETAP5OVRDEN => tied_to_ground_i,
643  RXDFEUTHOLD => tied_to_ground_i,
644  RXDFEUTOVRDEN => tied_to_ground_i,
645  RXDFEVPHOLD => tied_to_ground_i,
646  RXDFEVPOVRDEN => tied_to_ground_i,
647  RXDFEVSEN => tied_to_ground_i,
648  RXLPMLFKLOVRDEN => tied_to_ground_i,
649  RXMONITOROUT => open,
650  RXMONITORSEL => "00",
651  RXOSHOLD => tied_to_ground_i,
652  RXOSOVRDEN => tied_to_ground_i,
653  ------------ Receive Ports - RX Fabric ClocK Output Control Ports ----------
654  RXRATEDONE => open,
655  --------------- Receive Ports - RX Fabric Output Control Ports -------------
656  RXOUTCLK => RXOUTCLK_OUT,
657  RXOUTCLKFABRIC => open,
658  RXOUTCLKPCS => open,
659  RXOUTCLKSEL => "010",
660  ---------------------- Receive Ports - RX Gearbox Ports --------------------
661  RXDATAVALID => open,
662  RXHEADER => open,
663  RXHEADERVALID => open,
664  RXSTARTOFSEQ => open,
665  --------------------- Receive Ports - RX Gearbox Ports --------------------
666  RXGEARBOXSLIP => tied_to_ground_i,
667  ------------- Receive Ports - RX Initialization and Reset Ports ------------
668  GTRXRESET => GTRXRESET_IN,
669  RXOOBRESET => tied_to_ground_i,
670  RXPCSRESET => tied_to_ground_i,
671  RXPMARESET => RXPMARESET_IN,
672  ------------------ Receive Ports - RX Margin Analysis ports ----------------
673  RXLPMEN => tied_to_ground_i,
674  ------------------- Receive Ports - RX OOB Signaling ports -----------------
675  RXCOMSASDET => open,
676  RXCOMWAKEDET => open,
677  ------------------ Receive Ports - RX OOB Signaling ports -----------------
678  RXCOMINITDET => open,
679  ------------------ Receive Ports - RX OOB signalling Ports -----------------
680  RXELECIDLE => open,
681  RXELECIDLEMODE => "11",
682  ----------------- Receive Ports - RX Polarity Control Ports ----------------
683  RXPOLARITY => tied_to_ground_i,
684  ---------------------- Receive Ports - RX gearbox ports --------------------
685  RXSLIDE => tied_to_ground_i,
686  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
687  RXCHARISCOMMA(7 downto 4) => rxchariscomma_float_i ,
688  RXCHARISCOMMA(3 downto 0) => RXCHARISCOMMA_OUT,
689  RXCHARISK(7 downto 4) => rxcharisk_float_i,
690  RXCHARISK(3 downto 0) => RXCHARISK_OUT,
691  ------------------ Receive Ports - Rx Channel Bonding Ports ----------------
692  RXCHBONDI => "00000",
693  -------------- Receive Ports -RX Initialization and Reset Ports ------------
694  RXRESETDONE => RXRESETDONE_OUT,
695  -------------------------------- Rx AFE Ports ------------------------------
696  RXQPIEN => tied_to_ground_i,
697  RXQPISENN => open,
698  RXQPISENP => open,
699  --------------------------- TX Buffer Bypass Ports -------------------------
700  TXPHDLYTSTCLK => tied_to_ground_i,
701  ------------------------ TX Configurable Driver Ports ----------------------
702  TXPOSTCURSOR => "00000",
703  TXPOSTCURSORINV => tied_to_ground_i,
704  TXPRECURSOR => tied_to_ground_vec_i (4 downto 0),
705  TXPRECURSORINV => tied_to_ground_i,
706  TXQPIBIASEN => tied_to_ground_i,
707  TXQPISTRONGPDOWN => tied_to_ground_i,
708  TXQPIWEAKPUP => tied_to_ground_i,
709  --------------------- TX Initialization and Reset Ports --------------------
710  CFGRESET => tied_to_ground_i,
711  GTTXRESET => GTTXRESET_IN,
712  PCSRSVDOUT => open,
713  TXUSERRDY => TXUSERRDY_IN,
714  ---------------------- Transceiver Reset Mode Operation --------------------
715  GTRESETSEL => tied_to_ground_i,
716  RESETOVRD => tied_to_ground_i,
717  ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
718  TXCHARDISPMODE => tied_to_ground_vec_i (7 downto 0),
719  TXCHARDISPVAL => tied_to_ground_vec_i (7 downto 0),
720  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
721  TXUSRCLK => TXUSRCLK_IN,
722  TXUSRCLK2 => TXUSRCLK2_IN,
723  --------------------- Transmit Ports - PCI Express Ports -------------------
724  TXELECIDLE => tied_to_ground_i,
725  TXMARGIN => tied_to_ground_vec_i (2 downto 0),
726  TXRATE => tied_to_ground_vec_i (2 downto 0),
727  TXSWING => tied_to_ground_i,
728  ------------------ Transmit Ports - Pattern Generator Ports ----------------
729  TXPRBSFORCEERR => tied_to_ground_i,
730  ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
731  TXDLYBYPASS => tied_to_vcc_i,
732  TXDLYEN => tied_to_ground_i,
733  TXDLYHOLD => tied_to_ground_i,
734  TXDLYOVRDEN => tied_to_ground_i,
735  TXDLYSRESET => tied_to_ground_i,
736  TXDLYSRESETDONE => open,
737  TXDLYUPDOWN => tied_to_ground_i,
738  TXPHALIGN => tied_to_ground_i,
739  TXPHALIGNDONE => open,
740  TXPHALIGNEN => tied_to_ground_i,
741  TXPHDLYPD => tied_to_ground_i,
742  TXPHDLYRESET => tied_to_ground_i,
743  TXPHINIT => tied_to_ground_i,
744  TXPHINITDONE => open,
745  TXPHOVRDEN => tied_to_ground_i,
746  ---------------------- Transmit Ports - TX Buffer Ports --------------------
747  TXBUFSTATUS => open,
748  --------------- Transmit Ports - TX Configurable Driver Ports --------------
749  TXBUFDIFFCTRL => "100",
750  TXDEEMPH => tied_to_ground_i,
751  TXDIFFCTRL => "1000",
752  TXDIFFPD => tied_to_ground_i,
753  TXINHIBIT => tied_to_ground_i,
754  TXMAINCURSOR => "0000000" ,
755  TXPISOPD => tied_to_ground_i,
756  ------------------ Transmit Ports - TX Data Path interface -----------------
757  TXDATA => txdata_i,
758  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
759  GTXTXN => GTXTXN_OUT,
760  GTXTXP => GTXTXP_OUT,
761  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
762  TXOUTCLK => TXOUTCLK_OUT,
763  TXOUTCLKFABRIC => TXOUTCLKFABRIC_OUT ,
764  TXOUTCLKPCS => TXOUTCLKPCS_OUT,
765  TXOUTCLKSEL => "011",
766  TXRATEDONE => open,
767  --------------------- Transmit Ports - TX Gearbox Ports --------------------
768  TXCHARISK(7 downto 4) => tied_to_ground_vec_i (3 downto 0),
769  TXCHARISK(3 downto 0) => TXCHARISK_IN,
770  TXGEARBOXREADY => open,
771  TXHEADER => tied_to_ground_vec_i (2 downto 0),
772  TXSEQUENCE => tied_to_ground_vec_i (6 downto 0),
773  TXSTARTSEQ => tied_to_ground_i,
774  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
775  TXPCSRESET => tied_to_ground_i,
776  TXPMARESET => tied_to_ground_i,
777  TXRESETDONE => TXRESETDONE_OUT,
778  ------------------ Transmit Ports - TX OOB signalling Ports ----------------
779  TXCOMFINISH => open,
780  TXCOMINIT => tied_to_ground_i,
781  TXCOMSAS => tied_to_ground_i,
782  TXCOMWAKE => tied_to_ground_i,
783  TXPDELECIDLEMODE => tied_to_ground_i,
784  ----------------- Transmit Ports - TX Polarity Control Ports ---------------
785  TXPOLARITY => tied_to_ground_i,
786  --------------- Transmit Ports - TX Receiver Detection Ports --------------
787  TXDETECTRX => tied_to_ground_i,
788  ------------------ Transmit Ports - TX8b/10b Encoder Ports -----------------
789  TX8B10BBYPASS => tied_to_ground_vec_i (7 downto 0),
790  ------------------ Transmit Ports - pattern Generator Ports ----------------
791  TXPRBSSEL => tied_to_ground_vec_i (2 downto 0),
792  ----------------------- Tx Configurable Driver Ports ----------------------
793  TXQPISENN => open,
794  TXQPISENP => open
795 
796  );
797 
798  end RTL;
799 
800 
801 
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