AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
 All Classes Variables
serdes5_wrapper.vhd
1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 10:12:42 12/19/2013
6 -- Design Name:
7 -- Module Name: serdes5_wrapper - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 library IEEE;
21 use IEEE.STD_LOGIC_1164.ALL;
22 use work.amc13_pack.all;
23 
24 -- Uncomment the following library declaration if using
25 -- arithmetic functions with Signed or Unsigned values
26 --use IEEE.NUMERIC_STD.ALL;
27 
28 -- Uncomment the following library declaration if instantiating
29 -- any Xilinx primitives in this code.
30 library UNISIM;
31 use UNISIM.VComponents.all;
32 
33 entity serdes5_wrapper is
34  Port ( refclk : in STD_LOGIC;
35  DRPclk : in STD_LOGIC;
36  sfp_pd : in array3x2;
37  txusrclk_out : out STD_LOGIC;
38  qplllock : out STD_LOGIC;
39  gtx_reset : in STD_LOGIC;
40  data_valid : in STD_LOGIC_VECTOR (2 downto 0);
41  sfp_rxp : in STD_LOGIC_VECTOR (2 downto 0);
42  sfp_rxn : in STD_LOGIC_VECTOR (2 downto 0);
43  txfsmresetdone : out STD_LOGIC_VECTOR (2 downto 0);
44  rxfsmresetdone : out STD_LOGIC_VECTOR (2 downto 0);
45  rxcdrlock : out STD_LOGIC_VECTOR (2 downto 0);
46  rxnotintable : out array3x4;
47  rxmcommaalignen : in STD_LOGIC_VECTOR (2 downto 0);
48  rxpcommaalignen : in STD_LOGIC_VECTOR (2 downto 0);
49  rxbyteisaligned : out STD_LOGIC_VECTOR (2 downto 0);
50  rxbyterealign : out STD_LOGIC_VECTOR (2 downto 0);
51  rxcommadet : out STD_LOGIC_VECTOR (2 downto 0);
52  rxchariscomma : out array3x4;
53  rxcharisk : out array3x4;
54  rxresetdone : out STD_LOGIC_VECTOR (2 downto 0);
55  txresetdone : out STD_LOGIC_VECTOR (2 downto 0);
56  txcharisk : in array3x4;
57  txdata : in array3x32;
58  rxdata : out array3x32;
59  sfp_txp : out STD_LOGIC_VECTOR (2 downto 0);
60  sfp_txn : out STD_LOGIC_VECTOR (2 downto 0));
61 end serdes5_wrapper;
62 
63 architecture Behavioral of serdes5_wrapper is
64 component serdes5GpdProd_init
65 generic
66 (
67  -- Simulation attributes
68  EXAMPLE_SIM_GTRESET_SPEEDUP : string := "FALSE"; -- Set to 1 to speed up sim reset
69  EXAMPLE_SIMULATION : integer := 0; -- Set to 1 for simulation
70  STABLE_CLOCK_PERIOD : integer := 20; --Period of the stable clock driving this state-machine, unit is [ns]
71  EXAMPLE_USE_CHIPSCOPE : integer := 0 -- Set to 1 to use Chipscope to drive resets
72 
73 );
74 port
75 (
76  SYSCLK_IN : in std_logic;
77  SOFT_RESET_IN : in std_logic;
78  DONT_RESET_ON_DATA_ERROR_IN : in std_logic;
79  GT0_TX_FSM_RESET_DONE_OUT : out std_logic;
80  GT0_RX_FSM_RESET_DONE_OUT : out std_logic;
81  GT0_DATA_VALID_IN : in std_logic;
82  GT1_TX_FSM_RESET_DONE_OUT : out std_logic;
83  GT1_RX_FSM_RESET_DONE_OUT : out std_logic;
84  GT1_DATA_VALID_IN : in std_logic;
85  GT2_TX_FSM_RESET_DONE_OUT : out std_logic;
86  GT2_RX_FSM_RESET_DONE_OUT : out std_logic;
87  GT2_DATA_VALID_IN : in std_logic;
88 
89  --_________________________________________________________________________
90  --GT0 (X1Y12)
91  --____________________________CHANNEL PORTS________________________________
92  ---------------------------- Channel - DRP Ports --------------------------
93  GT0_DRPADDR_IN : in std_logic_vector(8 downto 0);
94  GT0_DRPCLK_IN : in std_logic;
95  GT0_DRPDI_IN : in std_logic_vector(15 downto 0);
96  GT0_DRPDO_OUT : out std_logic_vector(15 downto 0);
97  GT0_DRPEN_IN : in std_logic;
98  GT0_DRPRDY_OUT : out std_logic;
99  GT0_DRPWE_IN : in std_logic;
100  ------------------------------ Power-Down Ports ----------------------------
101  GT0_RXPD_IN : in std_logic_vector(1 downto 0);
102  GT0_TXPD_IN : in std_logic_vector(1 downto 0);
103  --------------------- RX Initialization and Reset Ports --------------------
104  GT0_RXUSERRDY_IN : in std_logic;
105  -------------------------- RX Margin Analysis Ports ------------------------
106  GT0_EYESCANDATAERROR_OUT : out std_logic;
107  ------------------------- Receive Ports - CDR Ports ------------------------
108  GT0_RXCDRLOCK_OUT : out std_logic;
109  ------------------- Receive Ports - Clock Correction Ports -----------------
110  GT0_RXCLKCORCNT_OUT : out std_logic_vector(1 downto 0);
111  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
112  GT0_RXUSRCLK_IN : in std_logic;
113  GT0_RXUSRCLK2_IN : in std_logic;
114  ------------------ Receive Ports - FPGA RX interface Ports -----------------
115  GT0_RXDATA_OUT : out std_logic_vector(31 downto 0);
116  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
117  GT0_RXDISPERR_OUT : out std_logic_vector(3 downto 0);
118  GT0_RXNOTINTABLE_OUT : out std_logic_vector(3 downto 0);
119  --------------------------- Receive Ports - RX AFE -------------------------
120  GT0_GTXRXP_IN : in std_logic;
121  ------------------------ Receive Ports - RX AFE Ports ----------------------
122  GT0_GTXRXN_IN : in std_logic;
123  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
124  GT0_RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
125  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
126  GT0_RXBYTEISALIGNED_OUT : out std_logic;
127  GT0_RXBYTEREALIGN_OUT : out std_logic;
128  GT0_RXCOMMADET_OUT : out std_logic;
129  GT0_RXMCOMMAALIGNEN_IN : in std_logic;
130  GT0_RXPCOMMAALIGNEN_IN : in std_logic;
131  ------------- Receive Ports - RX Initialization and Reset Ports ------------
132  GT0_GTRXRESET_IN : in std_logic;
133  GT0_RXPMARESET_IN : in std_logic;
134  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
135  GT0_RXCHARISCOMMA_OUT : out std_logic_vector(3 downto 0);
136  GT0_RXCHARISK_OUT : out std_logic_vector(3 downto 0);
137  -------------- Receive Ports -RX Initialization and Reset Ports ------------
138  GT0_RXRESETDONE_OUT : out std_logic;
139  --------------------- TX Initialization and Reset Ports --------------------
140  GT0_GTTXRESET_IN : in std_logic;
141  GT0_TXUSERRDY_IN : in std_logic;
142  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
143  GT0_TXUSRCLK_IN : in std_logic;
144  GT0_TXUSRCLK2_IN : in std_logic;
145  ------------------ Transmit Ports - TX Data Path interface -----------------
146  GT0_TXDATA_IN : in std_logic_vector(31 downto 0);
147  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
148  GT0_GTXTXN_OUT : out std_logic;
149  GT0_GTXTXP_OUT : out std_logic;
150  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
151  GT0_TXOUTCLK_OUT : out std_logic;
152  GT0_TXOUTCLKFABRIC_OUT : out std_logic;
153  GT0_TXOUTCLKPCS_OUT : out std_logic;
154  --------------------- Transmit Ports - TX Gearbox Ports --------------------
155  GT0_TXCHARISK_IN : in std_logic_vector(3 downto 0);
156  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
157  GT0_TXRESETDONE_OUT : out std_logic;
158 
159  --_________________________________________________________________________
160  --GT1 (X1Y13)
161  --____________________________CHANNEL PORTS________________________________
162  ---------------------------- Channel - DRP Ports --------------------------
163  GT1_DRPADDR_IN : in std_logic_vector(8 downto 0);
164  GT1_DRPCLK_IN : in std_logic;
165  GT1_DRPDI_IN : in std_logic_vector(15 downto 0);
166  GT1_DRPDO_OUT : out std_logic_vector(15 downto 0);
167  GT1_DRPEN_IN : in std_logic;
168  GT1_DRPRDY_OUT : out std_logic;
169  GT1_DRPWE_IN : in std_logic;
170  ------------------------------ Power-Down Ports ----------------------------
171  GT1_RXPD_IN : in std_logic_vector(1 downto 0);
172  GT1_TXPD_IN : in std_logic_vector(1 downto 0);
173  --------------------- RX Initialization and Reset Ports --------------------
174  GT1_RXUSERRDY_IN : in std_logic;
175  -------------------------- RX Margin Analysis Ports ------------------------
176  GT1_EYESCANDATAERROR_OUT : out std_logic;
177  ------------------------- Receive Ports - CDR Ports ------------------------
178  GT1_RXCDRLOCK_OUT : out std_logic;
179  ------------------- Receive Ports - Clock Correction Ports -----------------
180  GT1_RXCLKCORCNT_OUT : out std_logic_vector(1 downto 0);
181  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
182  GT1_RXUSRCLK_IN : in std_logic;
183  GT1_RXUSRCLK2_IN : in std_logic;
184  ------------------ Receive Ports - FPGA RX interface Ports -----------------
185  GT1_RXDATA_OUT : out std_logic_vector(31 downto 0);
186  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
187  GT1_RXDISPERR_OUT : out std_logic_vector(3 downto 0);
188  GT1_RXNOTINTABLE_OUT : out std_logic_vector(3 downto 0);
189  --------------------------- Receive Ports - RX AFE -------------------------
190  GT1_GTXRXP_IN : in std_logic;
191  ------------------------ Receive Ports - RX AFE Ports ----------------------
192  GT1_GTXRXN_IN : in std_logic;
193  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
194  GT1_RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
195  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
196  GT1_RXBYTEISALIGNED_OUT : out std_logic;
197  GT1_RXBYTEREALIGN_OUT : out std_logic;
198  GT1_RXCOMMADET_OUT : out std_logic;
199  GT1_RXMCOMMAALIGNEN_IN : in std_logic;
200  GT1_RXPCOMMAALIGNEN_IN : in std_logic;
201  ------------- Receive Ports - RX Initialization and Reset Ports ------------
202  GT1_GTRXRESET_IN : in std_logic;
203  GT1_RXPMARESET_IN : in std_logic;
204  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
205  GT1_RXCHARISCOMMA_OUT : out std_logic_vector(3 downto 0);
206  GT1_RXCHARISK_OUT : out std_logic_vector(3 downto 0);
207  -------------- Receive Ports -RX Initialization and Reset Ports ------------
208  GT1_RXRESETDONE_OUT : out std_logic;
209  --------------------- TX Initialization and Reset Ports --------------------
210  GT1_GTTXRESET_IN : in std_logic;
211  GT1_TXUSERRDY_IN : in std_logic;
212  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
213  GT1_TXUSRCLK_IN : in std_logic;
214  GT1_TXUSRCLK2_IN : in std_logic;
215  ------------------ Transmit Ports - TX Data Path interface -----------------
216  GT1_TXDATA_IN : in std_logic_vector(31 downto 0);
217  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
218  GT1_GTXTXN_OUT : out std_logic;
219  GT1_GTXTXP_OUT : out std_logic;
220  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
221  GT1_TXOUTCLK_OUT : out std_logic;
222  GT1_TXOUTCLKFABRIC_OUT : out std_logic;
223  GT1_TXOUTCLKPCS_OUT : out std_logic;
224  --------------------- Transmit Ports - TX Gearbox Ports --------------------
225  GT1_TXCHARISK_IN : in std_logic_vector(3 downto 0);
226  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
227  GT1_TXRESETDONE_OUT : out std_logic;
228 
229  --_________________________________________________________________________
230  --GT2 (X1Y14)
231  --____________________________CHANNEL PORTS________________________________
232  ---------------------------- Channel - DRP Ports --------------------------
233  GT2_DRPADDR_IN : in std_logic_vector(8 downto 0);
234  GT2_DRPCLK_IN : in std_logic;
235  GT2_DRPDI_IN : in std_logic_vector(15 downto 0);
236  GT2_DRPDO_OUT : out std_logic_vector(15 downto 0);
237  GT2_DRPEN_IN : in std_logic;
238  GT2_DRPRDY_OUT : out std_logic;
239  GT2_DRPWE_IN : in std_logic;
240  ------------------------------ Power-Down Ports ----------------------------
241  GT2_RXPD_IN : in std_logic_vector(1 downto 0);
242  GT2_TXPD_IN : in std_logic_vector(1 downto 0);
243  --------------------- RX Initialization and Reset Ports --------------------
244  GT2_RXUSERRDY_IN : in std_logic;
245  -------------------------- RX Margin Analysis Ports ------------------------
246  GT2_EYESCANDATAERROR_OUT : out std_logic;
247  ------------------------- Receive Ports - CDR Ports ------------------------
248  GT2_RXCDRLOCK_OUT : out std_logic;
249  ------------------- Receive Ports - Clock Correction Ports -----------------
250  GT2_RXCLKCORCNT_OUT : out std_logic_vector(1 downto 0);
251  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
252  GT2_RXUSRCLK_IN : in std_logic;
253  GT2_RXUSRCLK2_IN : in std_logic;
254  ------------------ Receive Ports - FPGA RX interface Ports -----------------
255  GT2_RXDATA_OUT : out std_logic_vector(31 downto 0);
256  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
257  GT2_RXDISPERR_OUT : out std_logic_vector(3 downto 0);
258  GT2_RXNOTINTABLE_OUT : out std_logic_vector(3 downto 0);
259  --------------------------- Receive Ports - RX AFE -------------------------
260  GT2_GTXRXP_IN : in std_logic;
261  ------------------------ Receive Ports - RX AFE Ports ----------------------
262  GT2_GTXRXN_IN : in std_logic;
263  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
264  GT2_RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
265  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
266  GT2_RXBYTEISALIGNED_OUT : out std_logic;
267  GT2_RXBYTEREALIGN_OUT : out std_logic;
268  GT2_RXCOMMADET_OUT : out std_logic;
269  GT2_RXMCOMMAALIGNEN_IN : in std_logic;
270  GT2_RXPCOMMAALIGNEN_IN : in std_logic;
271  ------------- Receive Ports - RX Initialization and Reset Ports ------------
272  GT2_GTRXRESET_IN : in std_logic;
273  GT2_RXPMARESET_IN : in std_logic;
274  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
275  GT2_RXCHARISCOMMA_OUT : out std_logic_vector(3 downto 0);
276  GT2_RXCHARISK_OUT : out std_logic_vector(3 downto 0);
277  -------------- Receive Ports -RX Initialization and Reset Ports ------------
278  GT2_RXRESETDONE_OUT : out std_logic;
279  --------------------- TX Initialization and Reset Ports --------------------
280  GT2_GTTXRESET_IN : in std_logic;
281  GT2_TXUSERRDY_IN : in std_logic;
282  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
283  GT2_TXUSRCLK_IN : in std_logic;
284  GT2_TXUSRCLK2_IN : in std_logic;
285  ------------------ Transmit Ports - TX Data Path interface -----------------
286  GT2_TXDATA_IN : in std_logic_vector(31 downto 0);
287  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
288  GT2_GTXTXN_OUT : out std_logic;
289  GT2_GTXTXP_OUT : out std_logic;
290  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
291  GT2_TXOUTCLK_OUT : out std_logic;
292  GT2_TXOUTCLKFABRIC_OUT : out std_logic;
293  GT2_TXOUTCLKPCS_OUT : out std_logic;
294  --------------------- Transmit Ports - TX Gearbox Ports --------------------
295  GT2_TXCHARISK_IN : in std_logic_vector(3 downto 0);
296  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
297  GT2_TXRESETDONE_OUT : out std_logic;
298 
299 
300  --____________________________COMMON PORTS________________________________
301  ---------------------- Common Block - Ref Clock Ports ---------------------
302  GT0_GTREFCLK0_COMMON_IN : in std_logic;
303  ------------------------- Common Block - QPLL Ports ------------------------
304  GT0_QPLLLOCK_OUT : out std_logic;
305  GT0_QPLLLOCKDETCLK_IN : in std_logic;
306  GT0_QPLLRESET_IN : in std_logic
307 
308 
309 );
310 end component;
311 signal txusrclk : std_logic := '0';
312 signal gt0_txoutclk : std_logic := '0';
313 --signal : std_logic := '0';
314 --signal : std_logic_vector(2 downto 0) := (others => '0');
315 
316 begin
317  serdes5Gpd_init_i : serdes5GpdProd_init
318  port map
319  (
320  SYSCLK_IN => DRPclk,
321  SOFT_RESET_IN => '0',
322  DONT_RESET_ON_DATA_ERROR_IN => '0',
323  GT0_TX_FSM_RESET_DONE_OUT => txfsmresetdone(0),
324  GT0_RX_FSM_RESET_DONE_OUT => rxfsmresetdone(0),
325  GT0_DATA_VALID_IN => data_valid(0),
326  GT1_TX_FSM_RESET_DONE_OUT => txfsmresetdone(1),
327  GT1_RX_FSM_RESET_DONE_OUT => rxfsmresetdone(1),
328  GT1_DATA_VALID_IN => data_valid(1),
329  GT2_TX_FSM_RESET_DONE_OUT => txfsmresetdone(2),
330  GT2_RX_FSM_RESET_DONE_OUT => rxfsmresetdone(2),
331  GT2_DATA_VALID_IN => data_valid(2),
332 
333 
334 
335 
336 
337  --_____________________________________________________________________
338  --_____________________________________________________________________
339  --GT0 (X1Y12)
340 
341  ---------------------------- Channel - DRP Ports --------------------------
342  GT0_DRPADDR_IN => (others => '0'),
343  GT0_DRPCLK_IN => DRPclk,
344  GT0_DRPDI_IN => (others => '0'),
345  GT0_DRPDO_OUT => open,
346  GT0_DRPEN_IN => '0',
347  GT0_DRPRDY_OUT => open,
348  GT0_DRPWE_IN => '0',
349  ------------------------------ Power-Down Ports ----------------------------
350  GT0_RXPD_IN => sfp_pd(0),
351  GT0_TXPD_IN => sfp_pd(0),
352  --------------------- RX Initialization and Reset Ports --------------------
353  GT0_RXUSERRDY_IN => '0',
354  -------------------------- RX Margin Analysis Ports ------------------------
355  GT0_EYESCANDATAERROR_OUT => open,
356  ------------------------- Receive Ports - CDR Ports ------------------------
357  GT0_RXCDRLOCK_OUT => rxcdrlock(0),
358  ------------------- Receive Ports - Clock Correction Ports -----------------
359  GT0_RXCLKCORCNT_OUT => open,
360  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
361  GT0_RXUSRCLK_IN => txusrclk,
362  GT0_RXUSRCLK2_IN => txusrclk,
363  ------------------ Receive Ports - FPGA RX interface Ports -----------------
364  GT0_RXDATA_OUT => rxdata(0),
365  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
366  GT0_RXDISPERR_OUT => open,
367  GT0_RXNOTINTABLE_OUT => rxnotintable(0),
368  --------------------------- Receive Ports - RX AFE -------------------------
369  GT0_GTXRXP_IN => sfp_rxp(0),
370  ------------------------ Receive Ports - RX AFE Ports ----------------------
371  GT0_GTXRXN_IN => sfp_rxn(0),
372  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
373  GT0_RXBUFSTATUS_OUT => open,
374  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
375  GT0_RXBYTEISALIGNED_OUT => rxbyteisaligned(0),
376  GT0_RXBYTEREALIGN_OUT => rxbyterealign(0),
377  GT0_RXCOMMADET_OUT => rxcommadet(0),
378  GT0_RXMCOMMAALIGNEN_IN => rxmcommaalignen(0),
379  GT0_RXPCOMMAALIGNEN_IN => rxpcommaalignen(0),
380  ------------- Receive Ports - RX Initialization and Reset Ports ------------
381  GT0_GTRXRESET_IN => gtx_reset,
382  GT0_RXPMARESET_IN => '0',
383  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
384  GT0_RXCHARISCOMMA_OUT => rxchariscomma(0),
385  GT0_RXCHARISK_OUT => rxcharisk(0),
386  -------------- Receive Ports -RX Initialization and Reset Ports ------------
387  GT0_RXRESETDONE_OUT => rxresetdone(0),
388  --------------------- TX Initialization and Reset Ports --------------------
389  GT0_GTTXRESET_IN => gtx_reset,
390  GT0_TXUSERRDY_IN => '0',
391  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
392  GT0_TXUSRCLK_IN => txusrclk,
393  GT0_TXUSRCLK2_IN => txusrclk,
394  ------------------ Transmit Ports - TX Data Path interface -----------------
395  GT0_TXDATA_IN => txdata(0),
396  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
397  GT0_GTXTXN_OUT => sfp_txn(0),
398  GT0_GTXTXP_OUT => sfp_txp(0),
399  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
400  GT0_TXOUTCLK_OUT => gt0_txoutclk,
401  GT0_TXOUTCLKFABRIC_OUT => open,
402  GT0_TXOUTCLKPCS_OUT => open,
403  --------------------- Transmit Ports - TX Gearbox Ports --------------------
404  GT0_TXCHARISK_IN => txcharisk(0),
405  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
406  GT0_TXRESETDONE_OUT => txresetdone(0),
407 
408 
409 
410 
411 
412 
413  --_____________________________________________________________________
414  --_____________________________________________________________________
415  --GT1 (X1Y13)
416 
417  ---------------------------- Channel - DRP Ports --------------------------
418  GT1_DRPADDR_IN => (others => '0'),
419  GT1_DRPCLK_IN => DRPclk,
420  GT1_DRPDI_IN => (others => '0'),
421  GT1_DRPDO_OUT => open,
422  GT1_DRPEN_IN => '0',
423  GT1_DRPRDY_OUT => open,
424  GT1_DRPWE_IN => '0',
425  ------------------------------ Power-Down Ports ----------------------------
426  GT1_RXPD_IN => sfp_pd(1),
427  GT1_TXPD_IN => sfp_pd(1),
428  --------------------- RX Initialization and Reset Ports --------------------
429  GT1_RXUSERRDY_IN => '0',
430  -------------------------- RX Margin Analysis Ports ------------------------
431  GT1_EYESCANDATAERROR_OUT => open,
432  ------------------------- Receive Ports - CDR Ports ------------------------
433  GT1_RXCDRLOCK_OUT => rxcdrlock(1),
434  ------------------- Receive Ports - Clock Correction Ports -----------------
435  GT1_RXCLKCORCNT_OUT => open,
436  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
437  GT1_RXUSRCLK_IN => txusrclk,
438  GT1_RXUSRCLK2_IN => txusrclk,
439  ------------------ Receive Ports - FPGA RX interface Ports -----------------
440  GT1_RXDATA_OUT => rxdata(1),
441  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
442  GT1_RXDISPERR_OUT => open,
443  GT1_RXNOTINTABLE_OUT => rxnotintable(1),
444  --------------------------- Receive Ports - RX AFE -------------------------
445  GT1_GTXRXP_IN => sfp_rxp(1),
446  ------------------------ Receive Ports - RX AFE Ports ----------------------
447  GT1_GTXRXN_IN => sfp_rxn(1),
448  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
449  GT1_RXBUFSTATUS_OUT => open,
450  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
451  GT1_RXBYTEISALIGNED_OUT => rxbyteisaligned(1),
452  GT1_RXBYTEREALIGN_OUT => rxbyterealign(1),
453  GT1_RXCOMMADET_OUT => rxcommadet(1),
454  GT1_RXMCOMMAALIGNEN_IN => rxmcommaalignen(1),
455  GT1_RXPCOMMAALIGNEN_IN => rxpcommaalignen(1),
456  ------------- Receive Ports - RX Initialization and Reset Ports ------------
457  GT1_GTRXRESET_IN => gtx_reset,
458  GT1_RXPMARESET_IN => '0',
459  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
460  GT1_RXCHARISCOMMA_OUT => rxchariscomma(1),
461  GT1_RXCHARISK_OUT => rxcharisk(1),
462  -------------- Receive Ports -RX Initialization and Reset Ports ------------
463  GT1_RXRESETDONE_OUT => rxresetdone(1),
464  --------------------- TX Initialization and Reset Ports --------------------
465  GT1_GTTXRESET_IN => gtx_reset,
466  GT1_TXUSERRDY_IN => '0',
467  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
468  GT1_TXUSRCLK_IN => txusrclk,
469  GT1_TXUSRCLK2_IN => txusrclk,
470  ------------------ Transmit Ports - TX Data Path interface -----------------
471  GT1_TXDATA_IN => txdata(1),
472  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
473  GT1_GTXTXN_OUT => sfp_txn(1),
474  GT1_GTXTXP_OUT => sfp_txp(1),
475  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
476  GT1_TXOUTCLK_OUT => open,
477  GT1_TXOUTCLKFABRIC_OUT => open,
478  GT1_TXOUTCLKPCS_OUT => open,
479  --------------------- Transmit Ports - TX Gearbox Ports --------------------
480  GT1_TXCHARISK_IN => txcharisk(1),
481  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
482  GT1_TXRESETDONE_OUT => txresetdone(1),
483 
484 
485 
486 
487 
488  --_____________________________________________________________________
489  --_____________________________________________________________________
490  --GT2 (X1Y14)
491 
492  ---------------------------- Channel - DRP Ports --------------------------
493  GT2_DRPADDR_IN => (others => '0'),
494  GT2_DRPCLK_IN => DRPclk,
495  GT2_DRPDI_IN => (others => '0'),
496  GT2_DRPDO_OUT => open,
497  GT2_DRPEN_IN => '0',
498  GT2_DRPRDY_OUT => open,
499  GT2_DRPWE_IN => '0',
500  ------------------------------ Power-Down Ports ----------------------------
501  GT2_RXPD_IN => sfp_pd(2),
502  GT2_TXPD_IN => sfp_pd(2),
503  --------------------- RX Initialization and Reset Ports --------------------
504  GT2_RXUSERRDY_IN => '0',
505  -------------------------- RX Margin Analysis Ports ------------------------
506  GT2_EYESCANDATAERROR_OUT => open,
507  ------------------------- Receive Ports - CDR Ports ------------------------
508  GT2_RXCDRLOCK_OUT => rxcdrlock(2),
509  ------------------- Receive Ports - Clock Correction Ports -----------------
510  GT2_RXCLKCORCNT_OUT => open,
511  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
512  GT2_RXUSRCLK_IN => txusrclk,
513  GT2_RXUSRCLK2_IN => txusrclk,
514  ------------------ Receive Ports - FPGA RX interface Ports -----------------
515  GT2_RXDATA_OUT => rxdata(2),
516  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
517  GT2_RXDISPERR_OUT => open,
518  GT2_RXNOTINTABLE_OUT => rxnotintable(2),
519  --------------------------- Receive Ports - RX AFE -------------------------
520  GT2_GTXRXP_IN => sfp_rxp(2),
521  ------------------------ Receive Ports - RX AFE Ports ----------------------
522  GT2_GTXRXN_IN => sfp_rxn(2),
523  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
524  GT2_RXBUFSTATUS_OUT => open,
525  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
526  GT2_RXBYTEISALIGNED_OUT => rxbyteisaligned(2),
527  GT2_RXBYTEREALIGN_OUT => rxbyterealign(2),
528  GT2_RXCOMMADET_OUT => rxcommadet(2),
529  GT2_RXMCOMMAALIGNEN_IN => rxmcommaalignen(2),
530  GT2_RXPCOMMAALIGNEN_IN => rxpcommaalignen(2),
531  ------------- Receive Ports - RX Initialization and Reset Ports ------------
532  GT2_GTRXRESET_IN => gtx_reset,
533  GT2_RXPMARESET_IN => '0',
534  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
535  GT2_RXCHARISCOMMA_OUT => rxchariscomma(2),
536  GT2_RXCHARISK_OUT => rxcharisk(2),
537  -------------- Receive Ports -RX Initialization and Reset Ports ------------
538  GT2_RXRESETDONE_OUT => rxresetdone(2),
539  --------------------- TX Initialization and Reset Ports --------------------
540  GT2_GTTXRESET_IN => gtx_reset,
541  GT2_TXUSERRDY_IN => '0',
542  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
543  GT2_TXUSRCLK_IN => txusrclk,
544  GT2_TXUSRCLK2_IN => txusrclk,
545  ------------------ Transmit Ports - TX Data Path interface -----------------
546  GT2_TXDATA_IN => txdata(2),
547  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
548  GT2_GTXTXN_OUT => sfp_txn(2),
549  GT2_GTXTXP_OUT => sfp_txp(2),
550  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
551  GT2_TXOUTCLK_OUT => open,
552  GT2_TXOUTCLKFABRIC_OUT => open,
553  GT2_TXOUTCLKPCS_OUT => open,
554  --------------------- Transmit Ports - TX Gearbox Ports --------------------
555  GT2_TXCHARISK_IN => txcharisk(2),
556  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
557  GT2_TXRESETDONE_OUT => txresetdone(2),
558 
559 
560 
561 
562  --____________________________COMMON PORTS________________________________
563  ---------------------- Common Block - Ref Clock Ports ---------------------
564  GT0_GTREFCLK0_COMMON_IN => refclk,
565  ------------------------- Common Block - QPLL Ports ------------------------
566  GT0_QPLLLOCK_OUT => qplllock,
567  GT0_QPLLLOCKDETCLK_IN => DRPclk,
568  GT0_QPLLRESET_IN => '0'
569 
570  );
571 
572 i_txusrclk: bufg port map(i => gt0_txoutclk, o => txusrclk);
573 txusrclk_out <= txusrclk;
574 
575 end Behavioral;
576 
Generated on Wed Apr 18 2018 10:55:26 for AMC13 by   doxygen 1.8.1