AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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s6link_init.vhd
1 ------------------------------------------------------------------------------
2 -- ____ ____
3 -- / /\/ /
4 -- /___/ \ / Vendor: Xilinx
5 -- \ \ \/ Version : 2.5
6 -- \ \ Application : 7 Series FPGAs Transceivers Wizard
7 -- / / Filename : s6link_init.vhd
8 -- /___/ /\
9 -- \ \ / \
10 -- \___\/\___\
11 --
12 -- Description : This module instantiates the modules required for
13 -- reset and initialisation of the Transceiver
14 --
15 -- Module S6Link_init
16 -- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
17 --
18 --
19 -- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
20 --
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64 
65 
66 library ieee;
67 use ieee.std_logic_1164.all;
68 use ieee.numeric_std.all;
69 use ieee.std_logic_unsigned.all;
70 library UNISIM;
71 use UNISIM.VCOMPONENTS.ALL;
72 
73 --***********************************Entity Declaration************************
74 
75 entity S6Link_init is
76 generic
77 (
78  EXAMPLE_SIM_GTRESET_SPEEDUP : string := "TRUE"; -- simulation setting for GT SecureIP model
79  EXAMPLE_SIMULATION : integer := 0; -- Set to 1 for simulation
80  EQ_MODE : string := "LPM"; -- Rx Equalization Mode - Set to DFE or LPM
81  EXAMPLE_USE_CHIPSCOPE : integer := 0 -- Set to 1 to use Chipscope to drive resets
82 
83 );
84 port
85 (
86  SYSCLK_IN : in std_logic;
87  SOFT_RESET_IN : in std_logic;
88  GT0_TX_FSM_RESET_DONE_OUT : out std_logic;
89  GT0_RX_FSM_RESET_DONE_OUT : out std_logic;
90  GT0_DATA_VALID_IN : in std_logic;
91 
92  --_________________________________________________________________________
93  --GT0 (X1Y15)
94  --____________________________CHANNEL PORTS________________________________
95  --------------------------------- CPLL Ports -------------------------------
96  GT0_CPLLFBCLKLOST_OUT : out std_logic;
97  GT0_CPLLLOCK_OUT : out std_logic;
98  GT0_CPLLLOCKDETCLK_IN : in std_logic;
99  GT0_CPLLRESET_IN : in std_logic;
100  -------------------------- Channel - Clocking Ports ------------------------
101  GT0_GTREFCLK0_IN : in std_logic;
102  ---------------------------- Channel - DRP Ports --------------------------
103  GT0_DRPADDR_IN : in std_logic_vector(8 downto 0);
104  GT0_DRPCLK_IN : in std_logic;
105  GT0_DRPDI_IN : in std_logic_vector(15 downto 0);
106  GT0_DRPDO_OUT : out std_logic_vector(15 downto 0);
107  GT0_DRPEN_IN : in std_logic;
108  GT0_DRPRDY_OUT : out std_logic;
109  GT0_DRPWE_IN : in std_logic;
110  --------------------- RX Initialization and Reset Ports --------------------
111  GT0_RXUSERRDY_IN : in std_logic;
112  -------------------------- RX Margin Analysis Ports ------------------------
113  GT0_EYESCANDATAERROR_OUT : out std_logic;
114  ------------------------- Receive Ports - CDR Ports ------------------------
115  GT0_RXCDRLOCK_OUT : out std_logic;
116  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
117  GT0_RXUSRCLK_IN : in std_logic;
118  GT0_RXUSRCLK2_IN : in std_logic;
119  ------------------ Receive Ports - FPGA RX interface Ports -----------------
120  GT0_RXDATA_OUT : out std_logic_vector(15 downto 0);
121  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
122  GT0_RXDISPERR_OUT : out std_logic_vector(1 downto 0);
123  GT0_RXNOTINTABLE_OUT : out std_logic_vector(1 downto 0);
124  --------------------------- Receive Ports - RX AFE -------------------------
125  GT0_GTXRXP_IN : in std_logic;
126  ------------------------ Receive Ports - RX AFE Ports ----------------------
127  GT0_GTXRXN_IN : in std_logic;
128  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
129  GT0_RXMCOMMAALIGNEN_IN : in std_logic;
130  GT0_RXPCOMMAALIGNEN_IN : in std_logic;
131  --------------------- Receive Ports - RX Equalizer Ports -------------------
132  GT0_RXDFELPMRESET_IN : in std_logic;
133  ------------- Receive Ports - RX Initialization and Reset Ports ------------
134  GT0_GTRXRESET_IN : in std_logic;
135  GT0_RXPMARESET_IN : in std_logic;
136  ----------------- Receive Ports - RX Polarity Control Ports ----------------
137  GT0_RXPOLARITY_IN : in std_logic;
138  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
139  GT0_RXCHARISK_OUT : out std_logic_vector(1 downto 0);
140  -------------- Receive Ports -RX Initialization and Reset Ports ------------
141  GT0_RXRESETDONE_OUT : out std_logic;
142  --------------------- TX Initialization and Reset Ports --------------------
143  GT0_GTTXRESET_IN : in std_logic;
144  GT0_TXUSERRDY_IN : in std_logic;
145  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
146  GT0_TXUSRCLK_IN : in std_logic;
147  GT0_TXUSRCLK2_IN : in std_logic;
148  ------------------ Transmit Ports - TX Data Path interface -----------------
149  GT0_TXDATA_IN : in std_logic_vector(15 downto 0);
150  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
151  GT0_GTXTXN_OUT : out std_logic;
152  GT0_GTXTXP_OUT : out std_logic;
153  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
154  GT0_TXOUTCLK_OUT : out std_logic;
155  GT0_TXOUTCLKFABRIC_OUT : out std_logic;
156  GT0_TXOUTCLKPCS_OUT : out std_logic;
157  --------------------- Transmit Ports - TX Gearbox Ports --------------------
158  GT0_TXCHARISK_IN : in std_logic_vector(1 downto 0);
159  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
160  GT0_TXRESETDONE_OUT : out std_logic;
161  ----------------- Transmit Ports - TX Polarity Control Ports ---------------
162  GT0_TXPOLARITY_IN : in std_logic;
163 
164 
165  --____________________________COMMON PORTS________________________________
166  ---------------------- Common Block - Ref Clock Ports ---------------------
167  GT0_GTREFCLK0_COMMON_IN : in std_logic;
168  ------------------------- Common Block - QPLL Ports ------------------------
169  GT0_QPLLLOCK_OUT : out std_logic;
170  GT0_QPLLLOCKDETCLK_IN : in std_logic;
171  GT0_QPLLRESET_IN : in std_logic
172 
173 
174 );
175 
176 end S6Link_init;
177 
178 architecture RTL of S6Link_init is
179 
180 --**************************Component Declarations*****************************
181 
182 
183 component S6Link
184 generic
185 (
186  -- Simulation attributes
187  WRAPPER_SIM_GTRESET_SPEEDUP : string := "FALSE" -- Set to 1 to speed up sim reset
188 
189 );
190 port
191 (
192 
193  --_________________________________________________________________________
194  --_________________________________________________________________________
195  --GT0 (X1Y15)
196  --____________________________CHANNEL PORTS________________________________
197  --------------------------------- CPLL Ports -------------------------------
198  GT0_CPLLFBCLKLOST_OUT : out std_logic;
199  GT0_CPLLLOCK_OUT : out std_logic;
200  GT0_CPLLLOCKDETCLK_IN : in std_logic;
201  GT0_CPLLREFCLKLOST_OUT : out std_logic;
202  GT0_CPLLRESET_IN : in std_logic;
203  -------------------------- Channel - Clocking Ports ------------------------
204  GT0_GTREFCLK0_IN : in std_logic;
205  ---------------------------- Channel - DRP Ports --------------------------
206  GT0_DRPADDR_IN : in std_logic_vector(8 downto 0);
207  GT0_DRPCLK_IN : in std_logic;
208  GT0_DRPDI_IN : in std_logic_vector(15 downto 0);
209  GT0_DRPDO_OUT : out std_logic_vector(15 downto 0);
210  GT0_DRPEN_IN : in std_logic;
211  GT0_DRPRDY_OUT : out std_logic;
212  GT0_DRPWE_IN : in std_logic;
213  --------------------- RX Initialization and Reset Ports --------------------
214  GT0_RXUSERRDY_IN : in std_logic;
215  -------------------------- RX Margin Analysis Ports ------------------------
216  GT0_EYESCANDATAERROR_OUT : out std_logic;
217  ------------------------- Receive Ports - CDR Ports ------------------------
218  GT0_RXCDRLOCK_OUT : out std_logic;
219  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
220  GT0_RXUSRCLK_IN : in std_logic;
221  GT0_RXUSRCLK2_IN : in std_logic;
222  ------------------ Receive Ports - FPGA RX interface Ports -----------------
223  GT0_RXDATA_OUT : out std_logic_vector(15 downto 0);
224  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
225  GT0_RXDISPERR_OUT : out std_logic_vector(1 downto 0);
226  GT0_RXNOTINTABLE_OUT : out std_logic_vector(1 downto 0);
227  --------------------------- Receive Ports - RX AFE -------------------------
228  GT0_GTXRXP_IN : in std_logic;
229  ------------------------ Receive Ports - RX AFE Ports ----------------------
230  GT0_GTXRXN_IN : in std_logic;
231  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
232  GT0_RXMCOMMAALIGNEN_IN : in std_logic;
233  GT0_RXPCOMMAALIGNEN_IN : in std_logic;
234  --------------------- Receive Ports - RX Equalizer Ports -------------------
235  GT0_RXDFELPMRESET_IN : in std_logic;
236  --------------------- Receive Ports - RX Equilizer Ports -------------------
237  GT0_RXLPMHFHOLD_IN : in std_logic;
238  GT0_RXLPMLFHOLD_IN : in std_logic;
239  --------------- Receive Ports - RX Fabric Output Control Ports -------------
240  GT0_RXOUTCLK_OUT : out std_logic;
241  ------------- Receive Ports - RX Initialization and Reset Ports ------------
242  GT0_GTRXRESET_IN : in std_logic;
243  GT0_RXPMARESET_IN : in std_logic;
244  ----------------- Receive Ports - RX Polarity Control Ports ----------------
245  GT0_RXPOLARITY_IN : in std_logic;
246  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
247  GT0_RXCHARISK_OUT : out std_logic_vector(1 downto 0);
248  -------------- Receive Ports -RX Initialization and Reset Ports ------------
249  GT0_RXRESETDONE_OUT : out std_logic;
250  --------------------- TX Initialization and Reset Ports --------------------
251  GT0_GTTXRESET_IN : in std_logic;
252  GT0_TXUSERRDY_IN : in std_logic;
253  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
254  GT0_TXUSRCLK_IN : in std_logic;
255  GT0_TXUSRCLK2_IN : in std_logic;
256  ------------------ Transmit Ports - TX Data Path interface -----------------
257  GT0_TXDATA_IN : in std_logic_vector(15 downto 0);
258  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
259  GT0_GTXTXN_OUT : out std_logic;
260  GT0_GTXTXP_OUT : out std_logic;
261  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
262  GT0_TXOUTCLK_OUT : out std_logic;
263  GT0_TXOUTCLKFABRIC_OUT : out std_logic;
264  GT0_TXOUTCLKPCS_OUT : out std_logic;
265  --------------------- Transmit Ports - TX Gearbox Ports --------------------
266  GT0_TXCHARISK_IN : in std_logic_vector(1 downto 0);
267  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
268  GT0_TXRESETDONE_OUT : out std_logic;
269  ----------------- Transmit Ports - TX Polarity Control Ports ---------------
270  GT0_TXPOLARITY_IN : in std_logic;
271 
272 
273  --____________________________COMMON PORTS________________________________
274  ---------------------- Common Block - Ref Clock Ports ---------------------
275  GT0_GTREFCLK0_COMMON_IN : in std_logic;
276  ------------------------- Common Block - QPLL Ports ------------------------
277  GT0_QPLLLOCK_OUT : out std_logic;
278  GT0_QPLLLOCKDETCLK_IN : in std_logic;
279  GT0_QPLLREFCLKLOST_OUT : out std_logic;
280  GT0_QPLLRESET_IN : in std_logic
281 
282 
283 );
284 end component;
285 
286 component S6Link_TX_STARTUP_FSM
287  Generic(
288  GT_TYPE : string := "GTX";
289  STABLE_CLOCK_PERIOD : integer range 4 to 20 := 8; --Period of the stable clock driving this state-machine, unit is [ns]
290  RETRY_COUNTER_BITWIDTH : integer range 2 to 8 := 8;
291  TX_QPLL_USED : boolean := False; -- the TX and RX Reset FSMs must
292  RX_QPLL_USED : boolean := False; -- share these two generic values
293  PHASE_ALIGNMENT_MANUAL : boolean := True -- Decision if a manual phase-alignment is necessary or the automatic
294  -- is enough. For single-lane applications the automatic alignment is
295  -- sufficient
296  );
297  Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB
298  --or reference-clock present at startup.
299  TXUSERCLK : in STD_LOGIC; --TXUSERCLK as used in the design
300  SOFT_RESET : in STD_LOGIC; --User Reset, can be pulled any time
301  QPLLREFCLKLOST : in STD_LOGIC; --QPLL Reference-clock for the GT is lost
302  CPLLREFCLKLOST : in STD_LOGIC; --CPLL Reference-clock for the GT is lost
303  QPLLLOCK : in STD_LOGIC; --Lock Detect from the QPLL of the GT
304  CPLLLOCK : in STD_LOGIC; --Lock Detect from the CPLL of the GT
305  TXRESETDONE : in STD_LOGIC;
306  MMCM_LOCK : in STD_LOGIC;
307  GTTXRESET : out STD_LOGIC:='0';
308  MMCM_RESET : out STD_LOGIC:='0';
309  QPLL_RESET : out STD_LOGIC:='0'; --Reset QPLL
310  CPLL_RESET : out STD_LOGIC:='0'; --Reset CPLL
311  TX_FSM_RESET_DONE : out STD_LOGIC:='0'; --Reset-sequence has sucessfully been finished.
312  TXUSERRDY : out STD_LOGIC:='0';
313  RUN_PHALIGNMENT : out STD_LOGIC:='0';
314  RESET_PHALIGNMENT : out STD_LOGIC:='0';
315  PHALIGNMENT_DONE : in STD_LOGIC;
316 
317  RETRY_COUNTER : out STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of
318  -- Retries it took to get the transceiver up and running
319  );
320 end component;
321 
322 component S6Link_RX_STARTUP_FSM
323  Generic(
324  EXAMPLE_SIMULATION : integer := 0;
325  EQ_MODE : string := "DFE";
326  GT_TYPE : string := "GTX";
327  STABLE_CLOCK_PERIOD : integer range 4 to 20 := 8; --Period of the stable clock driving this state-machine, unit is [ns]
328  RETRY_COUNTER_BITWIDTH : integer range 2 to 8 := 8;
329  TX_QPLL_USED : boolean := False; -- the TX and RX Reset FSMs must
330  RX_QPLL_USED : boolean := False; -- share these two generic values
331  PHASE_ALIGNMENT_MANUAL : boolean := True -- Decision if a manual phase-alignment is necessary or the automatic
332  -- is enough. For single-lane applications the automatic alignment is
333  -- sufficient
334  );
335  Port ( STABLE_CLOCK : in STD_LOGIC; --Stable Clock, either a stable clock from the PCB
336  --or reference-clock present at startup.
337  RXUSERCLK : in STD_LOGIC; --RXUSERCLK as used in the design
338  SOFT_RESET : in STD_LOGIC; --User Reset, can be pulled any time
339  QPLLREFCLKLOST : in STD_LOGIC; --QPLL Reference-clock for the GT is lost
340  CPLLREFCLKLOST : in STD_LOGIC; --CPLL Reference-clock for the GT is lost
341  QPLLLOCK : in STD_LOGIC; --Lock Detect from the QPLL of the GT
342  CPLLLOCK : in STD_LOGIC; --Lock Detect from the CPLL of the GT
343  RXRESETDONE : in STD_LOGIC;
344  MMCM_LOCK : in STD_LOGIC;
345  RECCLK_STABLE : in STD_LOGIC;
346  RECCLK_MONITOR_RESTART : in STD_LOGIC;
347  DATA_VALID : in STD_LOGIC;
348  TXUSERRDY : in STD_LOGIC; --TXUSERRDY from GT
349  GTRXRESET : out STD_LOGIC:='0';
350  MMCM_RESET : out STD_LOGIC:='0';
351  QPLL_RESET : out STD_LOGIC:='0'; --Reset QPLL (only if RX uses QPLL)
352  CPLL_RESET : out STD_LOGIC:='0'; --Reset CPLL (only if RX uses CPLL)
353  RX_FSM_RESET_DONE : out STD_LOGIC:='0'; --Reset-sequence has sucessfully been finished.
354  RXUSERRDY : out STD_LOGIC:='0';
355  RUN_PHALIGNMENT : out STD_LOGIC;
356  PHALIGNMENT_DONE : in STD_LOGIC;
357  RESET_PHALIGNMENT : out STD_LOGIC:='0';
358  RXDFEAGCHOLD : out STD_LOGIC;
359  RXDFELFHOLD : out STD_LOGIC;
360  RXLPMLFHOLD : out STD_LOGIC;
361  RXLPMHFHOLD : out STD_LOGIC;
362  RETRY_COUNTER : out STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of
363  -- Retries it took to get the transceiver up and running
364  );
365 end component;
366 
367 component S6Link_ADAPT_TOP_DFE is
368  generic (
369  AGC_TIMER : integer range 0 to 4095:= 150
370  );
371  port (
372  EN : in STD_LOGIC;
373  CTLE3_COMP_EN : in STD_LOGIC;
374  GTRXRESET : in STD_LOGIC;
375  RXPMARESET : in STD_LOGIC;
376  RXDFELPMRESET : in STD_LOGIC;
377  DCLK : in STD_LOGIC;
378  DO : in STD_LOGIC_VECTOR(15 downto 0);
379  DRDY : in STD_LOGIC;
380  DADDR : out STD_LOGIC_VECTOR(8 downto 0);
381  DI : out STD_LOGIC_VECTOR(15 downto 0);
382  DEN : out STD_LOGIC;
383  DWE : out STD_LOGIC;
384  RXMONITOR : in STD_LOGIC_VECTOR(6 downto 0);
385  RXMONITORSEL : out STD_LOGIC_VECTOR(1 downto 0);
386  AGCHOLD : out STD_LOGIC;
387  KLHOLD : out STD_LOGIC;
388  KHHOLD : out STD_LOGIC;
389  DONE : out STD_LOGIC;
390  DEBUG : out STD_LOGIC_VECTOR(53 downto 0)
391  );
392 end component;
393 
394 component S6Link_ADAPT_TOP_LPM is
395 generic (
396  TIMER : integer range 0 to 4095:= 150
397 );
398 port
399  (
400  EN : in STD_LOGIC;
401  GTRXRESET : in STD_LOGIC;
402  RXPMARESET : in STD_LOGIC;
403  RXDFELPMRESET : in STD_LOGIC;
404  --DRP
405  DCLK : in STD_LOGIC;
406  DO : in STD_LOGIC_VECTOR(15 downto 0);
407  DRDY : in STD_LOGIC;
408  DADDR : out STD_LOGIC_VECTOR(8 downto 0);
409  DI : out STD_LOGIC_VECTOR(15 downto 0);
410  DEN : out STD_LOGIC;
411  DWE : out STD_LOGIC;
412 
413  KLHOLD : out STD_LOGIC;
414  KHHOLD : out STD_LOGIC;
415  --DONE
416  DONE : out STD_LOGIC;
417  --Debug
418  DEBUG : out STD_LOGIC_VECTOR(53 downto 0)
419 );
420 end component;
421 
422 
423 
424 
425 
426 
427 
428  function get_cdrlock_time(is_sim : in integer) return integer is
429  variable lock_time: integer;
430  begin
431  if (is_sim = 1) then
432  lock_time := 1000;
433  else
434  lock_time := 50000 / integer(2.5); --Typical CDR lock time is 50,000UI as per DS183
435  end if;
436  return lock_time;
437  end function;
438 
439  function get_lpm_adapt_lock_time(is_sim : in integer) return integer is
440  variable lock_time: integer;
441  begin
442  if (is_sim = 1) then
443  lock_time := 5;
444  else
445  lock_time := integer(13 * integer(60) / integer(2.5)); --Typical CDR lock time is 50,000UI as per DS183
446  end if;
447  return lock_time;
448  end function;
449 
450 --***********************************Parameter Declarations********************
451 
452  constant DLY : time := 1 ns;
453  constant STABLE_CLOCK_PERIOD : integer := 20; --Period of the stable clock driving this state-machine, unit is [ns]
454  constant RX_CDRLOCK_TIME : integer := get_cdrlock_time(EXAMPLE_SIMULATION); -- 200us
455  constant WAIT_TIME_CDRLOCK : integer := RX_CDRLOCK_TIME / STABLE_CLOCK_PERIOD; -- 200 us time-out
456  constant LPM_ADAPT_LOCK_TIMER : integer := get_lpm_adapt_lock_time(EXAMPLE_SIMULATION);
457  constant DFE_ADAPT_LOCK_TIMER : integer := integer((13 * integer(60)) / integer(2.5));
458 
459  -------------------------- GT Wrapper Wires ------------------------------
460  signal gt0_cpllreset_i : std_logic;
461  signal gt0_cpllreset_t : std_logic;
462  signal gt0_cpllrefclklost_i : std_logic;
463  signal gt0_cplllock_i : std_logic;
464  signal gt0_txresetdone_i : std_logic;
465  signal gt0_rxresetdone_i : std_logic;
466  signal gt0_gttxreset_i : std_logic;
467  signal gt0_gttxreset_t : std_logic;
468  signal gt0_gtrxreset_i : std_logic;
469  signal gt0_gtrxreset_t : std_logic;
470  signal gt0_rxdfelpmreset_i : std_logic;
471  signal gt0_txuserrdy_i : std_logic;
472  signal gt0_txuserrdy_t : std_logic;
473  signal gt0_rxuserrdy_i : std_logic;
474  signal gt0_rxuserrdy_t : std_logic;
475 
476  signal gt0_rxdfeagchold_i : std_logic;
477  signal gt0_rxdfelfhold_i : std_logic;
478  signal gt0_rxlpmlfhold_i : std_logic;
479  signal gt0_rxlpmhfhold_i : std_logic;
480 
481 
482  signal gt0_drpaddr_i : std_logic_vector(8 downto 0);
483  signal gt0_drpdi_i : std_logic_vector(15 downto 0);
484  signal gt0_drpdo_o : std_logic_vector(15 downto 0);
485  signal gt0_drpen_i : std_logic;
486  signal gt0_drpwe_i : std_logic;
487  signal gt0_drprdy_o : std_logic;
488 
489  signal gt0_drpaddr_int : std_logic_vector(8 downto 0);
490  signal gt0_drpdi_int : std_logic_vector(15 downto 0);
491  signal gt0_drpdo_int : std_logic_vector(15 downto 0);
492  signal gt0_drpen_int : std_logic;
493  signal gt0_drpwe_int : std_logic;
494  signal gt0_drprdy_int : std_logic;
495 
496  signal gt0_rxmonitorout_o : std_logic_vector(6 downto 0);
497  signal gt0_rxmonitorsel_i : std_logic_vector(1 downto 0);
498  signal gt0_adapt_done : std_logic;
499 
500  signal gt0_qpllreset_i : std_logic;
501  signal gt0_qpllreset_t : std_logic;
502  signal gt0_qpllrefclklost_i : std_logic;
503  signal gt0_qplllock_i : std_logic;
504 
505 
506  ------------------------------- Global Signals -----------------------------
507  signal tied_to_ground_i : std_logic;
508  signal tied_to_vcc_i : std_logic;
509 
510  signal gt0_rxoutclk_i : std_logic;
511  signal gt0_recclk_stable_i : std_logic;
512 
513 
514 
515 
516 
517 
518  signal rx_cdrlock_counter : integer range 0 to WAIT_TIME_CDRLOCK:= 0 ;
519  signal rx_cdrlocked : std_logic;
520 
521 
522 
523 
524 
525 --**************************** Main Body of Code *******************************
526 begin
527  -- Static signal Assigments
528  tied_to_ground_i <= '0';
529  tied_to_vcc_i <= '1';
530 
531  ----------------------------- The GT Wrapper -----------------------------
532 
533  -- Use the instantiation template in the example directory to add the GT wrapper to your design.
534  -- In this example, the wrapper is wired up for basic operation with a frame generator and frame
535  -- checker. The GTs will reset, then attempt to align and transmit data. If channel bonding is
536  -- enabled, bonding should occur after alignment.
537 
538 
539  S6Link_i : S6Link
540  generic map
541  (
542  WRAPPER_SIM_GTRESET_SPEEDUP => EXAMPLE_SIM_GTRESET_SPEEDUP
543  )
544  port map
545  (
546 
547  --_____________________________________________________________________
548  --_____________________________________________________________________
549  --GT0 (X1Y15)
550 
551  --------------------------------- CPLL Ports -------------------------------
552  GT0_CPLLFBCLKLOST_OUT => GT0_CPLLFBCLKLOST_OUT ,
553  GT0_CPLLLOCK_OUT => gt0_cplllock_i,
554  GT0_CPLLLOCKDETCLK_IN => GT0_CPLLLOCKDETCLK_IN ,
555  GT0_CPLLREFCLKLOST_OUT => gt0_cpllrefclklost_i ,
556  GT0_CPLLRESET_IN => gt0_cpllreset_i,
557  -------------------------- Channel - Clocking Ports ------------------------
558  GT0_GTREFCLK0_IN => GT0_GTREFCLK0_IN,
559  ---------------------------- Channel - DRP Ports --------------------------
560  GT0_DRPADDR_IN => gt0_drpaddr_i,
561  GT0_DRPCLK_IN => GT0_DRPCLK_IN,
562  GT0_DRPDI_IN => gt0_drpdi_i,
563  GT0_DRPDO_OUT => gt0_drpdo_o,
564  GT0_DRPEN_IN => gt0_drpen_i,
565  GT0_DRPRDY_OUT => gt0_drprdy_o,
566  GT0_DRPWE_IN => gt0_drpwe_i,
567  --------------------- RX Initialization and Reset Ports --------------------
568  GT0_RXUSERRDY_IN => gt0_rxuserrdy_i,
569  -------------------------- RX Margin Analysis Ports ------------------------
570  GT0_EYESCANDATAERROR_OUT => GT0_EYESCANDATAERROR_OUT,
571  ------------------------- Receive Ports - CDR Ports ------------------------
572  GT0_RXCDRLOCK_OUT => GT0_RXCDRLOCK_OUT,
573  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
574  GT0_RXUSRCLK_IN => GT0_RXUSRCLK_IN,
575  GT0_RXUSRCLK2_IN => GT0_RXUSRCLK2_IN,
576  ------------------ Receive Ports - FPGA RX interface Ports -----------------
577  GT0_RXDATA_OUT => GT0_RXDATA_OUT,
578  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
579  GT0_RXDISPERR_OUT => GT0_RXDISPERR_OUT,
580  GT0_RXNOTINTABLE_OUT => GT0_RXNOTINTABLE_OUT ,
581  --------------------------- Receive Ports - RX AFE -------------------------
582  GT0_GTXRXP_IN => GT0_GTXRXP_IN,
583  ------------------------ Receive Ports - RX AFE Ports ----------------------
584  GT0_GTXRXN_IN => GT0_GTXRXN_IN,
585  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
586  GT0_RXMCOMMAALIGNEN_IN => GT0_RXMCOMMAALIGNEN_IN ,
587  GT0_RXPCOMMAALIGNEN_IN => GT0_RXPCOMMAALIGNEN_IN ,
588  --------------------- Receive Ports - RX Equalizer Ports -------------------
589  GT0_RXDFELPMRESET_IN => gt0_rxdfelpmreset_i ,
590  --------------------- Receive Ports - RX Equilizer Ports -------------------
591  GT0_RXLPMHFHOLD_IN => gt0_rxlpmhfhold_i,
592  GT0_RXLPMLFHOLD_IN => gt0_rxlpmlfhold_i,
593  --------------- Receive Ports - RX Fabric Output Control Ports -------------
594  GT0_RXOUTCLK_OUT => gt0_rxoutclk_i,
595  ------------- Receive Ports - RX Initialization and Reset Ports ------------
596  GT0_GTRXRESET_IN => gt0_gtrxreset_i,
597  GT0_RXPMARESET_IN => GT0_RXPMARESET_IN,
598  ----------------- Receive Ports - RX Polarity Control Ports ----------------
599  GT0_RXPOLARITY_IN => GT0_RXPOLARITY_IN,
600  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
601  GT0_RXCHARISK_OUT => GT0_RXCHARISK_OUT,
602  -------------- Receive Ports -RX Initialization and Reset Ports ------------
603  GT0_RXRESETDONE_OUT => gt0_rxresetdone_i,
604  --------------------- TX Initialization and Reset Ports --------------------
605  GT0_GTTXRESET_IN => gt0_gttxreset_i,
606  GT0_TXUSERRDY_IN => gt0_txuserrdy_i,
607  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
608  GT0_TXUSRCLK_IN => GT0_TXUSRCLK_IN,
609  GT0_TXUSRCLK2_IN => GT0_TXUSRCLK2_IN,
610  ------------------ Transmit Ports - TX Data Path interface -----------------
611  GT0_TXDATA_IN => GT0_TXDATA_IN,
612  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
613  GT0_GTXTXN_OUT => GT0_GTXTXN_OUT,
614  GT0_GTXTXP_OUT => GT0_GTXTXP_OUT,
615  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
616  GT0_TXOUTCLK_OUT => GT0_TXOUTCLK_OUT,
617  GT0_TXOUTCLKFABRIC_OUT => GT0_TXOUTCLKFABRIC_OUT ,
618  GT0_TXOUTCLKPCS_OUT => GT0_TXOUTCLKPCS_OUT ,
619  --------------------- Transmit Ports - TX Gearbox Ports --------------------
620  GT0_TXCHARISK_IN => GT0_TXCHARISK_IN,
621  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
622  GT0_TXRESETDONE_OUT => gt0_txresetdone_i,
623  ----------------- Transmit Ports - TX Polarity Control Ports ---------------
624  GT0_TXPOLARITY_IN => GT0_TXPOLARITY_IN,
625 
626 
627 
628 
629  --____________________________COMMON PORTS________________________________
630  ---------------------- Common Block - Ref Clock Ports ---------------------
631  GT0_GTREFCLK0_COMMON_IN => GT0_GTREFCLK0_COMMON_IN ,
632  ------------------------- Common Block - QPLL Ports ------------------------
633  GT0_QPLLLOCK_OUT => gt0_qplllock_i,
634  GT0_QPLLLOCKDETCLK_IN => GT0_QPLLLOCKDETCLK_IN ,
635  GT0_QPLLREFCLKLOST_OUT => gt0_qpllrefclklost_i ,
636  GT0_QPLLRESET_IN => gt0_qpllreset_i
637 
638  );
639 
640 
641  gt0_rxdfelpmreset_i <= tied_to_ground_i;
642 
643 
644 
645 
646  GT0_CPLLLOCK_OUT <= gt0_cplllock_i;
647  GT0_TXRESETDONE_OUT <= gt0_txresetdone_i;
648  GT0_RXRESETDONE_OUT <= gt0_rxresetdone_i;
649  GT0_QPLLLOCK_OUT <= gt0_qplllock_i;
650 
651 chipscope : if EXAMPLE_USE_CHIPSCOPE = 1 generate
652  gt0_cpllreset_i <= GT0_CPLLRESET_IN;
653  gt0_gttxreset_i <= GT0_GTTXRESET_IN;
654  gt0_gtrxreset_i <= GT0_GTRXRESET_IN;
655  gt0_txuserrdy_i <= GT0_TXUSERRDY_IN;
656  gt0_rxuserrdy_i <= GT0_RXUSERRDY_IN;
657  gt0_qpllreset_i <= GT0_QPLLRESET_IN;
658 end generate chipscope;
659 
660 no_chipscope : if EXAMPLE_USE_CHIPSCOPE = 0 generate
661  gt0_cpllreset_i <= gt0_cpllreset_t ;
662  gt0_cpllreset_i <= gt0_cpllreset_t;
663  gt0_gttxreset_i <= gt0_gttxreset_t;
664  gt0_gtrxreset_i <= gt0_gtrxreset_t;
665  gt0_txuserrdy_i <= gt0_txuserrdy_t;
666  gt0_rxuserrdy_i <= gt0_rxuserrdy_t;
667  gt0_qpllreset_i <= gt0_qpllreset_t;
668 end generate no_chipscope;
669 
670 
671 gt0_txresetfsm_i: S6Link_TX_STARTUP_FSM
672 
673  generic map(
674  GT_TYPE => "GTX", --GTX or GTH or GTP
675  STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, -- Period of the stable clock driving this state-machine, unit is [ns]
676  RETRY_COUNTER_BITWIDTH => 8,
677  TX_QPLL_USED => FALSE , -- the TX and RX Reset FSMs must
678  RX_QPLL_USED => FALSE, -- share these two generic values
679  PHASE_ALIGNMENT_MANUAL => FALSE -- Decision if a manual phase-alignment is necessary or the automatic
680  -- is enough. For single-lane applications the automatic alignment is
681  -- sufficient
682  )
683  port map (
684  STABLE_CLOCK => SYSCLK_IN ,
685  TXUSERCLK => GT0_TXUSRCLK_IN,
686  SOFT_RESET => SOFT_RESET_IN,
687  QPLLREFCLKLOST => tied_to_ground_i,
688  CPLLREFCLKLOST => gt0_cpllrefclklost_i ,
689  QPLLLOCK => tied_to_vcc_i,
690  CPLLLOCK => gt0_cplllock_i,
691  TXRESETDONE => gt0_txresetdone_i,
692  MMCM_LOCK => tied_to_vcc_i,
693  GTTXRESET => gt0_gttxreset_t,
694  MMCM_RESET => open,
695  QPLL_RESET => open,
696  CPLL_RESET => gt0_cpllreset_t,
697  TX_FSM_RESET_DONE => GT0_TX_FSM_RESET_DONE_OUT ,
698  TXUSERRDY => gt0_txuserrdy_t,
699  RUN_PHALIGNMENT => open,
700  RESET_PHALIGNMENT => open,
701  PHALIGNMENT_DONE => tied_to_vcc_i,
702  RETRY_COUNTER => open
703  );
704 
705 
706 
707 
708 
709 
710 gt0_rxresetfsm_i: S6Link_RX_STARTUP_FSM
711 
712  generic map(
713  EXAMPLE_SIMULATION => EXAMPLE_SIMULATION,
714  GT_TYPE => "GTX", --GTX or GTH or GTP
715  EQ_MODE => EQ_MODE, --Rx Equalization Mode - Set to DFE or LPM
716  STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD, --Period of the stable clock driving this state-machine, unit is [ns]
717  RETRY_COUNTER_BITWIDTH => 8,
718  TX_QPLL_USED => FALSE , -- the TX and RX Reset FSMs must
719  RX_QPLL_USED => FALSE, -- share these two generic values
720  PHASE_ALIGNMENT_MANUAL => FALSE -- Decision if a manual phase-alignment is necessary or the automatic
721  -- is enough. For single-lane applications the automatic alignment is
722  -- sufficient
723  )
724  port map (
725  STABLE_CLOCK => SYSCLK_IN ,
726  RXUSERCLK => GT0_RXUSRCLK_IN,
727  SOFT_RESET => SOFT_RESET_IN,
728  QPLLREFCLKLOST => tied_to_ground_i,
729  CPLLREFCLKLOST => gt0_cpllrefclklost_i ,
730  QPLLLOCK => tied_to_vcc_i,
731  CPLLLOCK => gt0_cplllock_i,
732  RXRESETDONE => gt0_rxresetdone_i,
733  MMCM_LOCK => tied_to_vcc_i,
734  RECCLK_STABLE => gt0_recclk_stable_i ,
735  RECCLK_MONITOR_RESTART => tied_to_ground_i,
736  DATA_VALID => GT0_DATA_VALID_IN,
737  TXUSERRDY => gt0_txuserrdy_i,
738  GTRXRESET => gt0_gtrxreset_t,
739  MMCM_RESET => open,
740  QPLL_RESET => open,
741  CPLL_RESET => open,
742  RX_FSM_RESET_DONE => GT0_RX_FSM_RESET_DONE_OUT ,
743  RXUSERRDY => gt0_rxuserrdy_t,
744  RUN_PHALIGNMENT => open,
745  RESET_PHALIGNMENT => open,
746  PHALIGNMENT_DONE => tied_to_vcc_i,
747  RXDFELFHOLD => gt0_rxdfelfhold_i,
748  RXLPMLFHOLD => gt0_rxlpmlfhold_i,
749  RXLPMHFHOLD => gt0_rxlpmhfhold_i,
750  RXDFEAGCHOLD => open,
751  RETRY_COUNTER => open
752  );
753 
754 gt0_eq_dfe_mode: if EQ_MODE = "DFE" generate
755 gt0_adapt_top_dfe_i: S6Link_ADAPT_TOP_DFE
756  generic map (
757  AGC_TIMER => DFE_ADAPT_LOCK_TIMER
758  )
759  port map (
760  EN => '1',
761  CTLE3_COMP_EN => '1',
762  GTRXRESET => gt0_gtrxreset_i, --reset going to the GT, coming from either chipscope or TB
763  RXPMARESET => GT0_RXPMARESET_IN,--tied to ground, going to GT
764  RXDFELPMRESET => gt0_rxdfelpmreset_i,--tied to ground, going to GT
765  DCLK => GT0_DRPCLK_IN,
766  DO => gt0_drpdo_int,
767  DRDY => gt0_drprdy_int,
768  DADDR => gt0_drpaddr_int,
769  DI => gt0_drpdi_int,
770  DEN => gt0_drpen_int,
771  DWE => gt0_drpwe_int,
772  RXMONITOR => gt0_rxmonitorout_o,
773  RXMONITORSEL => gt0_rxmonitorsel_i,
774  AGCHOLD => gt0_rxdfeagchold_i,
775  KLHOLD => open,
776  KHHOLD => open,
777  DONE => gt0_adapt_done,
778  DEBUG => open
779  );
780 
781 end generate gt0_eq_dfe_mode;
782 
783 gt0_eq_lpm_mode: if EQ_MODE = "LPM" generate
784 gt0_adapt_top_lpm_i: S6Link_ADAPT_TOP_LPM
785  generic map (
786  TIMER => LPM_ADAPT_LOCK_TIMER
787  )
788  port map (
789  EN => '1',
790  GTRXRESET => gt0_gtrxreset_i, --reset going to the GT, coming from either chipscope or TB
791  RXPMARESET => GT0_RXPMARESET_IN,--tied to ground, going to GT
792  RXDFELPMRESET => gt0_rxdfelpmreset_i,--tied to ground, going to GT
793  DCLK => GT0_DRPCLK_IN,
794  DO => gt0_drpdo_int,
795  DRDY => gt0_drprdy_int,
796  DADDR => gt0_drpaddr_int,
797  DI => gt0_drpdi_int,
798  DEN => gt0_drpen_int,
799  DWE => gt0_drpwe_int,
800  KLHOLD => open,
801  KHHOLD => open,
802  DONE => gt0_adapt_done,
803  DEBUG => open
804  );
805 
806 end generate gt0_eq_lpm_mode;
807 
808  gt0_drpaddr_i <= GT0_DRPADDR_IN when (gt0_adapt_done='1') else gt0_drpaddr_int;
809  gt0_drpdi_i <= GT0_DRPDI_IN when (gt0_adapt_done='1') else gt0_drpdi_int;
810  gt0_drpen_i <= GT0_DRPEN_IN when (gt0_adapt_done='1') else gt0_drpen_int;
811  gt0_drpwe_i <= GT0_DRPWE_IN when (gt0_adapt_done='1') else gt0_drpwe_int;
812  GT0_DRPDO_OUT <= gt0_drpdo_o when (gt0_adapt_done='1') else "0000000000000000";
813  GT0_DRPRDY_OUT <= gt0_drprdy_o when (gt0_adapt_done='1') else '0';
814 
815  gt0_drpdo_int <= gt0_drpdo_o;
816  gt0_drprdy_int <= gt0_drprdy_o;
817 
818 
819 
820 
821  cdrlock_timeout:process(SYSCLK_IN)
822  begin
823  if rising_edge(SYSCLK_IN) then
824  if(gt0_gtrxreset_i = '1') then
825  rx_cdrlocked <= '0';
826  rx_cdrlock_counter <= 0 after DLY;
827  elsif (rx_cdrlock_counter = WAIT_TIME_CDRLOCK) then
828  rx_cdrlocked <= '1';
829  rx_cdrlock_counter <= rx_cdrlock_counter after DLY;
830  else
831  rx_cdrlock_counter <= rx_cdrlock_counter + 1 after DLY;
832  end if;
833  end if;
834  end process;
835 
836 gt0_recclk_stable_i <= rx_cdrlocked;
837 
838 
839 
840 
841 
842 
843 
844 end RTL;
845 
846 
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