AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
 All Classes Variables
my_sfp3_v2_7.vhd
1 -------------------------------------------------------------------------------
2 -- ____ ____
3 -- / /\/ /
4 -- /___/ \ / Vendor: Xilinx
5 -- \ \ \/ Version : 2.7
6 -- \ \ Application : 7 Series FPGAs Transceivers Wizard
7 -- / / Filename : sfp3_v2_7.vhd
8 -- /___/ /\
9 -- \ \ / \
10 -- \___\/\___\
11 --
12 --
13 -- Module SFP3_v2_7 (a GT Wrapper)
14 -- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
15 --
16 --
17 -- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
18 --
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62 
63 
64 library ieee;
65 use ieee.std_logic_1164.all;
66 use ieee.numeric_std.all;
67 use work.amc13_pack.all;
68 library UNISIM;
69 use UNISIM.VCOMPONENTS.ALL;
70 
71 
72 --***************************** Entity Declaration ****************************
73 
74 entity SFP3_v2_7 is
75 generic
76 (
77  QPLL_FBDIV_TOP : integer := 66;
78 
79  -- Simulation attributes
80  WRAPPER_SIM_GTRESET_SPEEDUP : string := "FALSE"; -- Set to "true" to speed up sim reset
81  RX_DFE_KL_CFG2_IN : bit_vector := X"301148AC";
82  PMA_RSV_IN : bit_vector := x"001E7080"
83 
84 );
85 port
86 (
87  --_________________________________________________________________________
88  --_________________________________________________________________________
89  --GT0 (X0Y12)
90  --____________________________CHANNEL PORTS________________________________
91  ---------------------------- Channel - DRP Ports --------------------------
92  GT0_DRPADDR_IN : in std_logic_vector(8 downto 0);
93  GT0_DRPCLK_IN : in std_logic;
94  GT0_DRPDI_IN : in std_logic_vector(15 downto 0);
95  GT0_DRPDO_OUT : out std_logic_vector(15 downto 0);
96  GT0_DRPEN_IN : in std_logic;
97  GT0_DRPRDY_OUT : out std_logic;
98  GT0_DRPWE_IN : in std_logic;
99  ------------------------------- Loopback Ports -----------------------------
100  GT0_LOOPBACK_IN : in std_logic_vector(2 downto 0);
101  ------------------------------ Power-Down Ports ----------------------------
102  GT0_RXPD_IN : in std_logic_vector(1 downto 0);
103  GT0_TXPD_IN : in std_logic_vector(1 downto 0);
104  --------------------- RX Initialization and Reset Ports --------------------
105  GT0_RXUSERRDY_IN : in std_logic;
106  -------------------------- RX Margin Analysis Ports ------------------------
107  GT0_EYESCANDATAERROR_OUT : out std_logic;
108  ------------------------- Receive Ports - CDR Ports ------------------------
109  GT0_RXCDRLOCK_OUT : out std_logic;
110  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
111  GT0_RXUSRCLK_IN : in std_logic;
112  GT0_RXUSRCLK2_IN : in std_logic;
113  ------------------ Receive Ports - FPGA RX interface Ports -----------------
114  GT0_RXDATA_OUT : out std_logic_vector(31 downto 0);
115  ------------------- Receive Ports - Pattern Checker Ports ------------------
116  GT0_RXPRBSERR_OUT : out std_logic;
117  GT0_RXPRBSSEL_IN : in std_logic_vector(2 downto 0);
118  ------------------- Receive Ports - Pattern Checker ports ------------------
119  GT0_RXPRBSCNTRESET_IN : in std_logic;
120  --------------------------- Receive Ports - RX AFE -------------------------
121  GT0_GTXRXP_IN : in std_logic;
122  ------------------------ Receive Ports - RX AFE Ports ----------------------
123  GT0_GTXRXN_IN : in std_logic;
124  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
125  GT0_RXBUFRESET_IN : in std_logic;
126  GT0_RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
127  --------------------- Receive Ports - RX Equalizer Ports -------------------
128  GT0_RXDFEAGCHOLD_IN : in std_logic;
129  GT0_RXDFELFHOLD_IN : in std_logic;
130  --------------- Receive Ports - RX Fabric Output Control Ports -------------
131  GT0_RXOUTCLK_OUT : out std_logic;
132  ---------------------- Receive Ports - RX Gearbox Ports --------------------
133  GT0_RXDATAVALID_OUT : out std_logic;
134  GT0_RXHEADER_OUT : out std_logic_vector(1 downto 0);
135  GT0_RXHEADERVALID_OUT : out std_logic;
136  --------------------- Receive Ports - RX Gearbox Ports --------------------
137  GT0_RXGEARBOXSLIP_IN : in std_logic;
138  ------------- Receive Ports - RX Initialization and Reset Ports ------------
139  GT0_GTRXRESET_IN : in std_logic;
140  GT0_RXPCSRESET_IN : in std_logic;
141  GT0_RXPMARESET_IN : in std_logic;
142  ------------------ Receive Ports - RX Margin Analysis ports ----------------
143  GT0_RXLPMEN_IN : in std_logic;
144  -------------- Receive Ports -RX Initialization and Reset Ports ------------
145  GT0_RXRESETDONE_OUT : out std_logic;
146  --------------------- TX Initialization and Reset Ports --------------------
147  GT0_GTTXRESET_IN : in std_logic;
148  GT0_TXUSERRDY_IN : in std_logic;
149  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
150  GT0_TXUSRCLK_IN : in std_logic;
151  GT0_TXUSRCLK2_IN : in std_logic;
152  --------------- Transmit Ports - TX Configurable Driver Ports --------------
153  GT0_TXDIFFCTRL_IN : in std_logic_vector(3 downto 0);
154  GT0_TXINHIBIT_IN : in std_logic;
155  GT0_TXMAINCURSOR_IN : in std_logic_vector(6 downto 0);
156  ------------------ Transmit Ports - TX Data Path interface -----------------
157  GT0_TXDATA_IN : in std_logic_vector(31 downto 0);
158  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
159  GT0_GTXTXN_OUT : out std_logic;
160  GT0_GTXTXP_OUT : out std_logic;
161  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
162  GT0_TXOUTCLK_OUT : out std_logic;
163  GT0_TXOUTCLKFABRIC_OUT : out std_logic;
164  GT0_TXOUTCLKPCS_OUT : out std_logic;
165  --------------------- Transmit Ports - TX Gearbox Ports --------------------
166  GT0_TXHEADER_IN : in std_logic_vector(1 downto 0);
167  GT0_TXSEQUENCE_IN : in std_logic_vector(6 downto 0);
168  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
169  GT0_TXPCSRESET_IN : in std_logic;
170  GT0_TXRESETDONE_OUT : out std_logic;
171  ------------------ Transmit Ports - pattern Generator Ports ----------------
172  GT0_TXPRBSSEL_IN : in std_logic_vector(2 downto 0);
173 
174  --GT1 (X0Y13)
175  --____________________________CHANNEL PORTS________________________________
176  ---------------------------- Channel - DRP Ports --------------------------
177  GT1_DRPADDR_IN : in std_logic_vector(8 downto 0);
178  GT1_DRPCLK_IN : in std_logic;
179  GT1_DRPDI_IN : in std_logic_vector(15 downto 0);
180  GT1_DRPDO_OUT : out std_logic_vector(15 downto 0);
181  GT1_DRPEN_IN : in std_logic;
182  GT1_DRPRDY_OUT : out std_logic;
183  GT1_DRPWE_IN : in std_logic;
184  ------------------------------- Loopback Ports -----------------------------
185  GT1_LOOPBACK_IN : in std_logic_vector(2 downto 0);
186  ------------------------------ Power-Down Ports ----------------------------
187  GT1_RXPD_IN : in std_logic_vector(1 downto 0);
188  GT1_TXPD_IN : in std_logic_vector(1 downto 0);
189  --------------------- RX Initialization and Reset Ports --------------------
190  GT1_RXUSERRDY_IN : in std_logic;
191  -------------------------- RX Margin Analysis Ports ------------------------
192  GT1_EYESCANDATAERROR_OUT : out std_logic;
193  ------------------------- Receive Ports - CDR Ports ------------------------
194  GT1_RXCDRLOCK_OUT : out std_logic;
195  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
196  GT1_RXUSRCLK_IN : in std_logic;
197  GT1_RXUSRCLK2_IN : in std_logic;
198  ------------------ Receive Ports - FPGA RX interface Ports -----------------
199  GT1_RXDATA_OUT : out std_logic_vector(31 downto 0);
200  ------------------- Receive Ports - Pattern Checker Ports ------------------
201  GT1_RXPRBSERR_OUT : out std_logic;
202  GT1_RXPRBSSEL_IN : in std_logic_vector(2 downto 0);
203  ------------------- Receive Ports - Pattern Checker ports ------------------
204  GT1_RXPRBSCNTRESET_IN : in std_logic;
205  --------------------------- Receive Ports - RX AFE -------------------------
206  GT1_GTXRXP_IN : in std_logic;
207  ------------------------ Receive Ports - RX AFE Ports ----------------------
208  GT1_GTXRXN_IN : in std_logic;
209  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
210  GT1_RXBUFRESET_IN : in std_logic;
211  GT1_RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
212  --------------------- Receive Ports - RX Equalizer Ports -------------------
213  GT1_RXDFEAGCHOLD_IN : in std_logic;
214  GT1_RXDFELFHOLD_IN : in std_logic;
215  --------------- Receive Ports - RX Fabric Output Control Ports -------------
216  GT1_RXOUTCLK_OUT : out std_logic;
217  ---------------------- Receive Ports - RX Gearbox Ports --------------------
218  GT1_RXDATAVALID_OUT : out std_logic;
219  GT1_RXHEADER_OUT : out std_logic_vector(1 downto 0);
220  GT1_RXHEADERVALID_OUT : out std_logic;
221  --------------------- Receive Ports - RX Gearbox Ports --------------------
222  GT1_RXGEARBOXSLIP_IN : in std_logic;
223  ------------- Receive Ports - RX Initialization and Reset Ports ------------
224  GT1_GTRXRESET_IN : in std_logic;
225  GT1_RXPCSRESET_IN : in std_logic;
226  GT1_RXPMARESET_IN : in std_logic;
227  ------------------ Receive Ports - RX Margin Analysis ports ----------------
228  GT1_RXLPMEN_IN : in std_logic;
229  -------------- Receive Ports -RX Initialization and Reset Ports ------------
230  GT1_RXRESETDONE_OUT : out std_logic;
231  --------------------- TX Initialization and Reset Ports --------------------
232  GT1_GTTXRESET_IN : in std_logic;
233  GT1_TXUSERRDY_IN : in std_logic;
234  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
235  GT1_TXUSRCLK_IN : in std_logic;
236  GT1_TXUSRCLK2_IN : in std_logic;
237  --------------- Transmit Ports - TX Configurable Driver Ports --------------
238  GT1_TXDIFFCTRL_IN : in std_logic_vector(3 downto 0);
239  GT1_TXINHIBIT_IN : in std_logic;
240  GT1_TXMAINCURSOR_IN : in std_logic_vector(6 downto 0);
241  ------------------ Transmit Ports - TX Data Path interface -----------------
242  GT1_TXDATA_IN : in std_logic_vector(31 downto 0);
243  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
244  GT1_GTXTXN_OUT : out std_logic;
245  GT1_GTXTXP_OUT : out std_logic;
246  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
247  GT1_TXOUTCLK_OUT : out std_logic;
248  GT1_TXOUTCLKFABRIC_OUT : out std_logic;
249  GT1_TXOUTCLKPCS_OUT : out std_logic;
250  --------------------- Transmit Ports - TX Gearbox Ports --------------------
251  GT1_TXHEADER_IN : in std_logic_vector(1 downto 0);
252  GT1_TXSEQUENCE_IN : in std_logic_vector(6 downto 0);
253  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
254  GT1_TXPCSRESET_IN : in std_logic;
255  GT1_TXRESETDONE_OUT : out std_logic;
256  ------------------ Transmit Ports - pattern Generator Ports ----------------
257  GT1_TXPRBSSEL_IN : in std_logic_vector(2 downto 0);
258 
259  --GT2 (X0Y14)
260  --____________________________CHANNEL PORTS________________________________
261  ---------------------------- Channel - DRP Ports --------------------------
262  GT2_DRPADDR_IN : in std_logic_vector(8 downto 0);
263  GT2_DRPCLK_IN : in std_logic;
264  GT2_DRPDI_IN : in std_logic_vector(15 downto 0);
265  GT2_DRPDO_OUT : out std_logic_vector(15 downto 0);
266  GT2_DRPEN_IN : in std_logic;
267  GT2_DRPRDY_OUT : out std_logic;
268  GT2_DRPWE_IN : in std_logic;
269  ------------------------------- Loopback Ports -----------------------------
270  GT2_LOOPBACK_IN : in std_logic_vector(2 downto 0);
271  ------------------------------ Power-Down Ports ----------------------------
272  GT2_RXPD_IN : in std_logic_vector(1 downto 0);
273  GT2_TXPD_IN : in std_logic_vector(1 downto 0);
274  --------------------- RX Initialization and Reset Ports --------------------
275  GT2_RXUSERRDY_IN : in std_logic;
276  -------------------------- RX Margin Analysis Ports ------------------------
277  GT2_EYESCANDATAERROR_OUT : out std_logic;
278  ------------------------- Receive Ports - CDR Ports ------------------------
279  GT2_RXCDRLOCK_OUT : out std_logic;
280  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
281  GT2_RXUSRCLK_IN : in std_logic;
282  GT2_RXUSRCLK2_IN : in std_logic;
283  ------------------ Receive Ports - FPGA RX interface Ports -----------------
284  GT2_RXDATA_OUT : out std_logic_vector(31 downto 0);
285  ------------------- Receive Ports - Pattern Checker Ports ------------------
286  GT2_RXPRBSERR_OUT : out std_logic;
287  GT2_RXPRBSSEL_IN : in std_logic_vector(2 downto 0);
288  ------------------- Receive Ports - Pattern Checker ports ------------------
289  GT2_RXPRBSCNTRESET_IN : in std_logic;
290  --------------------------- Receive Ports - RX AFE -------------------------
291  GT2_GTXRXP_IN : in std_logic;
292  ------------------------ Receive Ports - RX AFE Ports ----------------------
293  GT2_GTXRXN_IN : in std_logic;
294  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
295  GT2_RXBUFRESET_IN : in std_logic;
296  GT2_RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
297  --------------------- Receive Ports - RX Equalizer Ports -------------------
298  GT2_RXDFEAGCHOLD_IN : in std_logic;
299  GT2_RXDFELFHOLD_IN : in std_logic;
300  --------------- Receive Ports - RX Fabric Output Control Ports -------------
301  GT2_RXOUTCLK_OUT : out std_logic;
302  ---------------------- Receive Ports - RX Gearbox Ports --------------------
303  GT2_RXDATAVALID_OUT : out std_logic;
304  GT2_RXHEADER_OUT : out std_logic_vector(1 downto 0);
305  GT2_RXHEADERVALID_OUT : out std_logic;
306  --------------------- Receive Ports - RX Gearbox Ports --------------------
307  GT2_RXGEARBOXSLIP_IN : in std_logic;
308  ------------- Receive Ports - RX Initialization and Reset Ports ------------
309  GT2_GTRXRESET_IN : in std_logic;
310  GT2_RXPCSRESET_IN : in std_logic;
311  GT2_RXPMARESET_IN : in std_logic;
312  ------------------ Receive Ports - RX Margin Analysis ports ----------------
313  GT2_RXLPMEN_IN : in std_logic;
314  -------------- Receive Ports -RX Initialization and Reset Ports ------------
315  GT2_RXRESETDONE_OUT : out std_logic;
316  --------------------- TX Initialization and Reset Ports --------------------
317  GT2_GTTXRESET_IN : in std_logic;
318  GT2_TXUSERRDY_IN : in std_logic;
319  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
320  GT2_TXUSRCLK_IN : in std_logic;
321  GT2_TXUSRCLK2_IN : in std_logic;
322  --------------- Transmit Ports - TX Configurable Driver Ports --------------
323  GT2_TXDIFFCTRL_IN : in std_logic_vector(3 downto 0);
324  GT2_TXINHIBIT_IN : in std_logic;
325  GT2_TXMAINCURSOR_IN : in std_logic_vector(6 downto 0);
326  ------------------ Transmit Ports - TX Data Path interface -----------------
327  GT2_TXDATA_IN : in std_logic_vector(31 downto 0);
328  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
329  GT2_GTXTXN_OUT : out std_logic;
330  GT2_GTXTXP_OUT : out std_logic;
331  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
332  GT2_TXOUTCLK_OUT : out std_logic;
333  GT2_TXOUTCLKFABRIC_OUT : out std_logic;
334  GT2_TXOUTCLKPCS_OUT : out std_logic;
335  --------------------- Transmit Ports - TX Gearbox Ports --------------------
336  GT2_TXHEADER_IN : in std_logic_vector(1 downto 0);
337  GT2_TXSEQUENCE_IN : in std_logic_vector(6 downto 0);
338  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
339  GT2_TXPCSRESET_IN : in std_logic;
340  GT2_TXRESETDONE_OUT : out std_logic;
341  ------------------ Transmit Ports - pattern Generator Ports ----------------
342  GT2_TXPRBSSEL_IN : in std_logic_vector(2 downto 0);
343 
344 
345  --____________________________COMMON PORTS________________________________
346  ---------------------- Common Block - Ref Clock Ports ---------------------
347  GT0_GTREFCLK0_COMMON_IN : in std_logic;
348  ------------------------- Common Block - QPLL Ports ------------------------
349  GT0_QPLLLOCK_OUT : out std_logic;
350  GT0_QPLLLOCKDETCLK_IN : in std_logic;
351  GT0_QPLLREFCLKLOST_OUT : out std_logic;
352  GT0_QPLLRESET_IN : in std_logic
353 
354 
355 );
356 
357 
358 end SFP3_v2_7;
359 
360 architecture RTL of SFP3_v2_7 is
361 
362  attribute CORE_GENERATION_INFO : string;
363  attribute CORE_GENERATION_INFO of RTL : architecture is "SFP3_v2_7,gtwizard_v2_7,{protocol_file=10GBASE-R}";
364 
365 
366 --***********************************Parameter Declarations********************
367 
368  constant DLY : time := 1 ns;
369 
370 --***************************** Signal Declarations *****************************
371 
372  -- ground and tied_to_vcc_i signals
373  signal tied_to_ground_i : std_logic;
374  signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
375  signal tied_to_vcc_i : std_logic;
376  signal gt0_qplloutclk_i : std_logic;
377  signal gt0_qplloutrefclk_i : std_logic;
378 
379 
380  signal gt0_mgtrefclktx_i : std_logic_vector(1 downto 0);
381  signal gt0_mgtrefclkrx_i : std_logic_vector(1 downto 0);
382 
383  signal gt1_mgtrefclktx_i : std_logic_vector(1 downto 0);
384  signal gt1_mgtrefclkrx_i : std_logic_vector(1 downto 0);
385 
386  signal gt2_mgtrefclktx_i : std_logic_vector(1 downto 0);
387  signal gt2_mgtrefclkrx_i : std_logic_vector(1 downto 0);
388 
389 
390  signal gt0_qpllclk_i : std_logic;
391  signal gt0_qpllrefclk_i : std_logic;
392  signal gt1_qpllclk_i : std_logic;
393  signal gt1_qpllrefclk_i : std_logic;
394  signal gt2_qpllclk_i : std_logic;
395  signal gt2_qpllrefclk_i : std_logic;
396 
397 
398 --*************************** Component Declarations **************************
399 component SFP3_v2_7_GT
400 generic
401 (
402  -- Simulation attributes
403  GT_SIM_GTRESET_SPEEDUP : string := "FALSE";
404  RX_DFE_KL_CFG2_IN : bit_vector := X"3010D90C";
405  PMA_RSV_IN : bit_vector := X"00000000";
406  PCS_RSVD_ATTR_IN : bit_vector := X"000000000000"
407 );
408 port
409 (
410  ---------------------------- Channel - DRP Ports --------------------------
411  DRPADDR_IN : in std_logic_vector(8 downto 0);
412  DRPCLK_IN : in std_logic;
413  DRPDI_IN : in std_logic_vector(15 downto 0);
414  DRPDO_OUT : out std_logic_vector(15 downto 0);
415  DRPEN_IN : in std_logic;
416  DRPRDY_OUT : out std_logic;
417  DRPWE_IN : in std_logic;
418  ------------------------------- Clocking Ports -----------------------------
419  QPLLCLK_IN : in std_logic;
420  QPLLREFCLK_IN : in std_logic;
421  ------------------------------- Loopback Ports -----------------------------
422  LOOPBACK_IN : in std_logic_vector(2 downto 0);
423  ------------------------------ Power-Down Ports ----------------------------
424  RXPD_IN : in std_logic_vector(1 downto 0);
425  TXPD_IN : in std_logic_vector(1 downto 0);
426  --------------------- RX Initialization and Reset Ports --------------------
427  RXUSERRDY_IN : in std_logic;
428  -------------------------- RX Margin Analysis Ports ------------------------
429  EYESCANDATAERROR_OUT : out std_logic;
430  ------------------------- Receive Ports - CDR Ports ------------------------
431  RXCDRLOCK_OUT : out std_logic;
432  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
433  RXUSRCLK_IN : in std_logic;
434  RXUSRCLK2_IN : in std_logic;
435  ------------------ Receive Ports - FPGA RX interface Ports -----------------
436  RXDATA_OUT : out std_logic_vector(31 downto 0);
437  ------------------- Receive Ports - Pattern Checker Ports ------------------
438  RXPRBSERR_OUT : out std_logic;
439  RXPRBSSEL_IN : in std_logic_vector(2 downto 0);
440  ------------------- Receive Ports - Pattern Checker ports ------------------
441  RXPRBSCNTRESET_IN : in std_logic;
442  --------------------------- Receive Ports - RX AFE -------------------------
443  GTXRXP_IN : in std_logic;
444  ------------------------ Receive Ports - RX AFE Ports ----------------------
445  GTXRXN_IN : in std_logic;
446  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
447  RXBUFRESET_IN : in std_logic;
448  RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
449  --------------------- Receive Ports - RX Equalizer Ports -------------------
450  RXDFEAGCHOLD_IN : in std_logic;
451  RXDFELFHOLD_IN : in std_logic;
452  --------------- Receive Ports - RX Fabric Output Control Ports -------------
453  RXOUTCLK_OUT : out std_logic;
454  ---------------------- Receive Ports - RX Gearbox Ports --------------------
455  RXDATAVALID_OUT : out std_logic;
456  RXHEADER_OUT : out std_logic_vector(1 downto 0);
457  RXHEADERVALID_OUT : out std_logic;
458  --------------------- Receive Ports - RX Gearbox Ports --------------------
459  RXGEARBOXSLIP_IN : in std_logic;
460  ------------- Receive Ports - RX Initialization and Reset Ports ------------
461  GTRXRESET_IN : in std_logic;
462  RXPCSRESET_IN : in std_logic;
463  RXPMARESET_IN : in std_logic;
464  ------------------ Receive Ports - RX Margin Analysis ports ----------------
465  RXLPMEN_IN : in std_logic;
466  -------------- Receive Ports -RX Initialization and Reset Ports ------------
467  RXRESETDONE_OUT : out std_logic;
468  --------------------- TX Initialization and Reset Ports --------------------
469  GTTXRESET_IN : in std_logic;
470  TXUSERRDY_IN : in std_logic;
471  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
472  TXUSRCLK_IN : in std_logic;
473  TXUSRCLK2_IN : in std_logic;
474  --------------- Transmit Ports - TX Configurable Driver Ports --------------
475  TXDIFFCTRL_IN : in std_logic_vector(3 downto 0);
476  TXINHIBIT_IN : in std_logic;
477  TXMAINCURSOR_IN : in std_logic_vector(6 downto 0);
478  ------------------ Transmit Ports - TX Data Path interface -----------------
479  TXDATA_IN : in std_logic_vector(31 downto 0);
480  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
481  GTXTXN_OUT : out std_logic;
482  GTXTXP_OUT : out std_logic;
483  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
484  TXOUTCLK_OUT : out std_logic;
485  TXOUTCLKFABRIC_OUT : out std_logic;
486  TXOUTCLKPCS_OUT : out std_logic;
487  --------------------- Transmit Ports - TX Gearbox Ports --------------------
488  TXHEADER_IN : in std_logic_vector(1 downto 0);
489  TXSEQUENCE_IN : in std_logic_vector(6 downto 0);
490  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
491  TXPCSRESET_IN : in std_logic;
492  TXRESETDONE_OUT : out std_logic;
493  ------------------ Transmit Ports - pattern Generator Ports ----------------
494  TXPRBSSEL_IN : in std_logic_vector(2 downto 0)
495 
496 
497 );
498 end component;
499 
500 
501 
502 --*************************Logic to set Attribute QPLL_FB_DIV*****************************
503  impure function conv_qpll_fbdiv_top (qpllfbdiv_top : in integer) return bit_vector is
504  begin
505  if (qpllfbdiv_top = 16) then
506  return "0000100000";
507  elsif (qpllfbdiv_top = 20) then
508  return "0000110000" ;
509  elsif (qpllfbdiv_top = 32) then
510  return "0001100000" ;
511  elsif (qpllfbdiv_top = 40) then
512  return "0010000000" ;
513  elsif (qpllfbdiv_top = 64) then
514  return "0011100000" ;
515  elsif (qpllfbdiv_top = 66) then
516  return "0101000000" ;
517  elsif (qpllfbdiv_top = 80) then
518  return "0100100000" ;
519  elsif (qpllfbdiv_top = 100) then
520  return "0101110000" ;
521  else
522  return "0000000000" ;
523  end if;
524  end function;
525 
526  impure function conv_qpll_fbdiv_ratio (qpllfbdiv_top : in integer) return bit is
527  begin
528  if (qpllfbdiv_top = 16) then
529  return '1';
530  elsif (qpllfbdiv_top = 20) then
531  return '1' ;
532  elsif (qpllfbdiv_top = 32) then
533  return '1' ;
534  elsif (qpllfbdiv_top = 40) then
535  return '1' ;
536  elsif (qpllfbdiv_top = 64) then
537  return '1' ;
538  elsif (qpllfbdiv_top = 66) then
539  return '0' ;
540  elsif (qpllfbdiv_top = 80) then
541  return '1' ;
542  elsif (qpllfbdiv_top = 100) then
543  return '1' ;
544  else
545  return '1' ;
546  end if;
547  end function;
548 
549  constant QPLL_FBDIV_IN : bit_vector(9 downto 0) := conv_qpll_fbdiv_top(QPLL_FBDIV_TOP);
550  constant QPLL_FBDIV_RATIO : bit := conv_qpll_fbdiv_ratio(QPLL_FBDIV_TOP);
551 
552 --********************************* Main Body of Code**************************
553 
554 begin
555 
556  tied_to_ground_i <= '0';
557  tied_to_ground_vec_i(63 downto 0) <= (others => '0');
558  tied_to_vcc_i <= '1';
559  gt0_qpllclk_i <= gt0_qplloutclk_i;
560  gt0_qpllrefclk_i <= gt0_qplloutrefclk_i;
561 
562  gt1_qpllclk_i <= gt0_qplloutclk_i;
563  gt1_qpllrefclk_i <= gt0_qplloutrefclk_i;
564 
565  gt2_qpllclk_i <= gt0_qplloutclk_i;
566  gt2_qpllrefclk_i <= gt0_qplloutrefclk_i;
567 
568 
569 
570  --------------------------- GT Instances -------------------------------
571 
572  --_________________________________________________________________________
573  --_________________________________________________________________________
574  --GT0 (X0Y12)
575 
576  gt0_SFP3_v2_7_i : SFP3_v2_7_GT
577  generic map
578  (
579  -- Simulation attributes
580  GT_SIM_GTRESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP ,
581  RX_DFE_KL_CFG2_IN => RX_DFE_KL_CFG2_IN,
582  PMA_RSV_IN => PMA_RSV_IN,
583  PCS_RSVD_ATTR_IN => X"000000000000"
584  )
585  port map
586  (
587  ---------------------------- Channel - DRP Ports --------------------------
588  DRPADDR_IN => GT0_DRPADDR_IN,
589  DRPCLK_IN => GT0_DRPCLK_IN,
590  DRPDI_IN => GT0_DRPDI_IN,
591  DRPDO_OUT => GT0_DRPDO_OUT,
592  DRPEN_IN => GT0_DRPEN_IN,
593  DRPRDY_OUT => GT0_DRPRDY_OUT,
594  DRPWE_IN => GT0_DRPWE_IN,
595  ------------------------------- Clocking Ports -----------------------------
596  QPLLCLK_IN => gt0_qpllclk_i,
597  QPLLREFCLK_IN => gt0_qpllrefclk_i,
598  ------------------------------- Loopback Ports -----------------------------
599  LOOPBACK_IN => GT0_LOOPBACK_IN,
600  ------------------------------ Power-Down Ports ----------------------------
601  RXPD_IN => GT0_RXPD_IN,
602  TXPD_IN => GT0_TXPD_IN,
603  --------------------- RX Initialization and Reset Ports --------------------
604  RXUSERRDY_IN => GT0_RXUSERRDY_IN,
605  -------------------------- RX Margin Analysis Ports ------------------------
606  EYESCANDATAERROR_OUT => GT0_EYESCANDATAERROR_OUT,
607  ------------------------- Receive Ports - CDR Ports ------------------------
608  RXCDRLOCK_OUT => GT0_RXCDRLOCK_OUT,
609  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
610  RXUSRCLK_IN => GT0_RXUSRCLK_IN,
611  RXUSRCLK2_IN => GT0_RXUSRCLK2_IN,
612  ------------------ Receive Ports - FPGA RX interface Ports -----------------
613  RXDATA_OUT => GT0_RXDATA_OUT,
614  ------------------- Receive Ports - Pattern Checker Ports ------------------
615  RXPRBSERR_OUT => GT0_RXPRBSERR_OUT,
616  RXPRBSSEL_IN => GT0_RXPRBSSEL_IN,
617  ------------------- Receive Ports - Pattern Checker ports ------------------
618  RXPRBSCNTRESET_IN => GT0_RXPRBSCNTRESET_IN ,
619  --------------------------- Receive Ports - RX AFE -------------------------
620  GTXRXP_IN => GT0_GTXRXP_IN,
621  ------------------------ Receive Ports - RX AFE Ports ----------------------
622  GTXRXN_IN => GT0_GTXRXN_IN,
623  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
624  RXBUFRESET_IN => GT0_RXBUFRESET_IN,
625  RXBUFSTATUS_OUT => GT0_RXBUFSTATUS_OUT ,
626  --------------------- Receive Ports - RX Equalizer Ports -------------------
627  RXDFEAGCHOLD_IN => GT0_RXDFEAGCHOLD_IN ,
628  RXDFELFHOLD_IN => GT0_RXDFELFHOLD_IN,
629  --------------- Receive Ports - RX Fabric Output Control Ports -------------
630  RXOUTCLK_OUT => GT0_RXOUTCLK_OUT,
631  ---------------------- Receive Ports - RX Gearbox Ports --------------------
632  RXDATAVALID_OUT => GT0_RXDATAVALID_OUT ,
633  RXHEADER_OUT => GT0_RXHEADER_OUT,
634  RXHEADERVALID_OUT => GT0_RXHEADERVALID_OUT ,
635  --------------------- Receive Ports - RX Gearbox Ports --------------------
636  RXGEARBOXSLIP_IN => GT0_RXGEARBOXSLIP_IN ,
637  ------------- Receive Ports - RX Initialization and Reset Ports ------------
638  GTRXRESET_IN => GT0_GTRXRESET_IN,
639  RXPCSRESET_IN => GT0_RXPCSRESET_IN,
640  RXPMARESET_IN => GT0_RXPMARESET_IN,
641  ------------------ Receive Ports - RX Margin Analysis ports ----------------
642  RXLPMEN_IN => GT0_RXLPMEN_IN,
643  -------------- Receive Ports -RX Initialization and Reset Ports ------------
644  RXRESETDONE_OUT => GT0_RXRESETDONE_OUT ,
645  --------------------- TX Initialization and Reset Ports --------------------
646  GTTXRESET_IN => GT0_GTTXRESET_IN,
647  TXUSERRDY_IN => GT0_TXUSERRDY_IN,
648  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
649  TXUSRCLK_IN => GT0_TXUSRCLK_IN,
650  TXUSRCLK2_IN => GT0_TXUSRCLK2_IN,
651  --------------- Transmit Ports - TX Configurable Driver Ports --------------
652  TXDIFFCTRL_IN => GT0_TXDIFFCTRL_IN,
653  TXINHIBIT_IN => GT0_TXINHIBIT_IN,
654  TXMAINCURSOR_IN => GT0_TXMAINCURSOR_IN ,
655  ------------------ Transmit Ports - TX Data Path interface -----------------
656  TXDATA_IN => GT0_TXDATA_IN,
657  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
658  GTXTXN_OUT => GT0_GTXTXN_OUT,
659  GTXTXP_OUT => GT0_GTXTXP_OUT,
660  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
661  TXOUTCLK_OUT => GT0_TXOUTCLK_OUT,
662  TXOUTCLKFABRIC_OUT => GT0_TXOUTCLKFABRIC_OUT ,
663  TXOUTCLKPCS_OUT => GT0_TXOUTCLKPCS_OUT ,
664  --------------------- Transmit Ports - TX Gearbox Ports --------------------
665  TXHEADER_IN => GT0_TXHEADER_IN,
666  TXSEQUENCE_IN => GT0_TXSEQUENCE_IN,
667  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
668  TXPCSRESET_IN => GT0_TXPCSRESET_IN,
669  TXRESETDONE_OUT => GT0_TXRESETDONE_OUT ,
670  ------------------ Transmit Ports - pattern Generator Ports ----------------
671  TXPRBSSEL_IN => GT0_TXPRBSSEL_IN
672 
673  );
674 
675  --_________________________________________________________________________
676  --_________________________________________________________________________
677  --GT1 (X0Y13)
678 
679  gt1_SFP3_v2_7_i : SFP3_v2_7_GT
680  generic map
681  (
682  -- Simulation attributes
683  GT_SIM_GTRESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP ,
684  RX_DFE_KL_CFG2_IN => RX_DFE_KL_CFG2_IN,
685  PMA_RSV_IN => PMA_RSV_IN,
686  PCS_RSVD_ATTR_IN => X"000000000000"
687  )
688  port map
689  (
690  ---------------------------- Channel - DRP Ports --------------------------
691  DRPADDR_IN => GT1_DRPADDR_IN,
692  DRPCLK_IN => GT1_DRPCLK_IN,
693  DRPDI_IN => GT1_DRPDI_IN,
694  DRPDO_OUT => GT1_DRPDO_OUT,
695  DRPEN_IN => GT1_DRPEN_IN,
696  DRPRDY_OUT => GT1_DRPRDY_OUT,
697  DRPWE_IN => GT1_DRPWE_IN,
698  ------------------------------- Clocking Ports -----------------------------
699  QPLLCLK_IN => gt1_qpllclk_i,
700  QPLLREFCLK_IN => gt1_qpllrefclk_i,
701  ------------------------------- Loopback Ports -----------------------------
702  LOOPBACK_IN => GT1_LOOPBACK_IN,
703  ------------------------------ Power-Down Ports ----------------------------
704  RXPD_IN => GT1_RXPD_IN,
705  TXPD_IN => GT1_TXPD_IN,
706  --------------------- RX Initialization and Reset Ports --------------------
707  RXUSERRDY_IN => GT1_RXUSERRDY_IN,
708  -------------------------- RX Margin Analysis Ports ------------------------
709  EYESCANDATAERROR_OUT => GT1_EYESCANDATAERROR_OUT,
710  ------------------------- Receive Ports - CDR Ports ------------------------
711  RXCDRLOCK_OUT => GT1_RXCDRLOCK_OUT,
712  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
713  RXUSRCLK_IN => GT1_RXUSRCLK_IN,
714  RXUSRCLK2_IN => GT1_RXUSRCLK2_IN,
715  ------------------ Receive Ports - FPGA RX interface Ports -----------------
716  RXDATA_OUT => GT1_RXDATA_OUT,
717  ------------------- Receive Ports - Pattern Checker Ports ------------------
718  RXPRBSERR_OUT => GT1_RXPRBSERR_OUT,
719  RXPRBSSEL_IN => GT1_RXPRBSSEL_IN,
720  ------------------- Receive Ports - Pattern Checker ports ------------------
721  RXPRBSCNTRESET_IN => GT1_RXPRBSCNTRESET_IN ,
722  --------------------------- Receive Ports - RX AFE -------------------------
723  GTXRXP_IN => GT1_GTXRXP_IN,
724  ------------------------ Receive Ports - RX AFE Ports ----------------------
725  GTXRXN_IN => GT1_GTXRXN_IN,
726  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
727  RXBUFRESET_IN => GT1_RXBUFRESET_IN,
728  RXBUFSTATUS_OUT => GT1_RXBUFSTATUS_OUT ,
729  --------------------- Receive Ports - RX Equalizer Ports -------------------
730  RXDFEAGCHOLD_IN => GT1_RXDFEAGCHOLD_IN ,
731  RXDFELFHOLD_IN => GT1_RXDFELFHOLD_IN,
732  --------------- Receive Ports - RX Fabric Output Control Ports -------------
733  RXOUTCLK_OUT => GT1_RXOUTCLK_OUT,
734  ---------------------- Receive Ports - RX Gearbox Ports --------------------
735  RXDATAVALID_OUT => GT1_RXDATAVALID_OUT ,
736  RXHEADER_OUT => GT1_RXHEADER_OUT,
737  RXHEADERVALID_OUT => GT1_RXHEADERVALID_OUT ,
738  --------------------- Receive Ports - RX Gearbox Ports --------------------
739  RXGEARBOXSLIP_IN => GT1_RXGEARBOXSLIP_IN ,
740  ------------- Receive Ports - RX Initialization and Reset Ports ------------
741  GTRXRESET_IN => GT1_GTRXRESET_IN,
742  RXPCSRESET_IN => GT1_RXPCSRESET_IN,
743  RXPMARESET_IN => GT1_RXPMARESET_IN,
744  ------------------ Receive Ports - RX Margin Analysis ports ----------------
745  RXLPMEN_IN => GT1_RXLPMEN_IN,
746  -------------- Receive Ports -RX Initialization and Reset Ports ------------
747  RXRESETDONE_OUT => GT1_RXRESETDONE_OUT ,
748  --------------------- TX Initialization and Reset Ports --------------------
749  GTTXRESET_IN => GT1_GTTXRESET_IN,
750  TXUSERRDY_IN => GT1_TXUSERRDY_IN,
751  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
752  TXUSRCLK_IN => GT1_TXUSRCLK_IN,
753  TXUSRCLK2_IN => GT1_TXUSRCLK2_IN,
754  --------------- Transmit Ports - TX Configurable Driver Ports --------------
755  TXDIFFCTRL_IN => GT1_TXDIFFCTRL_IN,
756  TXINHIBIT_IN => GT1_TXINHIBIT_IN,
757  TXMAINCURSOR_IN => GT1_TXMAINCURSOR_IN ,
758  ------------------ Transmit Ports - TX Data Path interface -----------------
759  TXDATA_IN => GT1_TXDATA_IN,
760  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
761  GTXTXN_OUT => GT1_GTXTXN_OUT,
762  GTXTXP_OUT => GT1_GTXTXP_OUT,
763  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
764  TXOUTCLK_OUT => GT1_TXOUTCLK_OUT,
765  TXOUTCLKFABRIC_OUT => GT1_TXOUTCLKFABRIC_OUT ,
766  TXOUTCLKPCS_OUT => GT1_TXOUTCLKPCS_OUT ,
767  --------------------- Transmit Ports - TX Gearbox Ports --------------------
768  TXHEADER_IN => GT1_TXHEADER_IN,
769  TXSEQUENCE_IN => GT1_TXSEQUENCE_IN,
770  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
771  TXPCSRESET_IN => GT1_TXPCSRESET_IN,
772  TXRESETDONE_OUT => GT1_TXRESETDONE_OUT ,
773  ------------------ Transmit Ports - pattern Generator Ports ----------------
774  TXPRBSSEL_IN => GT1_TXPRBSSEL_IN
775 
776  );
777 
778  --_________________________________________________________________________
779  --_________________________________________________________________________
780  --GT2 (X0Y14)
781 g_gt2: if(flavor /= "HCAL") generate
782  gt2_SFP3_v2_7_i : SFP3_v2_7_GT
783  generic map
784  (
785  -- Simulation attributes
786  GT_SIM_GTRESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP ,
787  RX_DFE_KL_CFG2_IN => RX_DFE_KL_CFG2_IN,
788  PMA_RSV_IN => PMA_RSV_IN,
789  PCS_RSVD_ATTR_IN => X"000000000000"
790  )
791  port map
792  (
793  ---------------------------- Channel - DRP Ports --------------------------
794  DRPADDR_IN => GT2_DRPADDR_IN,
795  DRPCLK_IN => GT2_DRPCLK_IN,
796  DRPDI_IN => GT2_DRPDI_IN,
797  DRPDO_OUT => GT2_DRPDO_OUT,
798  DRPEN_IN => GT2_DRPEN_IN,
799  DRPRDY_OUT => GT2_DRPRDY_OUT,
800  DRPWE_IN => GT2_DRPWE_IN,
801  ------------------------------- Clocking Ports -----------------------------
802  QPLLCLK_IN => gt2_qpllclk_i,
803  QPLLREFCLK_IN => gt2_qpllrefclk_i,
804  ------------------------------- Loopback Ports -----------------------------
805  LOOPBACK_IN => GT2_LOOPBACK_IN,
806  ------------------------------ Power-Down Ports ----------------------------
807  RXPD_IN => GT2_RXPD_IN,
808  TXPD_IN => GT2_TXPD_IN,
809  --------------------- RX Initialization and Reset Ports --------------------
810  RXUSERRDY_IN => GT2_RXUSERRDY_IN,
811  -------------------------- RX Margin Analysis Ports ------------------------
812  EYESCANDATAERROR_OUT => GT2_EYESCANDATAERROR_OUT,
813  ------------------------- Receive Ports - CDR Ports ------------------------
814  RXCDRLOCK_OUT => GT2_RXCDRLOCK_OUT,
815  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
816  RXUSRCLK_IN => GT2_RXUSRCLK_IN,
817  RXUSRCLK2_IN => GT2_RXUSRCLK2_IN,
818  ------------------ Receive Ports - FPGA RX interface Ports -----------------
819  RXDATA_OUT => GT2_RXDATA_OUT,
820  ------------------- Receive Ports - Pattern Checker Ports ------------------
821  RXPRBSERR_OUT => GT2_RXPRBSERR_OUT,
822  RXPRBSSEL_IN => GT2_RXPRBSSEL_IN,
823  ------------------- Receive Ports - Pattern Checker ports ------------------
824  RXPRBSCNTRESET_IN => GT2_RXPRBSCNTRESET_IN ,
825  --------------------------- Receive Ports - RX AFE -------------------------
826  GTXRXP_IN => GT2_GTXRXP_IN,
827  ------------------------ Receive Ports - RX AFE Ports ----------------------
828  GTXRXN_IN => GT2_GTXRXN_IN,
829  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
830  RXBUFRESET_IN => GT2_RXBUFRESET_IN,
831  RXBUFSTATUS_OUT => GT2_RXBUFSTATUS_OUT ,
832  --------------------- Receive Ports - RX Equalizer Ports -------------------
833  RXDFEAGCHOLD_IN => GT2_RXDFEAGCHOLD_IN ,
834  RXDFELFHOLD_IN => GT2_RXDFELFHOLD_IN,
835  --------------- Receive Ports - RX Fabric Output Control Ports -------------
836  RXOUTCLK_OUT => GT2_RXOUTCLK_OUT,
837  ---------------------- Receive Ports - RX Gearbox Ports --------------------
838  RXDATAVALID_OUT => GT2_RXDATAVALID_OUT ,
839  RXHEADER_OUT => GT2_RXHEADER_OUT,
840  RXHEADERVALID_OUT => GT2_RXHEADERVALID_OUT ,
841  --------------------- Receive Ports - RX Gearbox Ports --------------------
842  RXGEARBOXSLIP_IN => GT2_RXGEARBOXSLIP_IN ,
843  ------------- Receive Ports - RX Initialization and Reset Ports ------------
844  GTRXRESET_IN => GT2_GTRXRESET_IN,
845  RXPCSRESET_IN => GT2_RXPCSRESET_IN,
846  RXPMARESET_IN => GT2_RXPMARESET_IN,
847  ------------------ Receive Ports - RX Margin Analysis ports ----------------
848  RXLPMEN_IN => GT2_RXLPMEN_IN,
849  -------------- Receive Ports -RX Initialization and Reset Ports ------------
850  RXRESETDONE_OUT => GT2_RXRESETDONE_OUT ,
851  --------------------- TX Initialization and Reset Ports --------------------
852  GTTXRESET_IN => GT2_GTTXRESET_IN,
853  TXUSERRDY_IN => GT2_TXUSERRDY_IN,
854  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
855  TXUSRCLK_IN => GT2_TXUSRCLK_IN,
856  TXUSRCLK2_IN => GT2_TXUSRCLK2_IN,
857  --------------- Transmit Ports - TX Configurable Driver Ports --------------
858  TXDIFFCTRL_IN => GT2_TXDIFFCTRL_IN,
859  TXINHIBIT_IN => GT2_TXINHIBIT_IN,
860  TXMAINCURSOR_IN => GT2_TXMAINCURSOR_IN ,
861  ------------------ Transmit Ports - TX Data Path interface -----------------
862  TXDATA_IN => GT2_TXDATA_IN,
863  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
864  GTXTXN_OUT => GT2_GTXTXN_OUT,
865  GTXTXP_OUT => GT2_GTXTXP_OUT,
866  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
867  TXOUTCLK_OUT => GT2_TXOUTCLK_OUT,
868  TXOUTCLKFABRIC_OUT => GT2_TXOUTCLKFABRIC_OUT ,
869  TXOUTCLKPCS_OUT => GT2_TXOUTCLKPCS_OUT ,
870  --------------------- Transmit Ports - TX Gearbox Ports --------------------
871  TXHEADER_IN => GT2_TXHEADER_IN,
872  TXSEQUENCE_IN => GT2_TXSEQUENCE_IN,
873  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
874  TXPCSRESET_IN => GT2_TXPCSRESET_IN,
875  TXRESETDONE_OUT => GT2_TXRESETDONE_OUT ,
876  ------------------ Transmit Ports - pattern Generator Ports ----------------
877  TXPRBSSEL_IN => GT2_TXPRBSSEL_IN
878 
879  );
880 end generate g_gt2;
881  --_________________________________________________________________________
882  --_________________________________________________________________________
883  --_________________________GTXE2_COMMON____________________________________
884 
885  gtxe2_common_0_i : GTXE2_COMMON
886  generic map
887  (
888  -- Simulation attributes
889  SIM_RESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP ,
890  SIM_QPLLREFCLK_SEL => ("001"),
891  SIM_VERSION => "4.0",
892 
893 
894  ------------------COMMON BLOCK Attributes---------------
895  BIAS_CFG => (x"0000040000001000"),
896  COMMON_CFG => (x"00000000"),
897  QPLL_CFG => (x"0680181"),
898  QPLL_CLKOUT_CFG => ("0000"),
899  QPLL_COARSE_FREQ_OVRD => ("010000"),
900  QPLL_COARSE_FREQ_OVRD_EN => ('0'),
901  QPLL_CP => ("0000011111"),
902  QPLL_CP_MONITOR_EN => ('0'),
903  QPLL_DMONITOR_SEL => ('0'),
904  QPLL_FBDIV => (QPLL_FBDIV_IN),
905  QPLL_FBDIV_MONITOR_EN => ('0'),
906  QPLL_FBDIV_RATIO => (QPLL_FBDIV_RATIO),
907  QPLL_INIT_CFG => (x"000006"),
908  QPLL_LOCK_CFG => (x"21E8"),
909  QPLL_LPF => ("1111"),
910  QPLL_REFCLK_DIV => (1)
911 
912 
913  )
914  port map
915  (
916  ------------- Common Block - Dynamic Reconfiguration Port (DRP) -----------
917  DRPADDR => tied_to_ground_vec_i (7 downto 0),
918  DRPCLK => tied_to_ground_i,
919  DRPDI => tied_to_ground_vec_i (15 downto 0),
920  DRPDO => open,
921  DRPEN => tied_to_ground_i,
922  DRPRDY => open,
923  DRPWE => tied_to_ground_i,
924  ---------------------- Common Block - Ref Clock Ports ---------------------
925  GTGREFCLK => tied_to_ground_i,
926  GTNORTHREFCLK0 => tied_to_ground_i,
927  GTNORTHREFCLK1 => tied_to_ground_i,
928  GTREFCLK0 => GT0_GTREFCLK0_COMMON_IN ,
929  GTREFCLK1 => tied_to_ground_i,
930  GTSOUTHREFCLK0 => tied_to_ground_i,
931  GTSOUTHREFCLK1 => tied_to_ground_i,
932  ------------------------- Common Block - QPLL Ports -----------------------
933  QPLLDMONITOR => open,
934  ----------------------- Common Block - Clocking Ports ----------------------
935  QPLLOUTCLK => gt0_qplloutclk_i,
936  QPLLOUTREFCLK => gt0_qplloutrefclk_i ,
937  REFCLKOUTMONITOR => open,
938  ------------------------- Common Block - QPLL Ports ------------------------
939  QPLLFBCLKLOST => open,
940  QPLLLOCK => GT0_QPLLLOCK_OUT,
941  QPLLLOCKDETCLK => GT0_QPLLLOCKDETCLK_IN ,
942  QPLLLOCKEN => tied_to_vcc_i,
943  QPLLOUTRESET => tied_to_ground_i,
944  QPLLPD => tied_to_ground_i,
945  QPLLREFCLKLOST => GT0_QPLLREFCLKLOST_OUT ,
946  QPLLREFCLKSEL => "001",
947  QPLLRESET => GT0_QPLLRESET_IN,
948  QPLLRSVD1 => "0000000000000000",
949  QPLLRSVD2 => "11111",
950  --------------------------------- QPLL Ports -------------------------------
951  BGBYPASSB => tied_to_vcc_i,
952  BGMONITORENB => tied_to_vcc_i,
953  BGPDB => tied_to_vcc_i,
954  BGRCALOVRD => "00000",
955  PMARSVD => "00000000",
956  RCALENB => tied_to_vcc_i
957 
958  );
959 
960 
961 
962 end RTL;
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