AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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mig_7series_v1_9_ddr_phy_top.vhd
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49 -- ____ ____
50 -- / /\/ /
51 -- /___/ \ / Vendor : Xilinx
52 -- \ \ \/ Version : 1.5
53 -- \ \ Application : MIG
54 -- / / Filename : ddr_phy_top.vhd
55 -- /___/ /\ Date Last Modified : $date$
56 -- \ \ / \ Date Created : Jan 31 2012
57 -- \___\/\___\
58 --
59 --Device : 7 Series
60 --Design Name : DDR3 SDRAM
61 --Purpose : Top level memory interface block. Instantiates a clock
62 -- and reset generator, the memory controller, the phy and
63 -- the user interface blocks.
64 --Reference :
65 --Revision History :
66 --*****************************************************************************
67 
68 library ieee;
69  use ieee.std_logic_1164.all;
70  use ieee.numeric_std.all;
71 
72 
73 entity mig_7series_v1_9_ddr_phy_top is
74  generic (
75 
76  TCQ : integer := 100; -- Register delay (simulation only)
77  AL : string := "0"; -- Additive Latency option
78  BANK_WIDTH : integer := 3; -- # of bank bits
79  BURST_MODE : string := "8"; -- Burst length
80  BURST_TYPE : string := "SEQ"; -- Burst type
81  CA_MIRROR : string := "OFF"; -- C/A mirror opt for DDR3 dual rank
82  CK_WIDTH : integer := 1; -- # of CK/CK# outputs to memory
83  CL : integer := 5;
84  COL_WIDTH : integer := 12; -- column address width
85  CS_WIDTH : integer := 1; -- # of unique CS outputs
86  CKE_WIDTH : integer := 1; -- # of cke outputs
87  CWL : integer := 5;
88  DM_WIDTH : integer := 8; -- # of DM (data mask)
89  DQ_WIDTH : integer := 64; -- # of DQ (data)
90  DQS_CNT_WIDTH : integer := 3; -- = ceil(log2(DQS_WIDTH))
91  DQS_WIDTH : integer := 8; -- # of DQS (strobe)
92  DRAM_TYPE : string := "DDR3";
93  DRAM_WIDTH : integer := 8; -- # of DQ per DQS
94  MASTER_PHY_CTL : integer := 0; -- The bank number where master PHY_CONTROL resides
95  LP_DDR_CK_WIDTH : integer := 2;
96  DATA_IO_IDLE_PWRDWN : string := "ON"; -- "ON" or "OFF"
97  -- Hard PHY parameters
98  PHYCTL_CMD_FIFO : string := "FALSE";
99  -- five fields, one per possible I/O bank, 4 bits in each field,
100  -- 1 per lane data=1/ctl=0
101  DATA_CTL_B0 : std_logic_vector(3 downto 0) := X"c";
102  DATA_CTL_B1 : std_logic_vector(3 downto 0) := X"f";
103  DATA_CTL_B2 : std_logic_vector(3 downto 0) := X"f";
104  DATA_CTL_B3 : std_logic_vector(3 downto 0) := X"f";
105  DATA_CTL_B4 : std_logic_vector(3 downto 0) := X"f";
106  -- defines the byte lanes in I/O banks being used in the interface
107  -- 1- Used, 0- Unused
108  BYTE_LANES_B0 : std_logic_vector(3 downto 0) := "1111";
109  BYTE_LANES_B1 : std_logic_vector(3 downto 0) := "0000";
110  BYTE_LANES_B2 : std_logic_vector(3 downto 0) := "0000";
111  BYTE_LANES_B3 : std_logic_vector(3 downto 0) := "0000";
112  BYTE_LANES_B4 : std_logic_vector(3 downto 0) := "0000";
113  -- defines the bit lanes in I/O banks being used in the interface. Each
114  -- = 1 I/O bank = 4 byte lanes = 48 bit lanes. 1-Used, 0-Unused
115  PHY_0_BITLANES : std_logic_vector(47 downto 0) := X"000000000000";
116  PHY_1_BITLANES : std_logic_vector(47 downto 0) := X"000000000000";
117  PHY_2_BITLANES : std_logic_vector(47 downto 0) := X"000000000000";
118 
119  -- control/address/data pin mapping parameters
120  CK_BYTE_MAP : std_logic_vector(143 downto 0) := X"000000000000000000000000000000000000";
121  ADDR_MAP : std_logic_vector(191 downto 0) := X"000000000000000000000000000000000000000000000000";
122  BANK_MAP : std_logic_vector(35 downto 0) := X"000000000";
123  CAS_MAP : std_logic_vector(11 downto 0) := X"000";
124  CKE_ODT_BYTE_MAP : std_logic_vector(7 downto 0) := X"00";
125  CKE_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
126  ODT_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
127  CKE_ODT_AUX : string := "FALSE";
128  CS_MAP : std_logic_vector(119 downto 0) := X"000000000000000000000000000000";
129  PARITY_MAP : std_logic_vector(11 downto 0) := X"000";
130  RAS_MAP : std_logic_vector(11 downto 0) := X"000";
131  WE_MAP : std_logic_vector(11 downto 0) := X"000";
132  DQS_BYTE_MAP
133  : std_logic_vector(143 downto 0) := X"000000000000000000000000000000000000";
134  DATA0_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
135  DATA1_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
136  DATA2_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
137  DATA3_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
138  DATA4_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
139  DATA5_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
140  DATA6_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
141  DATA7_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
142  DATA8_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
143  DATA9_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
144  DATA10_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
145  DATA11_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
146  DATA12_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
147  DATA13_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
148  DATA14_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
149  DATA15_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
150  DATA16_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
151  DATA17_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
152  MASK0_MAP : std_logic_vector(107 downto 0) := X"000000000000000000000000000";
153  MASK1_MAP : std_logic_vector(107 downto 0) := X"000000000000000000000000000";
154 
155  -- This parameter must be set based on memory clock frequency
156  -- It must be set to 4 for frequencies above 533 MHz?? (undecided)
157  -- and set to 2 for 533 MHz and below
158  PRE_REV3ES : string := "OFF"; -- Delay O/Ps using Phaser_Out fine dly
159  nCK_PER_CLK : integer := 2; -- # of memory CKs per fabric CLK
160  nCS_PER_RANK : integer := 1; -- # of unique CS outputs per rank
161  ADDR_CMD_MODE : string := "1T"; -- ADDR/CTRL timing: "2T", "1T"
162  IODELAY_HP_MODE : string := "ON";
163  BANK_TYPE : string := "HP_IO"; -- # = "HP_LP", "HR_LP", "DEFAULT"
164  DATA_IO_PRIM_TYPE : string := "DEFAULT"; -- # = "HP_LP", "HR_LP", "DEFAULT"
165  IODELAY_GRP : string := "IODELAY_MIG";
166  IBUF_LPWR_MODE : string := "OFF"; -- input buffer low power option
167  OUTPUT_DRV : string := "HIGH"; -- to calib_top
168  REG_CTRL : string := "OFF"; -- to calib_top
169  RTT_NOM : string := "60"; -- to calib_top
170  RTT_WR : string := "120"; -- to calib_top
171  tCK : integer := 2500; -- pS
172  tRFC : integer := 110000; -- pS
173  DDR2_DQSN_ENABLE : string := "YES"; -- Enable differential DQS for DDR2
174  WRLVL : string := "OFF"; -- to calib_top
175  DEBUG_PORT : string := "OFF"; -- to calib_top
176  RANKS : integer := 4;
177  ODT_WIDTH : integer := 1;
178  ROW_WIDTH : integer := 16; -- DRAM address bus width
179  SLOT_1_CONFIG : std_logic_vector(7 downto 0) := "00000000";
180  -- calibration Address. The address given below will be used for calibration
181  -- read and write operations.
182  CALIB_ROW_ADD : std_logic_vector(15 downto 0) := X"0000"; -- Calibration row address
183  CALIB_COL_ADD : std_logic_vector(11 downto 0) := X"000"; -- Calibration column address
184  CALIB_BA_ADD : std_logic_vector(2 downto 0) := "000"; -- Calibration bank address
185  -- Simulation /debug options
186  SIM_BYPASS_INIT_CAL : string := "OFF";
187  -- Parameter used to force skipping
188  -- or abbreviation of initialization
189  -- and calibration. Overrides
190  -- SIM_INIT_OPTION, SIM_CAL_OPTION,
191  -- and disables various other blocks
192  --parameter SIM_INIT_OPTION = "SKIP_PU_DLY", -- Skip various init steps
193  --parameter SIM_CAL_OPTION = "NONE", -- Skip various calib steps
194  REFCLK_FREQ : real := 200.0; -- IODELAY ref clock freq (MHz)
195  USE_CS_PORT : integer := 1; -- Support chip select output
196  USE_DM_PORT : integer := 1; -- Support data mask output
197  USE_ODT_PORT : integer := 1; -- Support ODT output
198  RD_PATH_REG : integer := 0 -- optional registers in the read path
199  -- to MC for timing improvement.
200  -- =1 enabled, = 0 disabled
201  );
202  port (
203  clk : in std_logic; -- Fabric logic clock
204  -- To MC, calib_top, hard PHY
205  clk_ref : in std_logic; -- Idelay_ctrl reference clock
206  -- To hard PHY (external source)
207  freq_refclk : in std_logic; -- To hard PHY for Phasers
208  mem_refclk : in std_logic; -- Memory clock to hard PHY
209  pll_lock : in std_logic; -- System PLL lock signal
210  sync_pulse : in std_logic; -- 1/N sync pulse used to
211  -- synchronize all PHASERS
212  error : in std_logic; -- Support for TG error detect
213  rst_tg_mc : out std_logic; -- Support for TG error detect
214 
215  device_temp : in std_logic_vector(11 downto 0);
216  tempmon_sample_en : in std_logic;
217 
218  dbg_sel_pi_incdec : in std_logic;
219  dbg_sel_po_incdec : in std_logic;
220  dbg_byte_sel : in std_logic_vector(DQS_CNT_WIDTH downto 0);
221  dbg_pi_f_inc : in std_logic;
222  dbg_pi_f_dec : in std_logic;
223  dbg_po_f_inc : in std_logic;
224  dbg_po_f_stg23_sel : in std_logic;
225  dbg_po_f_dec : in std_logic;
226  dbg_idel_down_all : in std_logic;
227  dbg_idel_down_cpt : in std_logic;
228  dbg_idel_up_all : in std_logic;
229  dbg_idel_up_cpt : in std_logic;
230  dbg_sel_all_idel_cpt : in std_logic;
231  dbg_sel_idel_cpt : in std_logic_vector(DQS_CNT_WIDTH-1 downto 0);
232  rst : in std_logic;
233  slot_0_present : in std_logic_vector(7 downto 0);
234  slot_1_present : in std_logic_vector(7 downto 0);
235  -- From MC
236  mc_ras_n : in std_logic_vector(nCK_PER_CLK-1 downto 0);
237  mc_cas_n : in std_logic_vector(nCK_PER_CLK-1 downto 0);
238  mc_we_n : in std_logic_vector(nCK_PER_CLK-1 downto 0);
239  mc_address : in std_logic_vector(nCK_PER_CLK*ROW_WIDTH-1 downto 0);
240  mc_bank : in std_logic_vector(nCK_PER_CLK*BANK_WIDTH-1 downto 0);
241  mc_cs_n : in std_logic_vector(CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1 downto 0);
242  mc_reset_n : in std_logic;
243  mc_odt : in std_logic_vector(1 downto 0);
244  mc_cke : in std_logic_vector(nCK_PER_CLK-1 downto 0);
245  -- AUX - For ODT and CKE assertion during reads and writes
246  mc_aux_out0 : in std_logic_vector(3 downto 0);
247  mc_aux_out1 : in std_logic_vector(3 downto 0);
248  mc_cmd_wren : in std_logic;
249  mc_ctl_wren : in std_logic;
250  mc_cmd : in std_logic_vector(2 downto 0);
251  mc_cas_slot : in std_logic_vector(1 downto 0);
252  mc_data_offset : in std_logic_vector(5 downto 0);
253  mc_data_offset_1 : in std_logic_vector(5 downto 0);
254  mc_data_offset_2 : in std_logic_vector(5 downto 0);
255  mc_rank_cnt : in std_logic_vector(1 downto 0);
256  -- Write
257  mc_wrdata_en : in std_logic;
258  mc_wrdata : in std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0);
259  mc_wrdata_mask : in std_logic_vector((2*nCK_PER_CLK*(DQ_WIDTH/8))-1 downto 0);
260  idle : in std_logic;
261  -- DDR bus signals
262  ddr_addr : out std_logic_vector(ROW_WIDTH-1 downto 0);
263  ddr_ba : out std_logic_vector(BANK_WIDTH-1 downto 0);
264  ddr_cas_n : out std_logic;
265  ddr_ck_n : out std_logic_vector(CK_WIDTH-1 downto 0);
266  ddr_ck : out std_logic_vector(CK_WIDTH-1 downto 0);
267  ddr_cke : out std_logic_vector(CKE_WIDTH-1 downto 0);
268  ddr_cs_n : out std_logic_vector((CS_WIDTH*nCS_PER_RANK)-1 downto 0);
269  ddr_dm : out std_logic_vector(DM_WIDTH-1 downto 0);
270  ddr_odt : out std_logic_vector(ODT_WIDTH-1 downto 0);
271  ddr_ras_n : out std_logic;
272  ddr_reset_n : out std_logic;
273  ddr_parity : out std_logic;
274  ddr_we_n : out std_logic;
275  ddr_dq : inout std_logic_vector(DQ_WIDTH-1 downto 0);
276  ddr_dqs_n : inout std_logic_vector(DQS_WIDTH-1 downto 0);
277  ddr_dqs : inout std_logic_vector(DQS_WIDTH-1 downto 0);
278 
279  dbg_calib_top : out std_logic_vector(255 downto 0);
280  dbg_cpt_first_edge_cnt : out std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0);
281  dbg_cpt_second_edge_cnt : out std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0);
282  dbg_cpt_tap_cnt : out std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0);
283  dbg_dq_idelay_tap_cnt : out std_logic_vector(5*DQS_WIDTH*RANKS-1 downto 0);
284  dbg_phy_rdlvl : out std_logic_vector(255 downto 0);
285  dbg_phy_wrcal : out std_logic_vector(99 downto 0);
286  dbg_final_po_fine_tap_cnt : out std_logic_vector(6*DQS_WIDTH-1 downto 0);
287  dbg_final_po_coarse_tap_cnt : out std_logic_vector(3*DQS_WIDTH-1 downto 0);
288  dbg_rd_data_edge_detect : out std_logic_vector(DQS_WIDTH-1 downto 0);
289  dbg_rddata : out std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0);
290  dbg_rddata_valid : out std_logic;
291  dbg_rdlvl_done : out std_logic_vector(1 downto 0);
292  dbg_rdlvl_err : out std_logic_vector(1 downto 0);
293  dbg_rdlvl_start : out std_logic_vector(1 downto 0);
294  dbg_tap_cnt_during_wrlvl : out std_logic_vector(5 downto 0);
295  dbg_wl_edge_detect_valid : out std_logic;
296  dbg_wrlvl_done : out std_logic;
297  dbg_wrlvl_err : out std_logic;
298  dbg_wrlvl_start : out std_logic;
299  dbg_wrlvl_fine_tap_cnt : out std_logic_vector(6*DQS_WIDTH-1 downto 0);
300  dbg_wrlvl_coarse_tap_cnt : out std_logic_vector(3*DQS_WIDTH-1 downto 0);
301  dbg_phy_wrlvl : out std_logic_vector(255 downto 0);
302  dbg_pi_phaselock_start : out std_logic;
303  dbg_pi_phaselocked_done : out std_logic;
304  dbg_pi_phaselock_err : out std_logic;
305  dbg_pi_phase_locked_phy4lanes : out std_logic_vector(11 downto 0);
306  dbg_pi_dqsfound_start : out std_logic;
307  dbg_pi_dqsfound_done : out std_logic;
308  dbg_pi_dqsfound_err : out std_logic;
309  dbg_pi_dqs_found_lanes_phy4lanes : out std_logic_vector(11 downto 0);
310  dbg_wrcal_start : out std_logic;
311  dbg_wrcal_done : out std_logic;
312  dbg_wrcal_err : out std_logic;
313  -- FIFO status flags
314  phy_mc_ctl_full : out std_logic;
315  phy_mc_cmd_full : out std_logic;
316  phy_mc_data_full : out std_logic;
317  -- Calibration status and resultant outputs
318  init_calib_complete : out std_logic;
319  init_wrcal_complete : out std_logic;
320  calib_rd_data_offset_0 : out std_logic_vector(6*RANKS-1 downto 0);
321  calib_rd_data_offset_1 : out std_logic_vector(6*RANKS-1 downto 0);
322  calib_rd_data_offset_2 : out std_logic_vector(6*RANKS-1 downto 0);
323  phy_rddata_valid : out std_logic;
324  phy_rd_data : out std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0);
325 
326  ref_dll_lock : out std_logic;
327  rst_phaser_ref : in std_logic;
328  dbg_rd_data_offset : out std_logic_vector(6*RANKS-1 downto 0);
329  dbg_phy_init : out std_logic_vector(255 downto 0);
330  dbg_prbs_rdlvl : out std_logic_vector(255 downto 0);
331  dbg_dqs_found_cal : out std_logic_vector(255 downto 0);
332  dbg_pi_counter_read_val : out std_logic_vector(5 downto 0);
333  dbg_po_counter_read_val : out std_logic_vector(8 downto 0);
334  dbg_oclkdelay_calib_start : out std_logic;
335  dbg_oclkdelay_calib_done : out std_logic;
336  dbg_phy_oclkdelay_cal : out std_logic_vector(255 downto 0);
337  dbg_oclkdelay_rd_data : out std_logic_vector(DRAM_WIDTH*16-1 downto 0)
338  );
339 
340 end entity;
341 
342 architecture arch_ddr_phy_top of mig_7series_v1_9_ddr_phy_top is
343 
344  -- function to OR the bits in a vectored signal
345  function OR_BR (inp_var: std_logic_vector)
346  return std_logic is
347  variable temp: std_logic := '0';
348  begin
349  for idx in inp_var'range loop
350  temp := temp or inp_var(idx);
351  end loop;
352  return temp;
353  end function;
354 
355  -- Calculate number of slots in the system
356  function CALC_nSLOTS return integer is
357  begin
358  if (OR_BR(SLOT_1_CONFIG) = '1') then
359  return (2);
360  else
361  return (1);
362  end if;
363  end function;
364 
365  function SIM_INIT_OPTION_W return string is
366  begin
367  if (SIM_BYPASS_INIT_CAL = "SKIP") then
368  return ("SKIP_INIT");
369  elsif (SIM_BYPASS_INIT_CAL = "FAST" or
370  SIM_BYPASS_INIT_CAL = "SIM_FULL") then
371  return ("SKIP_PU_DLY");
372  else
373  return ("NONE");
374  end if;
375  end function;
376 
377  function SIM_CAL_OPTION_W return string is
378  begin
379  if (SIM_BYPASS_INIT_CAL = "SKIP") then
380  return ("SKIP_CAL");
381  elsif (SIM_BYPASS_INIT_CAL = "FAST") then
382  return ("FAST_CAL");
383  elsif (SIM_BYPASS_INIT_CAL = "SIM_FULL" or
384  SIM_BYPASS_INIT_CAL = "SIM_INIT_CAL_FULL") then
385  return ("FAST_WIN_DETECT");
386  else
387  return ("NONE");
388  end if;
389  end function;
390 
391  function CALC_WRLVL_W return string is
392  begin
393  if (SIM_BYPASS_INIT_CAL = "SKIP") then
394  return ("OFF");
395  else
396  return (WRLVL);
397  end if;
398  end function;
399 
400  function HIGHEST_BANK_W return integer is
401  begin
402  if (BYTE_LANES_B4 /= "0000") then
403  return (5);
404  elsif (BYTE_LANES_B3 /= "0000") then
405  return (4);
406  elsif (BYTE_LANES_B2 /= "0000") then
407  return (3);
408  elsif (BYTE_LANES_B1 /= "0000") then
409  return (2);
410  else
411  return (1);
412  end if;
413  end function;
414 
415  function HIGHEST_LANE_B0_W return integer is
416  begin
417  if (BYTE_LANES_B0(3) = '1') then
418  return (4);
419  elsif (BYTE_LANES_B0(2) = '1') then
420  return (3);
421  elsif (BYTE_LANES_B0(1) = '1') then
422  return (2);
423  elsif (BYTE_LANES_B0(0) = '1') then
424  return (1);
425  else
426  return (0);
427  end if;
428  end function;
429 
430  function HIGHEST_LANE_B1_W return integer is
431  begin
432  if (BYTE_LANES_B1(3) = '1') then
433  return (4);
434  elsif (BYTE_LANES_B1(2) = '1') then
435  return (3);
436  elsif (BYTE_LANES_B1(1) = '1') then
437  return (2);
438  elsif (BYTE_LANES_B1(0) = '1') then
439  return (1);
440  else
441  return (0);
442  end if;
443  end function;
444 
445  function HIGHEST_LANE_B2_W return integer is
446  begin
447  if (BYTE_LANES_B2(3) = '1') then
448  return (4);
449  elsif (BYTE_LANES_B2(2) = '1') then
450  return (3);
451  elsif (BYTE_LANES_B2(1) = '1') then
452  return (2);
453  elsif (BYTE_LANES_B2(0) = '1') then
454  return (1);
455  else
456  return (0);
457  end if;
458  end function;
459 
460  function HIGHEST_LANE_B3_W return integer is
461  begin
462  if (BYTE_LANES_B3(3) = '1') then
463  return (4);
464  elsif (BYTE_LANES_B3(2) = '1') then
465  return (3);
466  elsif (BYTE_LANES_B3(1) = '1') then
467  return (2);
468  elsif (BYTE_LANES_B3(0) = '1') then
469  return (1);
470  else
471  return (0);
472  end if;
473  end function;
474 
475  function HIGHEST_LANE_B4_W return integer is
476  begin
477  if (BYTE_LANES_B4(3) = '1') then
478  return (4);
479  elsif (BYTE_LANES_B4(2) = '1') then
480  return (3);
481  elsif (BYTE_LANES_B4(1) = '1') then
482  return (2);
483  elsif (BYTE_LANES_B4(0) = '1') then
484  return (1);
485  else
486  return (0);
487  end if;
488  end function;
489 
490  function HIGHEST_LANE_W return integer is
491  begin
492  if (HIGHEST_LANE_B4_W /= 0) then
493  return (HIGHEST_LANE_B4_W+16);
494  elsif (HIGHEST_LANE_B3_W /= 0) then
495  return (HIGHEST_LANE_B3_W+12);
496  elsif (HIGHEST_LANE_B2_W /= 0) then
497  return (HIGHEST_LANE_B2_W+8);
498  elsif (HIGHEST_LANE_B1_W /= 0) then
499  return (HIGHEST_LANE_B1_W+4);
500  else
501  return (HIGHEST_LANE_B0_W);
502  end if;
503  end function;
504 
505  function N_CTL_LANES_B0 return integer is
506  variable temp: integer := 0;
507  begin
508  for idx in 0 to 3 loop
509  if (not(DATA_CTL_B0(idx)) = '1' and BYTE_LANES_B0(idx) = '1') then
510  temp := temp + 1;
511  else
512  temp := temp;
513  end if;
514  end loop;
515  return temp;
516  end function;
517 
518  function N_CTL_LANES_B1 return integer is
519  variable temp: integer := 0;
520  begin
521  for idx in 0 to 3 loop
522  if (not(DATA_CTL_B1(idx)) = '1' and BYTE_LANES_B1(idx) = '1') then
523  temp := temp + 1;
524  else
525  temp := temp;
526  end if;
527  end loop;
528  return temp;
529  end function;
530 
531  function N_CTL_LANES_B2 return integer is
532  variable temp: integer := 0;
533  begin
534  for idx in 0 to 3 loop
535  if (not(DATA_CTL_B2(idx)) = '1' and BYTE_LANES_B2(idx) = '1') then
536  temp := temp + 1;
537  else
538  temp := temp;
539  end if;
540  end loop;
541  return temp;
542  end function;
543 
544  function N_CTL_LANES_B3 return integer is
545  variable temp: integer := 0;
546  begin
547  for idx in 0 to 3 loop
548  if (not(DATA_CTL_B3(idx)) = '1' and BYTE_LANES_B3(idx) = '1') then
549  temp := temp + 1;
550  else
551  temp := temp;
552  end if;
553  end loop;
554  return temp;
555  end function;
556 
557  function N_CTL_LANES_B4 return integer is
558  variable temp: integer := 0;
559  begin
560  for idx in 0 to 3 loop
561  if (not(DATA_CTL_B4(idx)) = '1' and BYTE_LANES_B4(idx) = '1') then
562  temp := temp + 1;
563  else
564  temp := temp;
565  end if;
566  end loop;
567  return temp;
568  end function;
569 
570  function CTL_BANK_B0 return std_logic is
571  begin
572  if ((not(DATA_CTL_B0(0)) = '1' and BYTE_LANES_B0(0) = '1') or
573  (not(DATA_CTL_B0(1)) = '1' and BYTE_LANES_B0(1) = '1') or
574  (not(DATA_CTL_B0(2)) = '1' and BYTE_LANES_B0(2) = '1') or
575  (not(DATA_CTL_B0(3)) = '1' and BYTE_LANES_B0(3) = '1')) then
576  return ('1') ;
577  else
578  return ('0') ;
579  end if;
580  end function;
581 
582  function CTL_BANK_B1 return std_logic is
583  begin
584  if ((not(DATA_CTL_B1(0)) = '1' and BYTE_LANES_B1(0) = '1') or
585  (not(DATA_CTL_B1(1)) = '1' and BYTE_LANES_B1(1) = '1') or
586  (not(DATA_CTL_B1(2)) = '1' and BYTE_LANES_B1(2) = '1') or
587  (not(DATA_CTL_B1(3)) = '1' and BYTE_LANES_B1(3) = '1')) then
588  return ('1') ;
589  else
590  return ('0') ;
591  end if;
592  end function;
593 
594  function CTL_BANK_B2 return std_logic is
595  begin
596  if ((not(DATA_CTL_B2(0)) = '1' and BYTE_LANES_B2(0) = '1') or
597  (not(DATA_CTL_B2(1)) = '1' and BYTE_LANES_B2(1) = '1') or
598  (not(DATA_CTL_B2(2)) = '1' and BYTE_LANES_B2(2) = '1') or
599  (not(DATA_CTL_B2(3)) = '1' and BYTE_LANES_B2(3) = '1')) then
600  return ('1') ;
601  else
602  return ('0') ;
603  end if;
604  end function;
605 
606  function CTL_BANK_B3 return std_logic is
607  begin
608  if ((not(DATA_CTL_B3(0)) = '1' and BYTE_LANES_B3(0) = '1') or
609  (not(DATA_CTL_B3(1)) = '1' and BYTE_LANES_B3(1) = '1') or
610  (not(DATA_CTL_B3(2)) = '1' and BYTE_LANES_B3(2) = '1') or
611  (not(DATA_CTL_B3(3)) = '1' and BYTE_LANES_B3(3) = '1')) then
612  return ('1') ;
613  else
614  return ('0') ;
615  end if;
616  end function;
617 
618  function CTL_BANK_B4 return std_logic is
619  begin
620  if ((not(DATA_CTL_B4(0)) = '1' and BYTE_LANES_B4(0) = '1') or
621  (not(DATA_CTL_B4(1)) = '1' and BYTE_LANES_B4(1) = '1') or
622  (not(DATA_CTL_B4(2)) = '1' and BYTE_LANES_B4(2) = '1') or
623  (not(DATA_CTL_B4(3)) = '1' and BYTE_LANES_B4(3) = '1')) then
624  return ('1') ;
625  else
626  return ('0') ;
627  end if;
628  end function;
629 
630  function CTL_BANK_W return std_logic_vector is
631  variable ctl_bank_var : std_logic_vector(2 downto 0);
632  begin
633  if (CTL_BANK_B0 = '1') then
634  ctl_bank_var := "000";
635  elsif (CTL_BANK_B1 = '1') then
636  ctl_bank_var := "001";
637  elsif (CTL_BANK_B2 = '1') then
638  ctl_bank_var := "010";
639  elsif (CTL_BANK_B3 = '1') then
640  ctl_bank_var := "011";
641  elsif (CTL_BANK_B4 = '1') then
642  ctl_bank_var := "100";
643  else
644  ctl_bank_var := "000";
645  end if;
646  return (ctl_bank_var);
647  end function;
648 
649  function ODD_PARITY (inp_var : std_logic_vector) return std_logic is
650  variable tmp : std_logic := '0';
651  begin
652  for idx in inp_var'range loop
653  tmp := tmp XOR inp_var(idx);
654  end loop;
655  return tmp;
656  end ODD_PARITY;
657 
658  -- Calculate number of slots in the system
659  constant nSLOTS : integer := CALC_nSLOTS;
660  constant CLK_PERIOD : integer := tCK * nCK_PER_CLK;
661 
662  -- Parameter used to force skipping or abbreviation of initialization
663  -- and calibration. Overrides SIM_INIT_OPTION, SIM_CAL_OPTION, and
664  -- disables various other blocks depending on the option selected
665  -- This option should only be used during simulation. In the case of
666  -- the "SKIP" option, the testbench used should also not be modeling
667  -- propagation delays.
668  -- Allowable options = {"NONE", "SIM_FULL", "SKIP", "FAST"}
669  -- "NONE" = options determined by the individual parameter settings
670  -- "SIM_FULL" = skip power-up delay. FULL calibration performed without
671  -- averaging algorithm turned ON during window detection.
672  -- "SKIP" = skip power-up delay. Skip calibration not yet supported.
673  -- "FAST" = skip power-up delay, and calibrate (read leveling, write
674  -- leveling, and phase detector) only using one DQS group, and
675  -- apply the results to all other DQS groups.
676  constant SIM_INIT_OPTION : string := SIM_INIT_OPTION_W;
677  constant SIM_CAL_OPTION : string := SIM_CAL_OPTION_W;
678  constant WRLVL_W : string := CALC_WRLVL_W;
679 
680  constant HIGHEST_BANK : integer := HIGHEST_BANK_W;
681 
682  -- constant HIGHEST_LANE_B0 = HIGHEST_LANE_B0_W;
683  -- constant HIGHEST_LANE_B1 = HIGHEST_LANE_B1_W;
684  -- constant HIGHEST_LANE_B2 = HIGHEST_LANE_B2_W;
685  -- constant HIGHEST_LANE_B3 = HIGHEST_LANE_B3_W;
686  -- constant HIGHEST_LANE_B4 = HIGHEST_LANE_B4_W;
687 
688  constant HIGHEST_LANE : integer := HIGHEST_LANE_W;
689 
690  constant N_CTL_LANES : integer := N_CTL_LANES_B0 + N_CTL_LANES_B1 + N_CTL_LANES_B2 + N_CTL_LANES_B3 + N_CTL_LANES_B4;
691 
692  -- Assuming Ck/Addr/Cmd and Control are placed in a single IO Bank
693  -- This should be the case since the PLL should be placed adjacent
694  -- to the same IO Bank as Ck/Addr/Cmd and Control
695  constant CTL_BANK : std_logic_vector(2 downto 0):= CTL_BANK_W;
696 
697  function CTL_BYTE_LANE_W return std_logic_vector is
698  variable ctl_byte_lane_var: std_logic_vector(7 downto 0);
699  begin
700  if (N_CTL_LANES = 4) then
701  ctl_byte_lane_var := "11100100";
702  elsif (N_CTL_LANES = 3 and
703  (((not(DATA_CTL_B0(0)) = '1') and BYTE_LANES_B0(0) = '1' and
704  (not(DATA_CTL_B0(1)) = '1') and BYTE_LANES_B0(1) = '1' and
705  (not(DATA_CTL_B0(2)) = '1') and BYTE_LANES_B0(2) = '1') or
706  ((not(DATA_CTL_B1(0)) = '1') and BYTE_LANES_B1(0) = '1' and
707  (not(DATA_CTL_B1(1)) = '1') and BYTE_LANES_B1(1) = '1' and
708  (not(DATA_CTL_B1(2)) = '1') and BYTE_LANES_B1(2) = '1') or
709  ((not(DATA_CTL_B2(0)) = '1') and BYTE_LANES_B2(0) = '1' and
710  (not(DATA_CTL_B2(1)) = '1') and BYTE_LANES_B2(1) = '1' and
711  (not(DATA_CTL_B2(2)) = '1') and BYTE_LANES_B2(2) = '1') or
712  ((not(DATA_CTL_B3(0)) = '1') and BYTE_LANES_B3(0) = '1' and
713  (not(DATA_CTL_B3(1)) = '1') and BYTE_LANES_B3(1) = '1' and
714  (not(DATA_CTL_B3(2)) = '1') and BYTE_LANES_B3(2) = '1') or
715  ((not(DATA_CTL_B4(0)) = '1') and BYTE_LANES_B4(0) = '1' and
716  (not(DATA_CTL_B4(1)) = '1') and BYTE_LANES_B4(1) = '1' and
717  (not(DATA_CTL_B4(2)) = '1') and BYTE_LANES_B4(2) = '1'))) then
718  ctl_byte_lane_var := "00100100";
719  elsif (N_CTL_LANES = 3 and
720  (((not(DATA_CTL_B0(0)) = '1') and BYTE_LANES_B0(0) = '1' and
721  (not(DATA_CTL_B0(1)) = '1') and BYTE_LANES_B0(1) = '1' and
722  (not(DATA_CTL_B0(3)) = '1') and BYTE_LANES_B0(3) = '1') or
723  ((not(DATA_CTL_B1(0)) = '1') and BYTE_LANES_B1(0) = '1' and
724  (not(DATA_CTL_B1(1)) = '1') and BYTE_LANES_B1(1) = '1' and
725  (not(DATA_CTL_B1(3)) = '1') and BYTE_LANES_B1(3) = '1') or
726  ((not(DATA_CTL_B2(0)) = '1') and BYTE_LANES_B2(0) = '1' and
727  (not(DATA_CTL_B2(1)) = '1') and BYTE_LANES_B2(1) = '1' and
728  (not(DATA_CTL_B2(3)) = '1') and BYTE_LANES_B2(3) = '1') or
729  ((not(DATA_CTL_B3(0)) = '1') and BYTE_LANES_B3(0) = '1' and
730  (not(DATA_CTL_B3(1)) = '1') and BYTE_LANES_B3(1) = '1' and
731  (not(DATA_CTL_B3(3)) = '1') and BYTE_LANES_B3(3) = '1') or
732  ((not(DATA_CTL_B4(0)) = '1') and BYTE_LANES_B4(0) = '1' and
733  (not(DATA_CTL_B4(1)) = '1') and BYTE_LANES_B4(1) = '1' and
734  (not(DATA_CTL_B4(3)) = '1') and BYTE_LANES_B4(3) = '1'))) then
735  ctl_byte_lane_var := "00110100";
736  elsif (N_CTL_LANES = 3 and
737  (((not(DATA_CTL_B0(0)) = '1') and BYTE_LANES_B0(0) = '1' and
738  (not(DATA_CTL_B0(2)) = '1') and BYTE_LANES_B0(2) = '1' and
739  (not(DATA_CTL_B0(3)) = '1') and BYTE_LANES_B0(3) = '1') or
740  ((not(DATA_CTL_B1(0)) = '1') and BYTE_LANES_B1(0) = '1' and
741  (not(DATA_CTL_B1(2)) = '1') and BYTE_LANES_B1(2) = '1' and
742  (not(DATA_CTL_B1(3)) = '1') and BYTE_LANES_B1(3) = '1') or
743  ((not(DATA_CTL_B2(0)) = '1') and BYTE_LANES_B2(0) = '1' and
744  (not(DATA_CTL_B2(2)) = '1') and BYTE_LANES_B2(2) = '1' and
745  (not(DATA_CTL_B2(3)) = '1') and BYTE_LANES_B2(3) = '1') or
746  ((not(DATA_CTL_B3(0)) = '1') and BYTE_LANES_B3(0) = '1' and
747  (not(DATA_CTL_B3(2)) = '1') and BYTE_LANES_B3(2) = '1' and
748  (not(DATA_CTL_B3(3)) = '1') and BYTE_LANES_B3(3) = '1') or
749  ((not(DATA_CTL_B4(0)) = '1') and BYTE_LANES_B4(0) = '1' and
750  (not(DATA_CTL_B4(2)) = '1') and BYTE_LANES_B4(2) = '1' and
751  (not(DATA_CTL_B4(3)) = '1') and BYTE_LANES_B4(3) = '1'))) then
752  ctl_byte_lane_var := "00111000";
753  elsif (N_CTL_LANES = 3 and
754  (((not(DATA_CTL_B0(0)) = '1') and BYTE_LANES_B0(0) = '1' and
755  (not(DATA_CTL_B0(2)) = '1') and BYTE_LANES_B0(2) = '1' and
756  (not(DATA_CTL_B0(3)) = '1') and BYTE_LANES_B0(3) = '1') or
757  ((not(DATA_CTL_B1(0)) = '1') and BYTE_LANES_B1(0) = '1' and
758  (not(DATA_CTL_B1(2)) = '1') and BYTE_LANES_B1(2) = '1' and
759  (not(DATA_CTL_B1(3)) = '1') and BYTE_LANES_B1(3) = '1') or
760  ((not(DATA_CTL_B2(0)) = '1') and BYTE_LANES_B2(0) = '1' and
761  (not(DATA_CTL_B2(2)) = '1') and BYTE_LANES_B2(2) = '1' and
762  (not(DATA_CTL_B2(3)) = '1') and BYTE_LANES_B2(3) = '1') or
763  ((not(DATA_CTL_B3(0)) = '1') and BYTE_LANES_B3(0) = '1' and
764  (not(DATA_CTL_B3(2)) = '1') and BYTE_LANES_B3(2) = '1' and
765  (not(DATA_CTL_B3(3)) = '1') and BYTE_LANES_B3(3) = '1') or
766  ((not(DATA_CTL_B4(0)) = '1') and BYTE_LANES_B4(0) = '1' and
767  (not(DATA_CTL_B4(2)) = '1') and BYTE_LANES_B4(2) = '1' and
768  (not(DATA_CTL_B4(3)) = '1') and BYTE_LANES_B4(3) = '1'))) then
769  ctl_byte_lane_var := "00111001";
770  elsif (N_CTL_LANES = 2 and
771  (((not(DATA_CTL_B0(0)) = '1') and BYTE_LANES_B0(0) = '1' and
772  (not(DATA_CTL_B0(1)) = '1') and BYTE_LANES_B0(1) = '1') or
773  ((not(DATA_CTL_B1(0)) = '1') and BYTE_LANES_B1(0) = '1' and
774  (not(DATA_CTL_B1(1)) = '1') and BYTE_LANES_B1(1) = '1') or
775  ((not(DATA_CTL_B2(0)) = '1') and BYTE_LANES_B2(0) = '1' and
776  (not(DATA_CTL_B2(1)) = '1') and BYTE_LANES_B2(1) = '1') or
777  ((not(DATA_CTL_B3(0)) = '1') and BYTE_LANES_B3(0) = '1' and
778  (not(DATA_CTL_B3(1)) = '1') and BYTE_LANES_B3(1) = '1') or
779  ((not(DATA_CTL_B4(0)) = '1') and BYTE_LANES_B4(0) = '1' and
780  (not(DATA_CTL_B4(1)) = '1') and BYTE_LANES_B4(1) = '1'))) then
781  ctl_byte_lane_var := "00000100";
782  elsif (N_CTL_LANES = 2 and
783  (((not(DATA_CTL_B0(0)) = '1') and BYTE_LANES_B0(0) = '1' and
784  (not(DATA_CTL_B0(3)) = '1') and BYTE_LANES_B0(3) = '1') or
785  ((not(DATA_CTL_B1(0)) = '1') and BYTE_LANES_B1(0) = '1' and
786  (not(DATA_CTL_B1(3)) = '1') and BYTE_LANES_B1(3) = '1') or
787  ((not(DATA_CTL_B2(0)) = '1') and BYTE_LANES_B2(0) = '1' and
788  (not(DATA_CTL_B2(3)) = '1') and BYTE_LANES_B2(3) = '1') or
789  ((not(DATA_CTL_B3(0)) = '1') and BYTE_LANES_B3(0) = '1' and
790  (not(DATA_CTL_B3(3)) = '1') and BYTE_LANES_B3(3) = '1') or
791  ((not(DATA_CTL_B4(0)) = '1') and BYTE_LANES_B4(0) = '1' and
792  (not(DATA_CTL_B4(3)) = '1') and BYTE_LANES_B4(3) = '1'))) then
793  ctl_byte_lane_var := "00001100";
794  elsif (N_CTL_LANES = 2 and
795  (((not(DATA_CTL_B0(2)) = '1') and BYTE_LANES_B0(2) = '1' and
796  (not(DATA_CTL_B0(3)) = '1') and BYTE_LANES_B0(3) = '1') or
797  ((not(DATA_CTL_B1(2)) = '1') and BYTE_LANES_B1(2) = '1' and
798  (not(DATA_CTL_B1(3)) = '1') and BYTE_LANES_B1(3) = '1') or
799  ((not(DATA_CTL_B2(2)) = '1') and BYTE_LANES_B2(2) = '1' and
800  (not(DATA_CTL_B2(3)) = '1') and BYTE_LANES_B2(3) = '1') or
801  ((not(DATA_CTL_B3(2)) = '1') and BYTE_LANES_B3(2) = '1' and
802  (not(DATA_CTL_B3(3)) = '1') and BYTE_LANES_B3(3) = '1') or
803  ((not(DATA_CTL_B4(2)) = '1') and BYTE_LANES_B4(2) = '1' and
804  (not(DATA_CTL_B4(3)) = '1') and BYTE_LANES_B4(3) = '1'))) then
805  ctl_byte_lane_var := "00001110";
806  elsif (N_CTL_LANES = 2 and
807  (((not(DATA_CTL_B0(1)) = '1') and BYTE_LANES_B0(1) = '1' and
808  (not(DATA_CTL_B0(2)) = '1') and BYTE_LANES_B0(2) = '1') or
809  ((not(DATA_CTL_B1(1)) = '1') and BYTE_LANES_B1(1) = '1' and
810  (not(DATA_CTL_B1(2)) = '1') and BYTE_LANES_B1(2) = '1') or
811  ((not(DATA_CTL_B2(1)) = '1') and BYTE_LANES_B2(1) = '1' and
812  (not(DATA_CTL_B2(2)) = '1') and BYTE_LANES_B2(2) = '1') or
813  ((not(DATA_CTL_B3(1)) = '1') and BYTE_LANES_B3(1) = '1' and
814  (not(DATA_CTL_B3(2)) = '1') and BYTE_LANES_B3(2) = '1') or
815  ((not(DATA_CTL_B4(1)) = '1') and BYTE_LANES_B4(1) = '1' and
816  (not(DATA_CTL_B4(2)) = '1') and BYTE_LANES_B4(2) = '1'))) then
817  ctl_byte_lane_var := "00001001";
818  elsif (N_CTL_LANES = 2 and
819  (((not(DATA_CTL_B0(1)) = '1') and BYTE_LANES_B0(1) = '1' and
820  (not(DATA_CTL_B0(3)) = '1') and BYTE_LANES_B0(3) = '1') or
821  ((not(DATA_CTL_B1(1)) = '1') and BYTE_LANES_B1(1) = '1' and
822  (not(DATA_CTL_B1(3)) = '1') and BYTE_LANES_B1(3) = '1') or
823  ((not(DATA_CTL_B2(1)) = '1') and BYTE_LANES_B2(1) = '1' and
824  (not(DATA_CTL_B2(3)) = '1') and BYTE_LANES_B2(3) = '1') or
825  ((not(DATA_CTL_B3(1)) = '1') and BYTE_LANES_B3(1) = '1' and
826  (not(DATA_CTL_B3(3)) = '1') and BYTE_LANES_B3(3) = '1') or
827  ((not(DATA_CTL_B4(1)) = '1') and BYTE_LANES_B4(1) = '1' and
828  (not(DATA_CTL_B4(3)) = '1') and BYTE_LANES_B4(3) = '1'))) then
829  ctl_byte_lane_var := "00001101";
830  elsif (N_CTL_LANES = 2 and
831  (((not(DATA_CTL_B0(0)) = '1') and BYTE_LANES_B0(0) = '1' and
832  (not(DATA_CTL_B0(2)) = '1') and BYTE_LANES_B0(2) = '1') or
833  ((not(DATA_CTL_B1(0)) = '1') and BYTE_LANES_B1(0) = '1' and
834  (not(DATA_CTL_B1(2)) = '1') and BYTE_LANES_B1(2) = '1') or
835  ((not(DATA_CTL_B2(0)) = '1') and BYTE_LANES_B2(0) = '1' and
836  (not(DATA_CTL_B2(2)) = '1') and BYTE_LANES_B2(2) = '1') or
837  ((not(DATA_CTL_B3(0)) = '1') and BYTE_LANES_B3(0) = '1' and
838  (not(DATA_CTL_B3(2)) = '1') and BYTE_LANES_B3(2) = '1') or
839  ((not(DATA_CTL_B4(0)) = '1') and BYTE_LANES_B4(0) = '1' and
840  (not(DATA_CTL_B4(2)) = '1') and BYTE_LANES_B4(2) = '1'))) then
841  ctl_byte_lane_var := "00001000";
842  else
843  ctl_byte_lane_var := "11100100";
844  end if;
845  return (ctl_byte_lane_var);
846  end function;
847 
848  constant CTL_BYTE_LANE : std_logic_vector(7 downto 0):= CTL_BYTE_LANE_W;
849 
850  component mig_7series_v1_9_ddr_mc_phy_wrapper is
851  generic (
852  TCQ : integer;
853  tCK : integer;
854  BANK_TYPE : string;
855  DATA_IO_PRIM_TYPE : string;
856  DATA_IO_IDLE_PWRDWN :string;
857  IODELAY_GRP : string;
858  nCK_PER_CLK : integer;
859  nCS_PER_RANK : integer;
860  BANK_WIDTH : integer;
861  CKE_WIDTH : integer;
862  CS_WIDTH : integer;
863  CK_WIDTH : integer;
864  CWL : integer;
865  DDR2_DQSN_ENABLE : string;
866  DM_WIDTH : integer;
867  DQ_WIDTH : integer;
868  DQS_CNT_WIDTH : integer;
869  DQS_WIDTH : integer;
870  DRAM_TYPE : string;
871  RANKS : integer;
872  ODT_WIDTH : integer;
873  REG_CTRL : string;
874  ROW_WIDTH : integer;
875  USE_CS_PORT : integer;
876  USE_DM_PORT : integer;
877  USE_ODT_PORT : integer;
878  IBUF_LPWR_MODE : string;
879  LP_DDR_CK_WIDTH : integer;
880  PHYCTL_CMD_FIFO : string;
881  DATA_CTL_B0 : std_logic_vector(3 downto 0);
882  DATA_CTL_B1 : std_logic_vector(3 downto 0);
883  DATA_CTL_B2 : std_logic_vector(3 downto 0);
884  DATA_CTL_B3 : std_logic_vector(3 downto 0);
885  DATA_CTL_B4 : std_logic_vector(3 downto 0);
886  BYTE_LANES_B0 : std_logic_vector(3 downto 0);
887  BYTE_LANES_B1 : std_logic_vector(3 downto 0);
888  BYTE_LANES_B2 : std_logic_vector(3 downto 0);
889  BYTE_LANES_B3 : std_logic_vector(3 downto 0);
890  BYTE_LANES_B4 : std_logic_vector(3 downto 0);
891  PHY_0_BITLANES : std_logic_vector(47 downto 0);
892  PHY_1_BITLANES : std_logic_vector(47 downto 0);
893  PHY_2_BITLANES : std_logic_vector(47 downto 0);
894  HIGHEST_BANK : integer;
895  HIGHEST_LANE : integer;
896  CK_BYTE_MAP : std_logic_vector(143 downto 0);
897  ADDR_MAP : std_logic_vector(191 downto 0);
898  BANK_MAP : std_logic_vector(35 downto 0);
899  CAS_MAP : std_logic_vector(11 downto 0);
900  CKE_ODT_BYTE_MAP : std_logic_vector(7 downto 0);
901  CKE_MAP : std_logic_vector(95 downto 0);
902  ODT_MAP : std_logic_vector(95 downto 0);
903  CKE_ODT_AUX : string;
904  CS_MAP : std_logic_vector(119 downto 0);
905  PARITY_MAP : std_logic_vector(11 downto 0);
906  RAS_MAP : std_logic_vector(11 downto 0);
907  WE_MAP : std_logic_vector(11 downto 0);
908  DQS_BYTE_MAP : std_logic_vector(143 downto 0);
909  DATA0_MAP : std_logic_vector(95 downto 0);
910  DATA1_MAP : std_logic_vector(95 downto 0);
911  DATA2_MAP : std_logic_vector(95 downto 0);
912  DATA3_MAP : std_logic_vector(95 downto 0);
913  DATA4_MAP : std_logic_vector(95 downto 0);
914  DATA5_MAP : std_logic_vector(95 downto 0);
915  DATA6_MAP : std_logic_vector(95 downto 0);
916  DATA7_MAP : std_logic_vector(95 downto 0);
917  DATA8_MAP : std_logic_vector(95 downto 0);
918  DATA9_MAP : std_logic_vector(95 downto 0);
919  DATA10_MAP : std_logic_vector(95 downto 0);
920  DATA11_MAP : std_logic_vector(95 downto 0);
921  DATA12_MAP : std_logic_vector(95 downto 0);
922  DATA13_MAP : std_logic_vector(95 downto 0);
923  DATA14_MAP : std_logic_vector(95 downto 0);
924  DATA15_MAP : std_logic_vector(95 downto 0);
925  DATA16_MAP : std_logic_vector(95 downto 0);
926  DATA17_MAP : std_logic_vector(95 downto 0);
927  MASK0_MAP : std_logic_vector(107 downto 0);
928  MASK1_MAP : std_logic_vector(107 downto 0);
929  SIM_CAL_OPTION : string;
930  MASTER_PHY_CTL : integer
931  );
932  port (
933  rst : in std_logic;
934  clk : in std_logic;
935  freq_refclk : in std_logic;
936  mem_refclk : in std_logic;
937  pll_lock : in std_logic;
938  sync_pulse : in std_logic;
939  idelayctrl_refclk : in std_logic;
940  phy_cmd_wr_en : in std_logic;
941  phy_data_wr_en : in std_logic;
942  phy_ctl_wd : in std_logic_vector(31 downto 0);
943  phy_ctl_wr : in std_logic;
944  phy_if_empty_def : in std_logic;
945  phy_if_reset : in std_logic;
946  data_offset_1 : in std_logic_vector(5 downto 0);
947  data_offset_2 : in std_logic_vector(5 downto 0);
948  aux_in_1 : in std_logic_vector(3 downto 0);
949  aux_in_2 : in std_logic_vector(3 downto 0);
950  idelaye2_init_val : out std_logic_vector(4 downto 0);
951  oclkdelay_init_val : out std_logic_vector(5 downto 0);
952  if_empty : out std_logic;
953  phy_ctl_full : out std_logic;
954  phy_cmd_full : out std_logic;
955  phy_data_full : out std_logic;
956  phy_pre_data_a_full : out std_logic;
957  ddr_clk : out std_logic_vector(CK_WIDTH*LP_DDR_CK_WIDTH-1 downto 0);
958  phy_mc_go : out std_logic;
959  phy_write_calib : in std_logic;
960  phy_read_calib : in std_logic;
961  calib_in_common : in std_logic;
962  calib_sel : in std_logic_vector(5 downto 0);
963  calib_zero_inputs : in std_logic_vector(HIGHEST_BANK-1 downto 0);
964  calib_zero_ctrl : in std_logic_vector(HIGHEST_BANK-1 downto 0);
965  po_fine_enable : in std_logic_vector(2 downto 0);
966  po_coarse_enable : in std_logic_vector(2 downto 0);
967  po_fine_inc : in std_logic_vector(2 downto 0);
968  po_coarse_inc : in std_logic_vector(2 downto 0);
969  po_counter_load_en : in std_logic;
970  po_counter_read_en : in std_logic;
971  po_sel_fine_oclk_delay : in std_logic_vector(2 downto 0);
972  po_counter_load_val : in std_logic_vector(8 downto 0);
973  po_counter_read_val : out std_logic_vector(8 downto 0);
974  pi_counter_read_val : out std_logic_vector(5 downto 0);
975  pi_rst_dqs_find : in std_logic_vector(HIGHEST_BANK-1 downto 0);
976  pi_fine_enable : in std_logic;
977  pi_fine_inc : in std_logic;
978  pi_counter_load_en : in std_logic;
979  pi_counter_load_val : in std_logic_vector(5 downto 0);
980  idelay_ce : in std_logic;
981  idelay_inc : in std_logic;
982  idelay_ld : in std_logic;
983  idle : in std_logic;
984  pi_phase_locked : out std_logic;
985  pi_phase_locked_all : out std_logic;
986  pi_dqs_found : out std_logic;
987  pi_dqs_found_all : out std_logic;
988  pi_dqs_out_of_range : out std_logic;
989  phy_init_data_sel : in std_logic;
990  mux_address : in std_logic_vector(nCK_PER_CLK*ROW_WIDTH-1 downto 0);
991  mux_bank : in std_logic_vector(nCK_PER_CLK*BANK_WIDTH-1 downto 0);
992  mux_cas_n : in std_logic_vector(nCK_PER_CLK-1 downto 0);
993  mux_cs_n : in std_logic_vector(CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1 downto 0);
994  mux_ras_n : in std_logic_vector(nCK_PER_CLK-1 downto 0);
995  mux_odt : in std_logic_vector(1 downto 0);
996  mux_cke : in std_logic_vector(nCK_PER_CLK-1 downto 0);
997  mux_we_n : in std_logic_vector(nCK_PER_CLK-1 downto 0);
998  parity_in : in std_logic_vector(nCK_PER_CLK-1 downto 0);
999  mux_wrdata : in std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0);
1000  mux_wrdata_mask : in std_logic_vector(2*nCK_PER_CLK*(DQ_WIDTH/8)-1 downto 0);
1001  mux_reset_n : in std_logic;
1002  rd_data : out std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0);
1003  ddr_addr : out std_logic_vector(ROW_WIDTH-1 downto 0);
1004  ddr_ba : out std_logic_vector(BANK_WIDTH-1 downto 0);
1005  ddr_cas_n : out std_logic;
1006  ddr_cke : out std_logic_vector(CKE_WIDTH-1 downto 0);
1007  ddr_cs_n : out std_logic_vector(CS_WIDTH*nCS_PER_RANK-1 downto 0);
1008  ddr_dm : out std_logic_vector(DM_WIDTH-1 downto 0);
1009  ddr_odt : out std_logic_vector(ODT_WIDTH-1 downto 0);
1010  ddr_parity : out std_logic;
1011  ddr_ras_n : out std_logic;
1012  ddr_we_n : out std_logic;
1013  ddr_reset_n : out std_logic;
1014  ddr_dq : inout std_logic_vector(DQ_WIDTH-1 downto 0);
1015  ddr_dqs : inout std_logic_vector(DQS_WIDTH-1 downto 0);
1016  ddr_dqs_n : inout std_logic_vector(DQS_WIDTH-1 downto 0);
1017  dbg_pi_counter_read_en : in std_logic;
1018  ref_dll_lock : out std_logic;
1019  rst_phaser_ref : in std_logic;
1020  dbg_pi_phase_locked_phy4lanes : out std_logic_vector(11 downto 0);
1021  dbg_pi_dqs_found_lanes_phy4lanes : out std_logic_vector(11 downto 0)
1022  );
1023  end component mig_7series_v1_9_ddr_mc_phy_wrapper;
1024 
1025  component mig_7series_v1_9_ddr_calib_top is
1026  generic (
1027  TCQ : integer;
1028  nCK_PER_CLK : integer;
1029  tCK : integer;
1030  CLK_PERIOD : integer;
1031  N_CTL_LANES : integer;
1032  DRAM_TYPE : string;
1033  PRBS_WIDTH : integer;
1034  HIGHEST_LANE : integer;
1035  HIGHEST_BANK : integer;
1036  BANK_TYPE : string;
1037  BYTE_LANES_B0 : std_logic_vector(3 downto 0);
1038  BYTE_LANES_B1 : std_logic_vector(3 downto 0);
1039  BYTE_LANES_B2 : std_logic_vector(3 downto 0);
1040  BYTE_LANES_B3 : std_logic_vector(3 downto 0);
1041  BYTE_LANES_B4 : std_logic_vector(3 downto 0);
1042  DATA_CTL_B0 : std_logic_vector(3 downto 0);
1043  DATA_CTL_B1 : std_logic_vector(3 downto 0);
1044  DATA_CTL_B2 : std_logic_vector(3 downto 0);
1045  DATA_CTL_B3 : std_logic_vector(3 downto 0);
1046  DATA_CTL_B4 : std_logic_vector(3 downto 0);
1047  DQS_BYTE_MAP : std_logic_vector(143 downto 0);
1048  CTL_BYTE_LANE : std_logic_vector(7 downto 0);
1049  CTL_BANK : std_logic_vector(2 downto 0);
1050  SLOT_1_CONFIG : std_logic_vector(7 downto 0);
1051  BANK_WIDTH : integer;
1052  CA_MIRROR : string;
1053  COL_WIDTH : integer;
1054  nCS_PER_RANK : integer;
1055  DQ_WIDTH : integer;
1056  DQS_CNT_WIDTH : integer;
1057  DQS_WIDTH : integer;
1058  DRAM_WIDTH : integer;
1059  ROW_WIDTH : integer;
1060  RANKS : integer;
1061  CS_WIDTH : integer;
1062  CKE_WIDTH : integer;
1063  DDR2_DQSN_ENABLE : string;
1064  PER_BIT_DESKEW : string;
1065  CALIB_ROW_ADD : std_logic_vector(15 downto 0);
1066  CALIB_COL_ADD : std_logic_vector(11 downto 0);
1067  CALIB_BA_ADD : std_logic_vector(2 downto 0);
1068  AL : string;
1069  ADDR_CMD_MODE : string;
1070  BURST_MODE : string;
1071  BURST_TYPE : string;
1072  nCL : integer;
1073  nCWL : integer;
1074  tRFC : integer;
1075  OUTPUT_DRV : string;
1076  REG_CTRL : string;
1077  RTT_NOM : string;
1078  RTT_WR : string;
1079  USE_ODT_PORT : integer;
1080  WRLVL : string;
1081  PRE_REV3ES : string;
1082  SIM_INIT_OPTION : string;
1083  SIM_CAL_OPTION : string;
1084  CKE_ODT_AUX : string;
1085  DEBUG_PORT : string
1086  );
1087  port (
1088  clk : in std_logic;
1089  rst : in std_logic;
1090  slot_0_present : in std_logic_vector(7 downto 0);
1091  slot_1_present : in std_logic_vector(7 downto 0);
1092  phy_ctl_ready : in std_logic;
1093  phy_ctl_full : in std_logic;
1094  phy_cmd_full : in std_logic;
1095  phy_data_full : in std_logic;
1096  write_calib : out std_logic;
1097  read_calib : out std_logic;
1098  calib_ctl_wren : out std_logic;
1099  calib_cmd_wren : out std_logic;
1100  calib_seq : out std_logic_vector(1 downto 0);
1101  calib_aux_out : out std_logic_vector(3 downto 0);
1102  calib_cke : out std_logic_vector(nCK_PER_CLK-1 downto 0);
1103  calib_odt : out std_logic_vector(1 downto 0);
1104  calib_cmd : out std_logic_vector(2 downto 0);
1105  calib_wrdata_en : out std_logic;
1106  calib_rank_cnt : out std_logic_vector(1 downto 0);
1107  calib_cas_slot : out std_logic_vector(1 downto 0);
1108  calib_data_offset_0 : out std_logic_vector(5 downto 0);
1109  calib_data_offset_1 : out std_logic_vector(5 downto 0);
1110  calib_data_offset_2 : out std_logic_vector(5 downto 0);
1111  phy_address : out std_logic_vector(nCK_PER_CLK*ROW_WIDTH-1 downto 0);
1112  phy_bank : out std_logic_vector(nCK_PER_CLK*BANK_WIDTH-1 downto 0);
1113  phy_cs_n : out std_logic_vector(CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1 downto 0);
1114  phy_ras_n : out std_logic_vector(nCK_PER_CLK-1 downto 0);
1115  phy_cas_n : out std_logic_vector(nCK_PER_CLK-1 downto 0);
1116  phy_we_n : out std_logic_vector(nCK_PER_CLK-1 downto 0);
1117  phy_reset_n : out std_logic;
1118  calib_sel : out std_logic_vector(5 downto 0);
1119  calib_in_common : out std_logic;
1120  calib_zero_inputs : out std_logic_vector(HIGHEST_BANK-1 downto 0);
1121  calib_zero_ctrl : out std_logic_vector(HIGHEST_BANK-1 downto 0);
1122  phy_if_empty_def : out std_logic;
1123  phy_if_reset : out std_logic;
1124  pi_phaselocked : in std_logic;
1125  pi_phase_locked_all : in std_logic;
1126  pi_found_dqs : in std_logic;
1127  pi_dqs_found_all : in std_logic;
1128  pi_dqs_found_lanes : in std_logic_vector(HIGHEST_LANE-1 downto 0);
1129  pi_counter_read_val : in std_logic_vector(5 downto 0);
1130  pi_rst_stg1_cal : out std_logic_vector(HIGHEST_BANK-1 downto 0);
1131  pi_en_stg2_f : out std_logic;
1132  pi_stg2_f_incdec : out std_logic;
1133  pi_stg2_load : out std_logic;
1134  pi_stg2_reg_l : out std_logic_vector(5 downto 0);
1135  idelay_ce : out std_logic;
1136  idelay_inc : out std_logic;
1137  idelay_ld : out std_logic;
1138  po_sel_stg2stg3 : out std_logic_vector(2 downto 0);
1139  po_stg2_c_incdec : out std_logic_vector(2 downto 0);
1140  po_en_stg2_c : out std_logic_vector(2 downto 0);
1141  po_stg2_f_incdec : out std_logic_vector(2 downto 0);
1142  po_en_stg2_f : out std_logic_vector(2 downto 0);
1143  po_counter_load_en : out std_logic;
1144  po_counter_read_val : in std_logic_vector(8 downto 0);
1145  device_temp : in std_logic_vector(11 downto 0);
1146  tempmon_sample_en : in std_logic;
1147  phy_if_empty : in std_logic;
1148  idelaye2_init_val : in std_logic_vector(4 downto 0);
1149  oclkdelay_init_val : in std_logic_vector(5 downto 0);
1150  tg_err : in std_logic;
1151  rst_tg_mc : out std_logic;
1152  phy_wrdata : out std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0);
1153  dlyval_dq : out std_logic_vector(5*RANKS*DQ_WIDTH-1 downto 0);
1154  phy_rddata : in std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0);
1155  calib_rd_data_offset_0 : out std_logic_vector(6*RANKS-1 downto 0);
1156  calib_rd_data_offset_1 : out std_logic_vector(6*RANKS-1 downto 0);
1157  calib_rd_data_offset_2 : out std_logic_vector(6*RANKS-1 downto 0);
1158  phy_rddata_valid : out std_logic;
1159  calib_writes : out std_logic;
1160  init_calib_complete : out std_logic;
1161  init_wrcal_complete : out std_logic;
1162  pi_phase_locked_err : out std_logic;
1163  pi_dqsfound_err : out std_logic;
1164  wrcal_err : out std_logic;
1165  dbg_pi_phaselock_start : out std_logic;
1166  dbg_pi_dqsfound_start : out std_logic;
1167  dbg_pi_dqsfound_done : out std_logic;
1168  dbg_wrcal_start : out std_logic;
1169  dbg_wrcal_done : out std_logic;
1170  dbg_wrlvl_start : out std_logic;
1171  dbg_wrlvl_done : out std_logic;
1172  dbg_wrlvl_err : out std_logic;
1173  dbg_wrlvl_fine_tap_cnt : out std_logic_vector(6*DQS_WIDTH-1 downto 0);
1174  dbg_wrlvl_coarse_tap_cnt : out std_logic_vector(3*DQS_WIDTH-1 downto 0);
1175  dbg_phy_wrlvl : out std_logic_vector(255 downto 0);
1176  dbg_tap_cnt_during_wrlvl : out std_logic_vector(5 downto 0);
1177  dbg_wl_edge_detect_valid : out std_logic;
1178  dbg_rd_data_edge_detect : out std_logic_vector(DQS_WIDTH-1 downto 0);
1179  dbg_final_po_fine_tap_cnt : out std_logic_vector(6*DQS_WIDTH-1 downto 0);
1180  dbg_final_po_coarse_tap_cnt : out std_logic_vector(3*DQS_WIDTH-1 downto 0);
1181  dbg_phy_wrcal : out std_logic_vector(99 downto 0);
1182  dbg_rdlvl_start : out std_logic_vector(1 downto 0);
1183  dbg_rdlvl_done : out std_logic_vector(1 downto 0);
1184  dbg_rdlvl_err : out std_logic_vector(1 downto 0);
1185  dbg_cpt_first_edge_cnt : out std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0);
1186  dbg_cpt_second_edge_cnt : out std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0);
1187  dbg_cpt_tap_cnt : out std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0);
1188  dbg_dq_idelay_tap_cnt : out std_logic_vector(5*DQS_WIDTH*RANKS-1 downto 0);
1189  dbg_sel_pi_incdec : in std_logic;
1190  dbg_sel_po_incdec : in std_logic;
1191  dbg_byte_sel : in std_logic_vector(DQS_CNT_WIDTH downto 0);
1192  dbg_pi_f_inc : in std_logic;
1193  dbg_pi_f_dec : in std_logic;
1194  dbg_po_f_inc : in std_logic;
1195  dbg_po_f_stg23_sel : in std_logic;
1196  dbg_po_f_dec : in std_logic;
1197  dbg_idel_up_all : in std_logic;
1198  dbg_idel_down_all : in std_logic;
1199  dbg_idel_up_cpt : in std_logic;
1200  dbg_idel_down_cpt : in std_logic;
1201  dbg_sel_idel_cpt : in std_logic_vector(DQS_CNT_WIDTH-1 downto 0);
1202  dbg_sel_all_idel_cpt : in std_logic;
1203  dbg_phy_rdlvl : out std_logic_vector(255 downto 0);
1204  dbg_calib_top : out std_logic_vector(255 downto 0);
1205  dbg_phy_init : out std_logic_vector(255 downto 0);
1206  dbg_prbs_rdlvl : out std_logic_vector(255 downto 0);
1207  dbg_dqs_found_cal : out std_logic_vector(255 downto 0);
1208  dbg_phy_oclkdelay_cal : out std_logic_vector(255 downto 0);
1209  dbg_oclkdelay_rd_data : out std_logic_vector(DRAM_WIDTH*16-1 downto 0);
1210  dbg_oclkdelay_calib_start : out std_logic;
1211  dbg_oclkdelay_calib_done : out std_logic
1212  );
1213  end component mig_7series_v1_9_ddr_calib_top;
1214 
1215  signal phy_din : std_logic_vector(HIGHEST_LANE*80-1 downto 0);
1216  signal phy_dout : std_logic_vector(HIGHEST_LANE*80-1 downto 0);
1217  signal ddr_cmd_ctl_data : std_logic_vector(HIGHEST_LANE*12-1 downto 0);
1218  signal aux_out : std_logic_vector((((HIGHEST_LANE+3)/4)*4)-1 downto 0);
1219  signal ddr_clk : std_logic_vector(CK_WIDTH * LP_DDR_CK_WIDTH-1 downto 0);
1220  signal phy_mc_go : std_logic;
1221  signal phy_ctl_full : std_logic;
1222  signal phy_cmd_full : std_logic;
1223  signal phy_data_full : std_logic;
1224  signal phy_pre_data_a_full : std_logic;
1225  signal if_empty : std_logic;
1226  signal phy_write_calib : std_logic;
1227  signal phy_read_calib : std_logic;
1228  signal rst_stg1_cal : std_logic_vector(HIGHEST_BANK-1 downto 0);
1229  signal calib_sel : std_logic_vector(5 downto 0);
1230  signal calib_in_common : std_logic;
1231  signal calib_zero_inputs : std_logic_vector(HIGHEST_BANK-1 downto 0);
1232  signal calib_zero_ctrl : std_logic_vector(HIGHEST_BANK-1 downto 0);
1233  signal pi_phase_locked : std_logic;
1234  signal pi_phase_locked_all : std_logic;
1235  signal pi_found_dqs : std_logic;
1236  signal pi_dqs_found_all : std_logic;
1237  signal pi_dqs_out_of_range : std_logic;
1238  signal pi_enstg2_f : std_logic;
1239  signal pi_stg2_fincdec : std_logic;
1240  signal pi_stg2_load : std_logic;
1241  signal pi_stg2_reg_l : std_logic_vector(5 downto 0);
1242  signal idelay_ce : std_logic;
1243  signal idelay_inc : std_logic;
1244  signal idelay_ld : std_logic;
1245  signal po_sel_stg2stg3 : std_logic_vector(2 downto 0);
1246  signal po_stg2_cincdec : std_logic_vector(2 downto 0);
1247  signal po_enstg2_c : std_logic_vector(2 downto 0);
1248  signal po_stg2_fincdec : std_logic_vector(2 downto 0);
1249  signal po_enstg2_f : std_logic_vector(2 downto 0);
1250  signal po_counter_read_val : std_logic_vector(8 downto 0);
1251  signal pi_counter_read_val : std_logic_vector(5 downto 0);
1252  signal phy_wrdata : std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0);
1253  signal parity : std_logic_vector(nCK_PER_CLK-1 downto 0);
1254  signal phy_address : std_logic_vector(nCK_PER_CLK*ROW_WIDTH-1 downto 0);
1255  signal phy_bank : std_logic_vector(nCK_PER_CLK*BANK_WIDTH-1 downto 0);
1256  signal phy_cs_n : std_logic_vector(CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1 downto 0);
1257  signal phy_ras_n : std_logic_vector(nCK_PER_CLK-1 downto 0);
1258  signal phy_cas_n : std_logic_vector(nCK_PER_CLK-1 downto 0);
1259  signal phy_we_n : std_logic_vector(nCK_PER_CLK-1 downto 0);
1260  signal phy_reset_n : std_logic;
1261  signal calib_aux_out : std_logic_vector(3 downto 0);
1262  signal calib_cke : std_logic_vector(nCK_PER_CLK-1 downto 0);
1263  signal calib_odt : std_logic_vector(1 downto 0);
1264  signal calib_ctl_wren : std_logic;
1265  signal calib_cmd_wren : std_logic;
1266  signal calib_wrdata_en : std_logic;
1267  signal calib_cmd : std_logic_vector(2 downto 0);
1268  signal calib_seq : std_logic_vector(1 downto 0);
1269  signal calib_data_offset_0 : std_logic_vector(5 downto 0);
1270  signal calib_data_offset_1 : std_logic_vector(5 downto 0);
1271  signal calib_data_offset_2 : std_logic_vector(5 downto 0);
1272  signal calib_rank_cnt : std_logic_vector(1 downto 0);
1273  signal calib_cas_slot : std_logic_vector(1 downto 0);
1274  signal mux_address : std_logic_vector(nCK_PER_CLK*ROW_WIDTH-1 downto 0);
1275  signal mux_aux_out : std_logic_vector(3 downto 0);
1276  signal aux_out_map : std_logic_vector(3 downto 0);
1277  signal mux_bank : std_logic_vector(nCK_PER_CLK*BANK_WIDTH-1 downto 0);
1278  signal mux_cmd : std_logic_vector(2 downto 0);
1279  signal mux_cmd_wren : std_logic;
1280  signal mux_cs_n : std_logic_vector(CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1 downto 0);
1281  signal mux_ctl_wren : std_logic;
1282  signal mux_cas_slot : std_logic_vector(1 downto 0);
1283  signal mux_data_offset : std_logic_vector(5 downto 0);
1284  signal mux_data_offset_1 : std_logic_vector(5 downto 0);
1285  signal mux_data_offset_2 : std_logic_vector(5 downto 0);
1286  signal mux_ras_n : std_logic_vector(nCK_PER_CLK-1 downto 0);
1287  signal mux_cas_n : std_logic_vector(nCK_PER_CLK-1 downto 0);
1288  signal mux_rank_cnt : std_logic_vector(1 downto 0);
1289  signal mux_reset_n : std_logic;
1290  signal mux_we_n : std_logic_vector(nCK_PER_CLK-1 downto 0);
1291  signal mux_wrdata : std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0);
1292  signal mux_wrdata_mask : std_logic_vector(2*nCK_PER_CLK*(DQ_WIDTH/8)-1 downto 0);
1293  signal mux_wrdata_en : std_logic;
1294  signal mux_cke : std_logic_vector(nCK_PER_CLK-1 downto 0);
1295  signal mux_odt : std_logic_vector(1 downto 0);
1296  signal phy_if_empty_def : std_logic;
1297  signal phy_if_reset : std_logic;
1298  signal phy_init_data_sel : std_logic;
1299  signal rd_data_map : std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0);
1300  signal phy_rddata_valid_w : std_logic;
1301  signal rddata_valid_reg : std_logic;
1302  signal rd_data_reg : std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0);
1303  signal idelaye2_init_val : std_logic_vector(4 downto 0);
1304  signal oclkdelay_init_val : std_logic_vector(5 downto 0);
1305 
1306  signal mc_cs_n_temp : std_logic_vector(CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1 downto 0);
1307 
1308  signal calib_rd_data_offset_i0 : std_logic_vector(6*RANKS-1 downto 0);
1309  signal init_wrcal_complete_i : std_logic;
1310  signal phy_ctl_wd_i : std_logic_vector(31 downto 0);
1311  signal po_counter_load_en : std_logic;
1312  signal parity_0_wire : std_logic_vector((ROW_WIDTH+BANK_WIDTH+3)-1 downto 0);
1313  signal parity_1_wire : std_logic_vector((ROW_WIDTH+BANK_WIDTH+3)-1 downto 0);
1314  signal parity_2_wire : std_logic_vector((ROW_WIDTH+BANK_WIDTH+3)-1 downto 0);
1315  signal parity_3_wire : std_logic_vector((ROW_WIDTH+BANK_WIDTH+3)-1 downto 0);
1316  signal dbg_pi_dqs_found_lanes_phy4lanes_i : std_logic_vector(11 downto 0);
1317  signal all_zeros : std_logic_vector(8 downto 0):= (others => '0');
1318 
1319  begin
1320 
1321  --***************************************************************************
1322 
1323  dbg_rddata_valid <= rddata_valid_reg;
1324  dbg_rddata <= rd_data_reg;
1325 
1326  dbg_rd_data_offset <= calib_rd_data_offset_i0;
1327  calib_rd_data_offset_0 <= calib_rd_data_offset_i0;
1328 
1329  dbg_pi_phaselocked_done <= pi_phase_locked_all;
1330 
1331  dbg_po_counter_read_val <= po_counter_read_val;
1332  dbg_pi_counter_read_val <= pi_counter_read_val;
1333 
1334  dbg_pi_dqs_found_lanes_phy4lanes <= dbg_pi_dqs_found_lanes_phy4lanes_i;
1335 
1336  init_wrcal_complete <= init_wrcal_complete_i;
1337 
1338  --***************************************************************************
1339 
1340  clock_gen : for i in 0 to (CK_WIDTH-1) generate
1341  ddr_ck(i) <= ddr_clk(LP_DDR_CK_WIDTH * i);
1342  ddr_ck_n(i) <= ddr_clk((LP_DDR_CK_WIDTH * i) + 1);
1343  end generate;
1344 
1345  --***************************************************************************
1346  -- During memory initialization and calibration the calibration logic drives
1347  -- the memory signals. After calibration is complete the memory controller
1348  -- drives the memory signals.
1349  -- Do not expect timing issues in 4:1 mode at 800 MHz/1600 Mbps
1350  --***************************************************************************
1351 
1352  cs_rdimm : if((REG_CTRL = "ON") and (DRAM_TYPE = "DDR3") and (RANKS = 1) and (nCS_PER_RANK = 2)) generate
1353  cs_rdimm_gen: for v in 0 to (CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK)-1 generate
1354  cs_rdimm_gen_i : if((v mod (CS_WIDTH*nCS_PER_RANK)) = 0) generate
1355  mc_cs_n_temp(v) <= mc_cs_n(v) ;
1356  end generate;
1357 
1358  cs_rdimm_gen_j : if(not((v mod (CS_WIDTH*nCS_PER_RANK)) = 0)) generate
1359  mc_cs_n_temp(v) <= '1' ;
1360  end generate;
1361 
1362  end generate;
1363  end generate;
1364 
1365  cs_others : if(not(REG_CTRL = "ON") or not(DRAM_TYPE = "DDR3") or not(RANKS = 1) or not(nCS_PER_RANK = 2)) generate
1366  mc_cs_n_temp <= mc_cs_n ;
1367  end generate;
1368 
1369  mux_wrdata <= mc_wrdata when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else phy_wrdata;
1370  mux_wrdata_mask <= mc_wrdata_mask when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else (others => '0');
1371  mux_address <= mc_address when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else phy_address;
1372  mux_bank <= mc_bank when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else phy_bank;
1373  mux_cs_n <= mc_cs_n_temp when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else phy_cs_n;
1374  mux_ras_n <= mc_ras_n when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else phy_ras_n;
1375  mux_cas_n <= mc_cas_n when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else phy_cas_n;
1376  mux_we_n <= mc_we_n when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else phy_we_n;
1377  mux_reset_n <= mc_reset_n when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else phy_reset_n;
1378  mux_aux_out <= mc_aux_out0 when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else calib_aux_out;
1379  mux_odt <= mc_odt when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else calib_odt;
1380  mux_cke <= mc_cke when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else calib_cke;
1381  mux_cmd_wren <= mc_cmd_wren when (phy_init_data_sel ='1' or init_wrcal_complete_i = '1') else calib_cmd_wren;
1382  mux_ctl_wren <= mc_ctl_wren when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else calib_ctl_wren;
1383  mux_wrdata_en <= mc_wrdata_en when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else calib_wrdata_en;
1384  mux_cmd <= mc_cmd when (phy_init_data_sel ='1' or init_wrcal_complete_i ='1') else calib_cmd;
1385  mux_cas_slot <= mc_cas_slot when (phy_init_data_sel ='1' or init_wrcal_complete_i = '1') else calib_cas_slot;
1386  mux_data_offset <= mc_data_offset when (phy_init_data_sel ='1' or init_wrcal_complete_i = '1') else calib_data_offset_0;
1387  mux_data_offset_1 <= mc_data_offset_1 when (phy_init_data_sel ='1' or init_wrcal_complete_i = '1') else calib_data_offset_1;
1388  mux_data_offset_2 <= mc_data_offset_2 when (phy_init_data_sel ='1' or init_wrcal_complete_i = '1') else calib_data_offset_2;
1389  -- Reserved field. Hard coded to 2'b00 irrespective of the number of ranks. CR 643601
1390  mux_rank_cnt <= "00";
1391 
1392 
1393  -- Assigning cke & odt for DDR2 & DDR3
1394  -- No changes for DDR3 & DDR2 dual rank
1395  -- DDR2 single rank systems might potentially need 3 odt signals.
1396  -- Aux_out[2] will have the odt toggled by phy and controller
1397  -- wiring aux_out[2] to 0 & 3. Depending upon the odt parameter
1398  -- all of the three odt bits or some of them might be used.
1399  -- mapping done in mc_phy_wrapper module
1400  aux_out_gen : if(CKE_ODT_AUX = "TRUE") generate
1401  aux_out_map <= (mux_aux_out(1) & mux_aux_out(1) & mux_aux_out(1) &
1402  mux_aux_out(0)) when ((DRAM_TYPE = "DDR2") and
1403  (RANKS = 1)) else
1404  mux_aux_out;
1405  end generate;
1406 
1407  wo_aux_out_gen : if(not(CKE_ODT_AUX = "TRUE")) generate
1408  aux_out_map <= "0000";
1409  end generate;
1410 
1411  init_calib_complete <= phy_init_data_sel;
1412 
1413  phy_mc_ctl_full <= phy_ctl_full;
1414  phy_mc_cmd_full <= phy_cmd_full;
1415  phy_mc_data_full <= phy_pre_data_a_full;
1416 
1417 
1418  --***************************************************************************
1419  -- Generate parity for DDR3 RDIMM.
1420  --***************************************************************************
1421 
1422  gen_ddr3_parity : if ((DRAM_TYPE = "DDR3") and (REG_CTRL = "ON")) generate
1423 
1424  gen_ddr3_parity_4by1: if (nCK_PER_CLK = 4) generate
1425 
1426  parity_0_wire <= (mux_address((ROW_WIDTH*4)-1 downto ROW_WIDTH*3) &
1427  mux_bank((BANK_WIDTH*4)-1 downto BANK_WIDTH*3) &
1428  mux_cas_n(3) & mux_ras_n(3) & mux_we_n(3));
1429  parity_1_wire <= (mux_address(ROW_WIDTH-1 downto 0) &
1430  mux_bank(BANK_WIDTH-1 downto 0) & mux_cas_n(0) &
1431  mux_ras_n(0) & mux_we_n(0));
1432  parity_2_wire <= (mux_address((ROW_WIDTH*2)-1 downto ROW_WIDTH) &
1433  mux_bank((BANK_WIDTH*2)-1 downto BANK_WIDTH) &
1434  mux_cas_n(1) & mux_ras_n(1) & mux_we_n(1));
1435  parity_3_wire <= (mux_address((ROW_WIDTH*3)-1 downto ROW_WIDTH*2) &
1436  mux_bank((BANK_WIDTH*3)-1 downto BANK_WIDTH*2) &
1437  mux_cas_n(2) & mux_ras_n(2) & mux_we_n(2));
1438 
1439  process (clk)
1440  begin
1441  if (clk'event and clk = '1') then
1442  parity(0) <= ODD_PARITY(parity_0_wire) after (TCQ) * 1 ps;
1443  end if;
1444  end process;
1445 
1446  process (mux_address, mux_bank, mux_cas_n, mux_ras_n, mux_we_n)
1447  begin
1448  parity(1) <= ODD_PARITY(parity_1_wire) after (TCQ) * 1 ps;
1449  parity(2) <= ODD_PARITY(parity_2_wire) after (TCQ) * 1 ps;
1450  parity(3) <= ODD_PARITY(parity_3_wire) after (TCQ) * 1 ps;
1451  end process;
1452  end generate;
1453 
1454  gen_ddr3_parity_2by1: if ( not(nCK_PER_CLK = 4)) generate
1455 
1456  parity_1_wire <= (mux_address(ROW_WIDTH-1 downto 0) &
1457  mux_bank(BANK_WIDTH-1 downto 0) & mux_cas_n(0) &
1458  mux_ras_n(0) & mux_we_n(0));
1459  parity_2_wire <= (mux_address((ROW_WIDTH*2)-1 downto ROW_WIDTH) &
1460  mux_bank((BANK_WIDTH*2)-1 downto BANK_WIDTH) &
1461  mux_cas_n(1) & mux_ras_n(1) & mux_we_n(1));
1462 
1463  process (clk)
1464  begin
1465  if (clk'event and clk='1') then
1466  parity(0) <= ODD_PARITY(parity_2_wire) after (TCQ) * 1 ps;
1467  end if;
1468  end process;
1469 
1470  process(mux_address, mux_bank, mux_cas_n, mux_ras_n, mux_we_n)
1471  begin
1472  parity(1) <= ODD_PARITY(parity_1_wire) after (TCQ) * 1 ps;
1473  end process;
1474  end generate;
1475  end generate;
1476 
1477  gen_ddr3_noparity : if (not(DRAM_TYPE = "DDR3") or not(REG_CTRL = "ON")) generate
1478  gen_ddr3_noparity_4by1 : if (nCK_PER_CLK = 4) generate
1479  process (clk)
1480  begin
1481  if (clk'event and clk='1') then
1482  parity(0) <= '0' after (TCQ)*1 ps;
1483  parity(1) <= '0' after (TCQ)*1 ps;
1484  parity(2) <= '0' after (TCQ)*1 ps;
1485  parity(3) <= '0' after (TCQ)*1 ps;
1486  end if;
1487  end process;
1488  end generate;
1489 
1490  gen_ddr3_noparity_2by1 : if (not(nCK_PER_CLK = 4)) generate
1491  process (clk)
1492  begin
1493  if (clk'event and clk='1') then
1494  parity(0) <= '0' after (TCQ)*1 ps;
1495  parity(1) <= '0' after (TCQ)*1 ps;
1496  end if;
1497  end process;
1498  end generate;
1499 
1500  end generate;
1501 
1502  --***************************************************************************
1503  -- Code for optional register stage in read path to MC for timing
1504  --***************************************************************************
1505  RD_REG_TIMING : if(RD_PATH_REG = 1) generate
1506  process (clk)
1507  begin
1508  if (clk'event and clk='1') then
1509  rddata_valid_reg <= phy_rddata_valid_w after (TCQ)*1 ps;
1510  rd_data_reg <= rd_data_map after (TCQ)*1 ps;
1511  end if;
1512  end process;
1513  end generate;
1514 
1515  RD_REG_NO_TIMING : if( not(RD_PATH_REG = 1)) generate
1516  process (phy_rddata_valid_w, rd_data_map)
1517  begin
1518  rddata_valid_reg <= phy_rddata_valid_w;
1519  rd_data_reg <= rd_data_map;
1520  end process;
1521  end generate;
1522 
1523  phy_rddata_valid <= rddata_valid_reg;
1524  phy_rd_data <= rd_data_reg;
1525 
1526  --***************************************************************************
1527  -- Hard PHY and accompanying bit mapping logic
1528  --***************************************************************************
1529 
1530  phy_ctl_wd_i <= ("00000" & mux_cas_slot & calib_seq & mux_data_offset &
1531  mux_rank_cnt & "000" & aux_out_map & "00000" & mux_cmd);
1532 
1533  u_ddr_mc_phy_wrapper : mig_7series_v1_9_ddr_mc_phy_wrapper
1534  generic map (
1535  TCQ => TCQ,
1536  tCK => tCK,
1537  BANK_TYPE => BANK_TYPE,
1538  DATA_IO_PRIM_TYPE => DATA_IO_PRIM_TYPE,
1539  IODELAY_GRP => IODELAY_GRP,
1540  DATA_IO_IDLE_PWRDWN => DATA_IO_IDLE_PWRDWN,
1541  nCK_PER_CLK => nCK_PER_CLK,
1542  nCS_PER_RANK => nCS_PER_RANK,
1543  BANK_WIDTH => BANK_WIDTH,
1544  CKE_WIDTH => CKE_WIDTH,
1545  CS_WIDTH => CS_WIDTH,
1546  CK_WIDTH => CK_WIDTH,
1547  CWL => CWL,
1548  DDR2_DQSN_ENABLE => DDR2_DQSN_ENABLE,
1549  DM_WIDTH => DM_WIDTH,
1550  DQ_WIDTH => DQ_WIDTH,
1551  DQS_CNT_WIDTH => DQS_CNT_WIDTH,
1552  DQS_WIDTH => DQS_WIDTH,
1553  DRAM_TYPE => DRAM_TYPE,
1554  RANKS => RANKS,
1555  ODT_WIDTH => ODT_WIDTH,
1556  REG_CTRL => REG_CTRL,
1557  ROW_WIDTH => ROW_WIDTH,
1558  USE_CS_PORT => USE_CS_PORT,
1559  USE_DM_PORT => USE_DM_PORT,
1560  USE_ODT_PORT => USE_ODT_PORT,
1561  IBUF_LPWR_MODE => IBUF_LPWR_MODE ,
1562  LP_DDR_CK_WIDTH => LP_DDR_CK_WIDTH,
1563  PHYCTL_CMD_FIFO => PHYCTL_CMD_FIFO,
1564  DATA_CTL_B0 => DATA_CTL_B0,
1565  DATA_CTL_B1 => DATA_CTL_B1,
1566  DATA_CTL_B2 => DATA_CTL_B2,
1567  DATA_CTL_B3 => DATA_CTL_B3,
1568  DATA_CTL_B4 => DATA_CTL_B4,
1569  BYTE_LANES_B0 => BYTE_LANES_B0,
1570  BYTE_LANES_B1 => BYTE_LANES_B1,
1571  BYTE_LANES_B2 => BYTE_LANES_B2,
1572  BYTE_LANES_B3 => BYTE_LANES_B3,
1573  BYTE_LANES_B4 => BYTE_LANES_B4,
1574  PHY_0_BITLANES => PHY_0_BITLANES ,
1575  PHY_1_BITLANES => PHY_1_BITLANES ,
1576  PHY_2_BITLANES => PHY_2_BITLANES ,
1577  HIGHEST_BANK => HIGHEST_BANK,
1578  HIGHEST_LANE => HIGHEST_LANE,
1579  CK_BYTE_MAP => CK_BYTE_MAP,
1580  ADDR_MAP => ADDR_MAP,
1581  BANK_MAP => BANK_MAP,
1582  CAS_MAP => CAS_MAP,
1583  CKE_ODT_BYTE_MAP => CKE_ODT_BYTE_MAP,
1584  CKE_MAP => CKE_MAP,
1585  ODT_MAP => ODT_MAP,
1586  CKE_ODT_AUX => CKE_ODT_AUX,
1587  CS_MAP => CS_MAP,
1588  PARITY_MAP => PARITY_MAP,
1589  RAS_MAP => RAS_MAP,
1590  WE_MAP => WE_MAP,
1591  DQS_BYTE_MAP => DQS_BYTE_MAP,
1592  DATA0_MAP => DATA0_MAP,
1593  DATA1_MAP => DATA1_MAP,
1594  DATA2_MAP => DATA2_MAP,
1595  DATA3_MAP => DATA3_MAP,
1596  DATA4_MAP => DATA4_MAP,
1597  DATA5_MAP => DATA5_MAP,
1598  DATA6_MAP => DATA6_MAP,
1599  DATA7_MAP => DATA7_MAP,
1600  DATA8_MAP => DATA8_MAP,
1601  DATA9_MAP => DATA9_MAP,
1602  DATA10_MAP => DATA10_MAP,
1603  DATA11_MAP => DATA11_MAP,
1604  DATA12_MAP => DATA12_MAP,
1605  DATA13_MAP => DATA13_MAP,
1606  DATA14_MAP => DATA14_MAP,
1607  DATA15_MAP => DATA15_MAP,
1608  DATA16_MAP => DATA16_MAP,
1609  DATA17_MAP => DATA17_MAP,
1610  MASK0_MAP => MASK0_MAP,
1611  MASK1_MAP => MASK1_MAP,
1612  SIM_CAL_OPTION => SIM_CAL_OPTION ,
1613  MASTER_PHY_CTL => MASTER_PHY_CTL
1614  )
1615  port map (
1616  rst => rst,
1617  clk => clk,
1618  -- For memory frequencies between 400~1066 MHz freq_refclk = mem_refclk
1619  -- For memory frequencies below 400 MHz mem_refclk = mem_refclk and
1620  -- freq_refclk = 2x or 4x mem_refclk such that it remains in the
1621  -- 400~1066 MHz range
1622  freq_refclk => freq_refclk,
1623  mem_refclk => mem_refclk,
1624  pll_lock => pll_lock,
1625  sync_pulse => sync_pulse,
1626  idelayctrl_refclk => clk_ref,
1627  phy_cmd_wr_en => mux_cmd_wren,
1628  phy_data_wr_en => mux_wrdata_en,
1629  -- phy_ctl_wd = {ACTPRE[31:30],EventDelay[29:25],seq[24:23],
1630  -- DataOffset[22:17],HiIndex[16:15],LowIndex[14:12],
1631  -- AuxOut[11:8],ControlOffset[7:3],PHYCmd[2:0]}
1632  -- The fields ACTPRE, and BankCount are only used
1633  -- when the hard PHY counters are used by the MC.
1634  phy_ctl_wd => phy_ctl_wd_i,
1635  phy_ctl_wr => mux_ctl_wren,
1636  phy_if_empty_def => phy_if_empty_def,
1637  phy_if_reset => phy_if_reset,
1638  data_offset_1 => mux_data_offset_1,
1639  data_offset_2 => mux_data_offset_2,
1640  aux_in_1 => aux_out_map,
1641  aux_in_2 => aux_out_map,
1642  idelaye2_init_val => idelaye2_init_val,
1643  oclkdelay_init_val => oclkdelay_init_val,
1644  if_empty => if_empty,
1645  phy_ctl_full => phy_ctl_full,
1646  phy_cmd_full => phy_cmd_full,
1647  phy_data_full => phy_data_full,
1648  phy_pre_data_a_full => phy_pre_data_a_full,
1649  ddr_clk => ddr_clk,
1650  phy_mc_go => phy_mc_go,
1651  phy_write_calib => phy_write_calib,
1652  phy_read_calib => phy_read_calib ,
1653  calib_in_common => calib_in_common,
1654  calib_sel => calib_sel,
1655  calib_zero_inputs => calib_zero_inputs,
1656  calib_zero_ctrl => calib_zero_ctrl,
1657  po_fine_enable => po_enstg2_f,
1658  po_coarse_enable => po_enstg2_c,
1659  po_fine_inc => po_stg2_fincdec,
1660  po_coarse_inc => po_stg2_cincdec,
1661  po_counter_load_en => po_counter_load_en,
1662  po_counter_read_en => '1',
1663  po_sel_fine_oclk_delay => po_sel_stg2stg3,
1664  po_counter_load_val => all_zeros,
1665  po_counter_read_val => po_counter_read_val,
1666  pi_counter_read_val => pi_counter_read_val,
1667  pi_rst_dqs_find => rst_stg1_cal,
1668  pi_fine_enable => pi_enstg2_f,
1669  pi_fine_inc => pi_stg2_fincdec,
1670  pi_counter_load_en => pi_stg2_load,
1671  pi_counter_load_val => pi_stg2_reg_l,
1672  idelay_ce => idelay_ce,
1673  idelay_inc => idelay_inc,
1674  idelay_ld => idelay_ld,
1675  idle => idle,
1676  pi_phase_locked => pi_phase_locked,
1677  pi_phase_locked_all => pi_phase_locked_all,
1678  pi_dqs_found => pi_found_dqs,
1679  pi_dqs_found_all => pi_dqs_found_all,
1680  -- Currently not being used. May be used in future if periodic reads
1681  -- become a requirement. This output could also be used to signal a
1682  -- catastrophic failure in read capture and the need for re-cal
1683  pi_dqs_out_of_range => pi_dqs_out_of_range,
1684  phy_init_data_sel => phy_init_data_sel,
1685  mux_address => mux_address,
1686  mux_bank => mux_bank,
1687  mux_cas_n => mux_cas_n,
1688  mux_cs_n => mux_cs_n,
1689  mux_ras_n => mux_ras_n,
1690  mux_odt => mux_odt,
1691  mux_cke => mux_cke,
1692  mux_we_n => mux_we_n,
1693  parity_in => parity,
1694  mux_wrdata => mux_wrdata,
1695  mux_wrdata_mask => mux_wrdata_mask,
1696  mux_reset_n => mux_reset_n,
1697  rd_data => rd_data_map,
1698  ddr_addr => ddr_addr,
1699  ddr_ba => ddr_ba,
1700  ddr_cas_n => ddr_cas_n,
1701  ddr_cke => ddr_cke,
1702  ddr_cs_n => ddr_cs_n,
1703  ddr_dm => ddr_dm,
1704  ddr_odt => ddr_odt,
1705  ddr_parity => ddr_parity,
1706  ddr_ras_n => ddr_ras_n,
1707  ddr_we_n => ddr_we_n,
1708  ddr_reset_n => ddr_reset_n,
1709  ddr_dq => ddr_dq,
1710  ddr_dqs => ddr_dqs,
1711  ddr_dqs_n => ddr_dqs_n,
1712  dbg_pi_counter_read_en => '1',
1713  ref_dll_lock => ref_dll_lock,
1714  rst_phaser_ref => rst_phaser_ref ,
1715  dbg_pi_phase_locked_phy4lanes => dbg_pi_phase_locked_phy4lanes,
1716  dbg_pi_dqs_found_lanes_phy4lanes => dbg_pi_dqs_found_lanes_phy4lanes_i
1717  );
1718 
1719  --***************************************************************************
1720  -- Soft memory initialization and calibration logic
1721  --***************************************************************************
1722 
1723  u_ddr_calib_top : mig_7series_v1_9_ddr_calib_top
1724  generic map (
1725  TCQ => TCQ,
1726  nCK_PER_CLK => nCK_PER_CLK,
1727  tCK => tCK,
1728  CLK_PERIOD => CLK_PERIOD,
1729  N_CTL_LANES => N_CTL_LANES,
1730  DRAM_TYPE => DRAM_TYPE,
1731  PRBS_WIDTH => 8,
1732  HIGHEST_LANE => HIGHEST_LANE,
1733  HIGHEST_BANK => HIGHEST_BANK,
1734  BANK_TYPE => BANK_TYPE,
1735  BYTE_LANES_B0 => BYTE_LANES_B0,
1736  BYTE_LANES_B1 => BYTE_LANES_B1,
1737  BYTE_LANES_B2 => BYTE_LANES_B2,
1738  BYTE_LANES_B3 => BYTE_LANES_B3,
1739  BYTE_LANES_B4 => BYTE_LANES_B4,
1740  DATA_CTL_B0 => DATA_CTL_B0,
1741  DATA_CTL_B1 => DATA_CTL_B1,
1742  DATA_CTL_B2 => DATA_CTL_B2,
1743  DATA_CTL_B3 => DATA_CTL_B3,
1744  DATA_CTL_B4 => DATA_CTL_B4,
1745  DQS_BYTE_MAP => DQS_BYTE_MAP,
1746  CTL_BYTE_LANE => CTL_BYTE_LANE,
1747  CTL_BANK => CTL_BANK,
1748  SLOT_1_CONFIG => SLOT_1_CONFIG,
1749  BANK_WIDTH => BANK_WIDTH,
1750  CA_MIRROR => CA_MIRROR,
1751  COL_WIDTH => COL_WIDTH,
1752  nCS_PER_RANK => nCS_PER_RANK,
1753  DQ_WIDTH => DQ_WIDTH,
1754  DQS_CNT_WIDTH => DQS_CNT_WIDTH,
1755  DQS_WIDTH => DQS_WIDTH,
1756  DRAM_WIDTH => DRAM_WIDTH,
1757  ROW_WIDTH => ROW_WIDTH,
1758  RANKS => RANKS,
1759  CS_WIDTH => CS_WIDTH,
1760  CKE_WIDTH => CKE_WIDTH,
1761  DDR2_DQSN_ENABLE => DDR2_DQSN_ENABLE,
1762  PER_BIT_DESKEW => "OFF",
1763  CALIB_ROW_ADD => CALIB_ROW_ADD,
1764  CALIB_COL_ADD => CALIB_COL_ADD,
1765  CALIB_BA_ADD => CALIB_BA_ADD,
1766  AL => AL,
1767  ADDR_CMD_MODE => ADDR_CMD_MODE,
1768  BURST_MODE => BURST_MODE,
1769  BURST_TYPE => BURST_TYPE,
1770  nCL => CL,
1771  nCWL => CWL,
1772  tRFC => tRFC,
1773  OUTPUT_DRV => OUTPUT_DRV,
1774  REG_CTRL => REG_CTRL,
1775  RTT_NOM => RTT_NOM,
1776  RTT_WR => RTT_WR,
1777  USE_ODT_PORT => USE_ODT_PORT,
1778  WRLVL => WRLVL_W,
1779  PRE_REV3ES => PRE_REV3ES,
1780  SIM_INIT_OPTION => SIM_INIT_OPTION,
1781  SIM_CAL_OPTION => SIM_CAL_OPTION ,
1782  CKE_ODT_AUX => CKE_ODT_AUX,
1783  DEBUG_PORT => DEBUG_PORT
1784  )
1785  port map (
1786  clk => clk,
1787  rst => rst,
1788 
1789  slot_0_present => slot_0_present ,
1790  slot_1_present => slot_1_present ,
1791  -- PHY Control Block and IN_FIFO status
1792  phy_ctl_ready => phy_mc_go,
1793  phy_ctl_full => '0',
1794  phy_cmd_full => '0',
1795  phy_data_full => '0',
1796  -- hard PHY calibration modes
1797  write_calib => phy_write_calib,
1798  read_calib => phy_read_calib ,
1799  -- Signals from calib logic to be MUXED with MC
1800  -- signals before sending to hard PHY
1801  calib_ctl_wren => calib_ctl_wren ,
1802  calib_cmd_wren => calib_cmd_wren ,
1803  calib_seq => calib_seq,
1804  calib_aux_out => calib_aux_out,
1805  calib_odt => calib_odt,
1806  calib_cke => calib_cke,
1807  calib_cmd => calib_cmd,
1808  calib_wrdata_en => calib_wrdata_en,
1809  calib_rank_cnt => calib_rank_cnt ,
1810  calib_cas_slot => calib_cas_slot ,
1811  calib_data_offset_0 => calib_data_offset_0,
1812  calib_data_offset_1 => calib_data_offset_1,
1813  calib_data_offset_2 => calib_data_offset_2,
1814  phy_address => phy_address,
1815  phy_bank => phy_bank,
1816  phy_cs_n => phy_cs_n,
1817  phy_ras_n => phy_ras_n,
1818  phy_cas_n => phy_cas_n,
1819  phy_we_n => phy_we_n,
1820  phy_reset_n => phy_reset_n,
1821  -- DQS count and ck/addr/cmd to be mapped to calib_sel
1822  -- based on parameter that defines placement of ctl lanes
1823  -- and DQS byte groups in each bank. When phy_write_calib
1824  -- is de-asserted calib_sel should select CK/addr/cmd/ctl.
1825  calib_sel => calib_sel,
1826  calib_in_common => calib_in_common,
1827  calib_zero_inputs => calib_zero_inputs,
1828  calib_zero_ctrl => calib_zero_ctrl,
1829  phy_if_empty_def => phy_if_empty_def,
1830  phy_if_reset => phy_if_reset,
1831  -- DQS Phaser_IN calibration/status signals
1832  pi_phaselocked => pi_phase_locked,
1833  pi_phase_locked_all => pi_phase_locked_all,
1834  pi_found_dqs => pi_found_dqs,
1835  pi_dqs_found_all => pi_dqs_found_all,
1836  pi_dqs_found_lanes => dbg_pi_dqs_found_lanes_phy4lanes_i (HIGHEST_LANE-1 downto 0),
1837  pi_rst_stg1_cal => rst_stg1_cal,
1838  pi_en_stg2_f => pi_enstg2_f,
1839  pi_stg2_f_incdec => pi_stg2_fincdec,
1840  pi_stg2_load => pi_stg2_load,
1841  pi_stg2_reg_l => pi_stg2_reg_l,
1842  pi_counter_read_val => pi_counter_read_val,
1843  device_temp => device_temp,
1844  tempmon_sample_en => tempmon_sample_en,
1845  -- IDELAY tap enable and inc signals
1846  idelay_ce => idelay_ce,
1847  idelay_inc => idelay_inc,
1848  idelay_ld => idelay_ld,
1849  -- DQS Phaser_OUT calibration/status signals
1850  po_sel_stg2stg3 => po_sel_stg2stg3,
1851  po_stg2_c_incdec => po_stg2_cincdec,
1852  po_en_stg2_c => po_enstg2_c,
1853  po_stg2_f_incdec => po_stg2_fincdec,
1854  po_en_stg2_f => po_enstg2_f,
1855  po_counter_load_en => po_counter_load_en,
1856  po_counter_read_val => po_counter_read_val,
1857  phy_if_empty => if_empty,
1858  idelaye2_init_val => idelaye2_init_val,
1859  oclkdelay_init_val => oclkdelay_init_val,
1860  tg_err => error,
1861  rst_tg_mc => rst_tg_mc,
1862  phy_wrdata => phy_wrdata,
1863  -- From calib logic To data IN_FIFO
1864  -- DQ IDELAY tap value from Calib logic
1865  -- port to be added to mc_phy by Gary
1866  dlyval_dq => open,
1867  -- From data IN_FIFO To Calib logic and MC/UI
1868  phy_rddata => rd_data_map,
1869  -- From calib logic To MC
1870  phy_rddata_valid => phy_rddata_valid_w,
1871  calib_rd_data_offset_0 => calib_rd_data_offset_i0,
1872  calib_rd_data_offset_1 => calib_rd_data_offset_1,
1873  calib_rd_data_offset_2 => calib_rd_data_offset_2,
1874  calib_writes => open,
1875  -- Mem Init and Calibration status To MC
1876  init_calib_complete => phy_init_data_sel,
1877  init_wrcal_complete => init_wrcal_complete_i,
1878  -- Debug Error signals
1879  pi_phase_locked_err => dbg_pi_phaselock_err,
1880  pi_dqsfound_err => dbg_pi_dqsfound_err,
1881  wrcal_err => dbg_wrcal_err,
1882  -- Debug Signals
1883  dbg_pi_phaselock_start => dbg_pi_phaselock_start,
1884  dbg_pi_dqsfound_start => dbg_pi_dqsfound_start,
1885  dbg_pi_dqsfound_done => dbg_pi_dqsfound_done,
1886  dbg_wrcal_start => dbg_wrcal_start,
1887  dbg_wrcal_done => dbg_wrcal_done ,
1888  dbg_wrlvl_start => dbg_wrlvl_start,
1889  dbg_wrlvl_done => dbg_wrlvl_done ,
1890  dbg_wrlvl_err => dbg_wrlvl_err,
1891  dbg_wrlvl_fine_tap_cnt => dbg_wrlvl_fine_tap_cnt,
1892  dbg_wrlvl_coarse_tap_cnt => dbg_wrlvl_coarse_tap_cnt,
1893  dbg_phy_wrlvl => dbg_phy_wrlvl,
1894  dbg_tap_cnt_during_wrlvl => dbg_tap_cnt_during_wrlvl,
1895  dbg_wl_edge_detect_valid => dbg_wl_edge_detect_valid,
1896  dbg_rd_data_edge_detect => dbg_rd_data_edge_detect,
1897  dbg_final_po_fine_tap_cnt => dbg_final_po_fine_tap_cnt,
1898  dbg_final_po_coarse_tap_cnt => dbg_final_po_coarse_tap_cnt,
1899  dbg_phy_wrcal => dbg_phy_wrcal,
1900  dbg_rdlvl_start => dbg_rdlvl_start,
1901  dbg_rdlvl_done => dbg_rdlvl_done ,
1902  dbg_rdlvl_err => dbg_rdlvl_err,
1903  dbg_cpt_first_edge_cnt => dbg_cpt_first_edge_cnt,
1904  dbg_cpt_second_edge_cnt => dbg_cpt_second_edge_cnt,
1905  dbg_cpt_tap_cnt => dbg_cpt_tap_cnt,
1906  dbg_dq_idelay_tap_cnt => dbg_dq_idelay_tap_cnt,
1907  dbg_sel_pi_incdec => dbg_sel_pi_incdec,
1908  dbg_sel_po_incdec => dbg_sel_po_incdec,
1909  dbg_byte_sel => dbg_byte_sel,
1910  dbg_pi_f_inc => dbg_pi_f_inc,
1911  dbg_pi_f_dec => dbg_pi_f_dec,
1912  dbg_po_f_inc => dbg_po_f_inc,
1913  dbg_po_f_stg23_sel => dbg_po_f_stg23_sel,
1914  dbg_po_f_dec => dbg_po_f_dec,
1915  dbg_idel_up_all => dbg_idel_up_all,
1916  dbg_idel_down_all => dbg_idel_down_all,
1917  dbg_idel_up_cpt => dbg_idel_up_cpt,
1918  dbg_idel_down_cpt => dbg_idel_down_cpt,
1919  dbg_sel_idel_cpt => dbg_sel_idel_cpt,
1920  dbg_sel_all_idel_cpt => dbg_sel_all_idel_cpt,
1921  dbg_phy_rdlvl => dbg_phy_rdlvl,
1922  dbg_calib_top => dbg_calib_top,
1923  dbg_phy_init => dbg_phy_init,
1924  dbg_prbs_rdlvl => dbg_prbs_rdlvl ,
1925  dbg_dqs_found_cal => dbg_dqs_found_cal,
1926  dbg_phy_oclkdelay_cal => dbg_phy_oclkdelay_cal,
1927  dbg_oclkdelay_rd_data => dbg_oclkdelay_rd_data,
1928  dbg_oclkdelay_calib_start => dbg_oclkdelay_calib_start,
1929  dbg_oclkdelay_calib_done => dbg_oclkdelay_calib_done
1930  );
1931 
1932 end architecture arch_ddr_phy_top;
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