AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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ipbus_if.vhd
1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 15:55:15 07/09/2010
6 -- Design Name:
7 -- Module Name: S6LINK_if - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 ----------------------------------------------------------------------------------
19 library IEEE;
20 use IEEE.STD_LOGIC_1164.ALL;
21 use IEEE.STD_LOGIC_ARITH.ALL;
22 use IEEE.STD_LOGIC_UNSIGNED.ALL;
23 use IEEE.std_logic_misc.all;
24 use work.ipbus.ALL;
25 use work.ipbus_trans_decl.ALL;
26 
27 -- Uncomment the following library declaration if using
28 -- arithmetic functions with Signed or Unsigned values
29 --use IEEE.NUMERIC_STD.ALL;
30 
31 -- Uncomment the following library declaration if instantiating
32 -- any Xilinx primitives in this code.
33 library UNISIM;
34 use UNISIM.VComponents.all;
35 Library UNIMACRO;
36 use UNIMACRO.vcomponents.all;
37 
38 entity ipbus_if is
39  generic(RXPOLARITY : std_logic := '0'; TXPOLARITY : std_logic := '0');
40  port(
41  ipb_clk : IN std_logic;
42  UsRclk : IN std_logic;
43  DRPclk : IN std_logic;
44  reset : IN std_logic;
45  got_SN : out std_logic;
46  GTX_RESET : IN std_logic;
47  GbE_REFCLK : in std_logic;
48  wr_amc_en : in std_logic;
49  en_RARP : in std_logic;
50  amc_en : in STD_LOGIC_VECTOR(11 downto 0);
51  IPADDR : in STD_LOGIC_VECTOR(31 downto 0);
52  MACADDR : in STD_LOGIC_VECTOR(47 downto 0);
53  S6LINK_RXN : in std_logic;
54  S6LINK_RXP : in std_logic;
55  S6LINK_TXN : out std_logic;
56  S6LINK_TXP : out std_logic;
57  ipb_out : out ipb_wbus;
58  ipb_in : in ipb_rbus;
59  SN : out STD_LOGIC_VECTOR(8 downto 0);
60  debug_in : IN std_logic_vector(31 downto 0);
61  debug_out : OUT std_logic_vector(127 downto 0)
62  );
63 end ipbus_if;
64 
65 architecture Behavioral of ipbus_if is
66 COMPONENT ipbus_ctrl
67  generic(
68  MAC_CFG: ipb_mac_cfg := EXTERNAL;
69  IP_CFG: ipb_ip_cfg := EXTERNAL;
70 -- Number of address bits to select RX or TX buffer in UDP I/F
71 -- Number of RX and TX buffers is 2**BUFWIDTH
72  BUFWIDTH: natural := 4;
73 -- Numer of address bits to select internal buffer in UDP I/F
74 -- Number of internal buffers is 2**INTERNALWIDTH
75  INTERNALWIDTH: natural := 1;
76 -- Number of address bits within each buffer in UDP I/F
77 -- Size of each buffer is 2**ADDRWIDTH
78  ADDRWIDTH: natural := 11;
79 -- UDP port for IPbus traffic in this instance of UDP I/F
80  IPBUSPORT: std_logic_vector(15 DOWNTO 0) := x"C351";
81 -- Flag whether this UDP I/F instance ignores everything except IPBus traffic
82  SECONDARYPORT: std_logic := '0';
83  N_OOB: natural := 0
84  );
85  port(
86  mac_clk: in std_logic; -- Ethernet MAC clock (125MHz)
87  rst_macclk: in std_logic; -- MAC clock domain sync reset
88  ipb_clk: in std_logic; -- IPbus clock
89  rst_ipb: in std_logic; -- IPbus clock domain sync reset
90  mac_rx_data: in std_logic_vector(7 downto 0); -- AXI4 style MAC signals
91  mac_rx_valid: in std_logic;
92  mac_rx_last: in std_logic;
93  mac_rx_error: in std_logic;
94  mac_tx_data: out std_logic_vector(7 downto 0);
95  mac_tx_valid: out std_logic;
96  mac_tx_last: out std_logic;
97  mac_tx_error: out std_logic;
98  mac_tx_ready: in std_logic;
99  ipb_out: out ipb_wbus; -- IPbus bus signals
100  ipb_in: in ipb_rbus;
101  ipb_req: out std_logic;
102  ipb_grant: in std_logic := '1';
103  mac_addr: in std_logic_vector(47 downto 0) := X"000000000000"; -- Static MAC and IP addresses
104  ip_addr: in std_logic_vector(31 downto 0) := X"00000000";
105  enable: in std_logic := '1';
106  RARP_select: in std_logic := '0';
107  pkt_rx: out std_logic;
108  pkt_tx: out std_logic;
109  pkt_rx_led: out std_logic;
110  pkt_tx_led: out std_logic;
111  oob_in: in ipbus_trans_in_array(N_OOB - 1 downto 0) := (others => ('0', X"00000000", '0'));
112  oob_out: out ipbus_trans_out_array(N_OOB - 1 downto 0)
113  );
114 END COMPONENT;
115 component S6Link_init
116 generic
117 (
118  -- Simulation attributes
119  EXAMPLE_SIM_GTRESET_SPEEDUP : string := "FALSE"; -- Set to 1 to speed up sim reset
120  EXAMPLE_SIMULATION : integer := 0; -- Set to 1 for simulation
121  EXAMPLE_USE_CHIPSCOPE : integer := 0 -- Set to 1 to use Chipscope to drive resets
122 
123 );
124 port
125 (
126  SYSCLK_IN : in std_logic;
127  SOFT_RESET_IN : in std_logic;
128  GT0_TX_FSM_RESET_DONE_OUT : out std_logic;
129  GT0_RX_FSM_RESET_DONE_OUT : out std_logic;
130  GT0_DATA_VALID_IN : in std_logic;
131 
132  --_________________________________________________________________________
133  --GT0 (X1Y15)
134  --____________________________CHANNEL PORTS________________________________
135  --------------------------------- CPLL Ports -------------------------------
136  GT0_CPLLFBCLKLOST_OUT : out std_logic;
137  GT0_CPLLLOCK_OUT : out std_logic;
138  GT0_CPLLLOCKDETCLK_IN : in std_logic;
139  GT0_CPLLRESET_IN : in std_logic;
140  -------------------------- Channel - Clocking Ports ------------------------
141  GT0_GTREFCLK0_IN : in std_logic;
142  ---------------------------- Channel - DRP Ports --------------------------
143  GT0_DRPADDR_IN : in std_logic_vector(8 downto 0);
144  GT0_DRPCLK_IN : in std_logic;
145  GT0_DRPDI_IN : in std_logic_vector(15 downto 0);
146  GT0_DRPDO_OUT : out std_logic_vector(15 downto 0);
147  GT0_DRPEN_IN : in std_logic;
148  GT0_DRPRDY_OUT : out std_logic;
149  GT0_DRPWE_IN : in std_logic;
150  --------------------- RX Initialization and Reset Ports --------------------
151  GT0_RXUSERRDY_IN : in std_logic;
152  -------------------------- RX Margin Analysis Ports ------------------------
153  GT0_EYESCANDATAERROR_OUT : out std_logic;
154  ------------------------- Receive Ports - CDR Ports ------------------------
155  GT0_RXCDRLOCK_OUT : out std_logic;
156  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
157  GT0_RXUSRCLK_IN : in std_logic;
158  GT0_RXUSRCLK2_IN : in std_logic;
159  ------------------ Receive Ports - FPGA RX interface Ports -----------------
160  GT0_RXDATA_OUT : out std_logic_vector(15 downto 0);
161  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
162  GT0_RXDISPERR_OUT : out std_logic_vector(1 downto 0);
163  GT0_RXNOTINTABLE_OUT : out std_logic_vector(1 downto 0);
164  --------------------------- Receive Ports - RX AFE -------------------------
165  GT0_GTXRXP_IN : in std_logic;
166  ------------------------ Receive Ports - RX AFE Ports ----------------------
167  GT0_GTXRXN_IN : in std_logic;
168  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
169  GT0_RXMCOMMAALIGNEN_IN : in std_logic;
170  GT0_RXPCOMMAALIGNEN_IN : in std_logic;
171  --------------------- Receive Ports - RX Equalizer Ports -------------------
172  GT0_RXDFELPMRESET_IN : in std_logic;
173  ------------- Receive Ports - RX Initialization and Reset Ports ------------
174  GT0_GTRXRESET_IN : in std_logic;
175  GT0_RXPMARESET_IN : in std_logic;
176  ----------------- Receive Ports - RX Polarity Control Ports ----------------
177  GT0_RXPOLARITY_IN : in std_logic;
178  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
179  GT0_RXCHARISK_OUT : out std_logic_vector(1 downto 0);
180  -------------- Receive Ports -RX Initialization and Reset Ports ------------
181  GT0_RXRESETDONE_OUT : out std_logic;
182  --------------------- TX Initialization and Reset Ports --------------------
183  GT0_GTTXRESET_IN : in std_logic;
184  GT0_TXUSERRDY_IN : in std_logic;
185  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
186  GT0_TXUSRCLK_IN : in std_logic;
187  GT0_TXUSRCLK2_IN : in std_logic;
188  ------------------ Transmit Ports - TX Data Path interface -----------------
189  GT0_TXDATA_IN : in std_logic_vector(15 downto 0);
190  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
191  GT0_GTXTXN_OUT : out std_logic;
192  GT0_GTXTXP_OUT : out std_logic;
193  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
194  GT0_TXOUTCLK_OUT : out std_logic;
195  GT0_TXOUTCLKFABRIC_OUT : out std_logic;
196  GT0_TXOUTCLKPCS_OUT : out std_logic;
197  --------------------- Transmit Ports - TX Gearbox Ports --------------------
198  GT0_TXCHARISK_IN : in std_logic_vector(1 downto 0);
199  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
200  GT0_TXRESETDONE_OUT : out std_logic;
201  ----------------- Transmit Ports - TX Polarity Control Ports ---------------
202  GT0_TXPOLARITY_IN : in std_logic;
203 
204 
205  --____________________________COMMON PORTS________________________________
206  ---------------------- Common Block - Ref Clock Ports ---------------------
207  GT0_GTREFCLK0_COMMON_IN : in std_logic;
208  ------------------------- Common Block - QPLL Ports ------------------------
209  GT0_QPLLLOCK_OUT : out std_logic;
210  GT0_QPLLLOCKDETCLK_IN : in std_logic;
211  GT0_QPLLRESET_IN : in std_logic
212 
213 
214 );
215 end component;
216 signal CPLLLOCK : std_logic := '0';
217 signal CPLLLOCK_n : std_logic := '0';
218 signal S6LinkRdy_n : std_logic := '1';
219 signal S6LINK_TxOutClk : std_logic := '0';
220 signal S6LINK_RxCharIsComma : std_logic_vector(1 downto 0) := (others => '0');
221 signal S6LINK_RxCharIsK : std_logic_vector(1 downto 0) := (others => '0');
222 signal S6LINK_RxNotInTable : std_logic_vector(1 downto 0) := (others => '0');
223 signal S6LINK_RxDataOut : std_logic_vector(15 downto 0) := (others => '0');
224 signal S6LINK_TxCharIsK : std_logic_vector(1 downto 0) := (others => '0');
225 signal S6LINK_TxDataIn : std_logic_vector(15 downto 0) := (others => '0');
226 signal S6LINK_RxResetDone : std_logic := '0';
227 signal S6LINK_RxResetDoneSyncRegs : std_logic_vector(2 downto 0) := (others => '0');
228 signal S6LINK_TxReset : std_logic := '0';
229 signal S6LINK_DiffCtrl : std_logic_vector(3 downto 0) := x"9"; -- 790mV drive
230 signal startTx : std_logic := '0';
231 signal sending : std_logic := '0';
232 signal enTx : std_logic := '1';
233 signal got_SNp : std_logic := '1';
234 signal SN_T2: std_logic_vector(8 downto 0) := (others => '0');
235 constant M : integer := 10;
236 signal SN_cntr: std_logic_vector(M downto 0) := (others => '0');
237 signal ipbus_txready : std_logic := '0';
238 signal ipbus_rxdlast : std_logic := '0';
239 signal ipbus_rxerr : std_logic := '0';
240 signal ipbus_txdvld : std_logic := '0';
241 signal ipbus_txdvld_q : std_logic := '0';
242 signal receive : std_logic := '0';
243 signal send_amc_en : std_logic := '0';
244 signal wr_amc_en_SyncRegs: std_logic_vector(3 downto 0) := (others => '0');
245 signal cmd: std_logic_vector(7 downto 0) := (others => '0');
246 signal cmd_cntr: std_logic_vector(2 downto 0) := (others => '0');
247 signal ipbus_rxdvld : std_logic := '0';
248 signal div: std_logic_vector(3 downto 0) := (others => '0');
249 signal tx_header: std_logic_vector(1 downto 0) := (others => '0');
250 signal ipbus_txdlast: std_logic_vector(3 downto 0) := (others => '0');
251 signal ipbus_txerr: std_logic_vector(3 downto 0) := (others => '0');
252 signal AXI4_bufA: std_logic_vector(7 downto 0) := (others => '0');
253 signal AXI4_bufB: std_logic_vector(7 downto 0) := (others => '0');
254 signal ipbus_rxd: std_logic_vector(7 downto 0) := (others => '0');
255 signal ipbus_txd: std_logic_vector(7 downto 0) := (others => '0');
256 signal DATA_VALID : std_logic := '0';
257 signal rxfsmresetdone : std_logic := '0';
258 signal txfsmresetdone : std_logic := '0';
259 signal rst_ipbus_ctrl : std_logic := '0';
260 signal oldRxData15 : std_logic := '0';
261 --component icon2
262 -- PORT (
263 -- CONTROL0 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
264 -- CONTROL1 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0));
265 
266 --end component;
267 --component ila64x4096
268 -- PORT (
269 -- CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
270 -- CLK : IN STD_LOGIC;
271 -- DATA : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
272 -- TRIG0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0));
273 --end component;
274 --signal cs0_control : std_logic_vector(35 downto 0) := (others => '0');
275 --signal cs1_control : std_logic_vector(35 downto 0) := (others => '0');
276 --signal cs0_data : std_logic_vector(63 downto 0) := (others => '0');
277 --signal cs1_data : std_logic_vector(63 downto 0) := (others => '0');
278 --signal cs0_trig : std_logic_vector(7 downto 0) := (others => '0');
279 --signal cs1_trig : std_logic_vector(7 downto 0) := (others => '0');
280 begin
281 --icon : icon2
282 -- port map (
283 -- CONTROL0 => cs0_control,
284 -- CONTROL1 => cs1_control);
285 -- cs0 : ila64x4096
286 -- port map (
287 -- CONTROL => cs0_control,
288 -- CLK => ipb_clk,
289 -- DATA => cs0_data,
290 -- TRIG0 => cs0_trig);
291 -- cs1 : ila64x4096
292 -- port map (
293 -- CONTROL => cs1_control,
294 -- CLK => UsRclk,
295 -- DATA => cs1_data,
296 -- TRIG0 => cs1_trig);
297 -- cs0_data(0) <= S6LinkRdy_n;
298 -- cs0_data(1) <= ipb_in.ipb_ack;
299 ---- cs0_data(2) <= ipb_out_i.ipb_write;
300 ---- cs0_data(3) <= ipb_out_i.ipb_strobe;
301 ---- cs0_data(35 downto 4) <= ipb_out_i.ipb_addr;
302 -- cs0_data(63 downto 36) <= (others => '0');
303 ---- cs0_trig(0) <= ipb_out_i.ipb_strobe;
304 -- cs0_trig(7 downto 1) <= (others => '0');
305 -- cs1_data(15 downto 0) <= S6LINK_RxDataOut;
306 -- cs1_data(31 downto 16) <= S6LINK_TxDataIn;
307 -- cs1_data(33 downto 32) <= S6LINK_RxCharIsK;
308 -- cs1_data(35 downto 34) <= S6LINK_TxCharIsK;
309 ---- cs1_data(40 downto 36) <= SN_cntr;
310 -- cs1_data(41) <= rxfsmresetdone;
311 -- cs1_data(42) <= txfsmresetdone;
312 -- cs1_data(43) <= DATA_VALID;
313 -- cs1_data(44) <= receive;
314 ---- cs1_data(45) <= rxgoodframe;
315 ---- cs1_data(46) <= rxbadframe;
316 ---- cs1_data(47) <= ipbus_txack;
317 -- cs1_data(48) <= startTx;
318 -- cs1_data(49) <= ipbus_txdvld;
319 -- cs1_data(50) <= sending;
320 -- cs1_data(51) <= enTx;
321 -- cs1_data(52) <= S6LINK_RxResetDone;
322 -- cs1_data(60 downto 53) <= SN_T2;
323 ---- cs1_data(63 downto 61) <= S6LinkCntr(2 downto 0);
324 -- cs1_trig(1 downto 0) <= S6LINK_RxCharIsK;
325 -- cs1_trig(2) <= receive;
326 -- cs1_trig(7 downto 3) <= (others => '0');
327 debug_out(127 downto 0) <= (others => '0');
328 rst_ipbus_ctrl <= not got_SNp or reset;
329 i_ipbus_ctrl: ipbus_ctrl port map(
330  mac_clk => UsrClk,
331  rst_macclk => rst_ipbus_ctrl,
332  ipb_clk => ipb_clk,
333  rst_ipb => rst_ipbus_ctrl ,
334  mac_rx_data => ipbus_rxd,
335  mac_rx_valid => ipbus_rxdvld,
336  mac_rx_last => ipbus_rxdlast,
337  mac_rx_error => ipbus_rxerr,
338  mac_tx_data => ipbus_txd,
339  mac_tx_valid => ipbus_txdvld,
340  mac_tx_last => ipbus_txdlast(0),
341  mac_tx_error => ipbus_txerr(0),
342  mac_tx_ready => ipbus_txready,
343  ipb_out => ipb_out,
344  ipb_in => ipb_in,
345  ipb_req => open,
346  ipb_grant => '1',
347  mac_addr => MACADDR,
348  ip_addr => IPADDR,
349  enable => '1',
350  RARP_select => en_RARP,
351  pkt_rx => open,
352  pkt_tx => open,
353  pkt_rx_led => open,
354  pkt_tx_led => open,
355  oob_in => (others => ('0', X"00000000", '0')),
356  oob_out => open
357  );
358 process(UsrClk,S6LINK_RxResetDone)
359 begin
360  if(S6LINK_RxResetDone = '0')then
361  S6LINK_RxResetDoneSyncRegs <= (others => '0');
362  elsif(UsrClk'event and UsrClk = '1')then
363  S6LINK_RxResetDoneSyncRegs <= S6LINK_RxResetDoneSyncRegs(1 downto 0) & '1';
364  end if;
365 end process;
366 process(ipb_clk,S6LINK_RxResetDone)
367 begin
368  if(S6LINK_RxResetDone = '0')then
369  S6LinkRdy_n <= '1';
370  elsif(ipb_clk'event and ipb_clk = '1')then
371  if(rxfsmresetdone = '1' and txfsmresetdone = '1')then
372  S6LinkRdy_n <= '0';
373  end if;
374  end if;
375 end process;
376 ipbus_rxerr <= '1' when S6LINK_RxCharIsK(0) = '1' and receive = '1' and S6LINK_RxDataOut(7 downto 0) /= x"f7" else '0';
377 ipbus_rxdlast <= receive and S6LINK_RxCharIsK(0);
378 process(UsrClk)
379 begin
380  if(UsrClk'event and UsrClk = '1')then
381  if(S6LINK_RxResetDoneSyncRegs(2) = '0' or or_reduce(S6LINK_RxNotInTable) = '1')then
382  DATA_VALID <= '0';
383  elsif(S6LINK_RxCharIsK(0) = '1' and S6LINK_RxDataOut(7 downto 0) = x"bc")then
384  DATA_VALID <= '1';
385  end if;
386  ipbus_rxd <= S6LINK_RxDataOut(7 downto 0);
387  ipbus_rxdvld <= receive and not S6LINK_RxCharIsK(0);
388  if(S6LINK_RxResetDoneSyncRegs(2) = '0' or got_SNp = '0')then
389  receive <= '0';
390  elsif(S6LINK_RxCharIsK(0) = '1')then
391  if(S6LINK_RxDataOut(7 downto 0) = x"3c")then
392  receive <= '1';
393  else
394  receive <= '0';
395  end if;
396  end if;
397  if(S6LINK_RxResetDoneSyncRegs(2) = '0' or ipbus_txdvld = '0')then
398  tx_header <= "00";
399  elsif(tx_header /= "11")then
400  tx_header <= tx_header + 1;
401  end if;
402  if(S6LINK_RxResetDoneSyncRegs(2) = '0')then
403  ipbus_txready <= '0';
404  elsif((tx_header(1) = '0' and ipbus_txdvld = '1') or startTx = '1')then
405  ipbus_txready <= '1';
406  elsif((tx_header = "10" and sending = '0') or (ipbus_txdlast(2) = '1' and sending = '1'))then
407  ipbus_txready <= '0';
408  end if;
409  ipbus_txdlast(3 downto 1) <= ipbus_txdlast(2 downto 0);
410  ipbus_txerr(3 downto 1) <= ipbus_txerr(2 downto 0);
411  if(ipbus_txready = '1' or sending = '1')then
412  AXI4_bufA <= ipbus_txd;
413  AXI4_bufB <= AXI4_bufA;
414  end if;
415  startTx <= enTx and tx_header(1) and not sending and not startTx;
416  if(ipbus_txdlast(2) = '1' and sending = '1')then
417  sending <= '0';
418  elsif(startTx = '1')then
419  sending <= '1';
420  end if;
421  if(startTx = '1' or sending = '1')then
422  enTx <= '0';
423  elsif(S6LINK_RxCharIsK(1) = '1' and S6LINK_RxDataOut(15 downto 8) = x"f7")then
424  enTx <= '1';
425  end if;
426  if(SN_cntr(M) = '0')then
427  SN <= "111111111";
428  else
429  SN <= SN_T2;
430  end if;
431  if(S6LinkRdy_n = '1')then
432  got_SNp <= '0';
433  got_SN <= '0';
434  else
435  got_SNp <= SN_cntr(M);
436  got_SN <= got_SNp;
437  end if;
438  if(S6LinkRdy_n = '1')then
439  SN_cntr <= (others => '0');
440  elsif(S6LINK_RxCharIsK = "01" and SN_cntr(M) = '0' and S6LINK_RxDataOut(7 downto 0) = x"bc")then
441  oldRxData15 <= S6LINK_RxDataOut(15);
442  if(S6LINK_RxDataOut(15) = oldRxData15)then
443  SN_T2 <= '1' & S6LINK_RxDataOut(15 downto 8);
444  elsif(S6LINK_RxDataOut(15) = '0')then
445  SN_T2(6 downto 0) <= S6LINK_RxDataOut(14 downto 8);
446  else
447  SN_T2(8 downto 7) <= S6LINK_RxDataOut(9 downto 8);
448  end if;
449  if(SN_T2(7 downto 0) = S6LINK_RxDataOut(15 downto 8))then
450  SN_cntr <= SN_cntr + 1;
451  elsif(S6LINK_RxDataOut(15) = '0' and SN_T2(6 downto 0) = S6LINK_RxDataOut(14 downto 8))then
452  SN_cntr <= SN_cntr + 1;
453  elsif(S6LINK_RxDataOut(15) = '1' and SN_T2(8 downto 7) = S6LINK_RxDataOut(9 downto 8))then
454  SN_cntr <= SN_cntr + 1;
455  else
456  SN_cntr <= (others => '0');
457  end if;
458  end if;
459  if(startTx = '1')then
460  S6LINK_TxCharIsK(0) <= '1';
461  S6LINK_TxDataIn(7 downto 0) <= x"3c"; -- K28.1
462  elsif(sending = '1')then
463  S6LINK_TxCharIsK(0) <= '0';
464  S6LINK_TxDataIn(7 downto 0) <= AXI4_bufB;
465  elsif(ipbus_txdlast(3) = '1')then
466  S6LINK_TxCharIsK(0) <= '1';
467  if(ipbus_txerr(3) = '0')then
468  S6LINK_TxDataIn(7 downto 0) <= x"bc"; -- K28.5
469  else
470  S6LINK_TxDataIn(7 downto 0) <= x"f7"; -- txerr
471  end if;
472  else
473  if(div(3) = '1')then
474  S6LINK_TxCharIsK(0) <= '1';
475  S6LINK_TxDataIn(7 downto 0) <= x"bc"; -- K28.5
476  div <= (others => '0');
477  else
478  S6LINK_TxCharIsK(0) <= '0';
479  S6LINK_TxDataIn(7 downto 0) <= x"00";
480  div <= div + 1;
481  end if;
482  end if;
483  wr_amc_en_SyncRegs <= wr_amc_en_SyncRegs(2 downto 0) & wr_amc_en;
484  if(wr_amc_en_SyncRegs(3 downto 2) = "01")then
485  send_amc_en <= '1';
486  elsif(cmd_cntr = "101")then
487  send_amc_en <= '0';
488  end if;
489  if(send_amc_en = '0')then
490  cmd_cntr <= (others => '0');
491  else
492  cmd_cntr <= cmd_cntr + 1;
493  end if;
494  if(send_amc_en = '1')then
495  cmd <= x"a5";
496  else
497  cmd <= x"00";
498  end if;
499  if(cmd_cntr = "001" or cmd_cntr = "101")then
500  S6LINK_TxCharIsK(1) <= '1';
501  else
502  S6LINK_TxCharIsK(1) <= '0';
503  end if;
504  case cmd_cntr is
505  when "001" => S6LINK_TxDataIn(15 downto 8) <= x"fe"; -- K30.7
506  when "010" => S6LINK_TxDataIn(15 downto 8) <= cmd; -- write AMC_en command
507  when "011" => S6LINK_TxDataIn(15 downto 8) <= amc_en(7 downto 0);
508  when "100" => S6LINK_TxDataIn(15 downto 8) <= x"0" & amc_en(11 downto 8);
509  when "101" => S6LINK_TxDataIn(15 downto 8) <= x"f7"; -- K23.7
510  when others => S6LINK_TxDataIn(15 downto 8) <= x"00";
511  end case;
512  end if;
513 end process;
514 cplllock_n <= not cplllock;
515 i_S6Link_init : S6Link_init
516  generic map
517  (
518  EXAMPLE_SIM_GTRESET_SPEEDUP => "true",
519  EXAMPLE_SIMULATION => 0,
520  EXAMPLE_USE_CHIPSCOPE => 0
521  )
522  port map
523  (
524  SYSCLK_IN => DRPclk,
525  SOFT_RESET_IN => '0',
526  GT0_TX_FSM_RESET_DONE_OUT => txfsmresetdone,
527  GT0_RX_FSM_RESET_DONE_OUT => rxfsmresetdone,
528  GT0_DATA_VALID_IN => DATA_VALID,
529 
530 
531 
532 
533 
534  --_____________________________________________________________________
535  --_____________________________________________________________________
536  --GT0 (X0Y15)
537 
538  --------------------------------- CPLL Ports -------------------------------
539  GT0_CPLLFBCLKLOST_OUT => open,
540  GT0_CPLLLOCK_OUT => cplllock,
541  GT0_CPLLLOCKDETCLK_IN => drpclk,
542  GT0_CPLLRESET_IN => GTX_RESET,
543  ------------------------- Channel - Ref Clock Ports ------------------------
544  GT0_GTREFCLK0_IN => GbE_REFCLK,
545  ---------------- Channel - Dynamic Reconfiguration Port (DRP) --------------
546  GT0_DRPADDR_IN => (others => '0'),
547  GT0_DRPCLK_IN => drpclk,
548  GT0_DRPDI_IN => (others => '0'),
549  GT0_DRPDO_OUT => open,
550  GT0_DRPEN_IN => '0',
551  GT0_DRPRDY_OUT => open,
552  GT0_DRPWE_IN => '0',
553  --------------------- RX Initialization and Reset Ports --------------------
554  GT0_RXUSERRDY_IN => '0',
555  -------------------------- RX Margin Analysis Ports ------------------------
556  GT0_EYESCANDATAERROR_OUT => open,
557  ------------------------- Receive Ports - CDR Ports ------------------------
558  GT0_RXCDRLOCK_OUT => open,
559  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
560  GT0_RXUSRCLK_IN => UsRClk,
561  GT0_RXUSRCLK2_IN => UsRClk,
562  ------------------ Receive Ports - FPGA RX interface Ports -----------------
563  GT0_RXDATA_OUT => S6LINK_RxDataOut,
564  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
565  GT0_RXDISPERR_OUT => open,
566  GT0_RXNOTINTABLE_OUT => S6LINK_RxNotInTable ,
567  --------------------------- Receive Ports - RX AFE -------------------------
568  GT0_GTXRXP_IN => S6LINK_RXP,
569  ------------------------ Receive Ports - RX AFE Ports ----------------------
570  GT0_GTXRXN_IN => S6LINK_RXN,
571  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
572  GT0_RXMCOMMAALIGNEN_IN => S6LINK_RxResetDoneSyncRegs (2),
573  GT0_RXPCOMMAALIGNEN_IN => S6LINK_RxResetDoneSyncRegs(2),
574  ------------ Receive Ports - RX Decision Feedback Equalizer(DFE) -----------
575  GT0_RXDFELPMRESET_IN => '0',
576  ------------- Receive Ports - RX Initialization and Reset Ports ------------
577  GT0_GTRXRESET_IN => cplllock_n,
578  GT0_RXPMARESET_IN => '0',
579  ----------------- Receive Ports - RX Polarity Control Ports ----------------
580  GT0_RXPOLARITY_IN => '0',
581  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
582  GT0_RXCHARISK_OUT => S6LINK_RxCharIsK,
583  -------------- Receive Ports -RX Initialization and Reset Ports ------------
584  GT0_RXRESETDONE_OUT => S6LINK_RxResetDone,
585  --------------------- TX Initialization and Reset Ports --------------------
586  GT0_GTTXRESET_IN => cplllock_n,
587  GT0_TXUSERRDY_IN => '0',
588  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
589  GT0_TXUSRCLK_IN => UsRClk,
590  GT0_TXUSRCLK2_IN => UsRClk,
591  ------------------ Transmit Ports - TX Data Path interface -----------------
592  GT0_TXDATA_IN => S6LINK_TxDataIn,
593  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
594  GT0_GTXTXN_OUT => S6LINK_TXN,
595  GT0_GTXTXP_OUT => S6LINK_TXP,
596  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
597  GT0_TXOUTCLK_OUT => open,
598  GT0_TXOUTCLKFABRIC_OUT => open,
599  GT0_TXOUTCLKPCS_OUT => open,
600  --------------------- Transmit Ports - TX Gearbox Ports --------------------
601  GT0_TXCHARISK_IN => S6LINK_TxCharIsK,
602  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
603  GT0_TXRESETDONE_OUT => open,
604  -------------------- Transmit Ports - TX Polarity Control ------------------
605  GT0_TXPOLARITY_IN => '0',
606 
607 
608 
609 
610  --____________________________COMMON PORTS________________________________
611  ---------------------- Common Block - Ref Clock Ports ---------------------
612  GT0_GTREFCLK0_COMMON_IN => GbE_REFCLK,
613  ------------------------- Common Block - QPLL Ports ------------------------
614  GT0_QPLLLOCK_OUT => open,
615  GT0_QPLLLOCKDETCLK_IN => drpclk,
616  GT0_QPLLRESET_IN => '0'
617 
618  );
619 end Behavioral;
620 
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