v3 Architecture Reference

List of all members.

Processes
write	( clk )
read	( clk125 )

Types
ram_type	array ( 2 ** ( BUFWIDTH + ADDRWIDTH - 2 ) - 1 downto 0 ) of std_logic_vector ( 31 downto 0

Signals
ram	ram_type
ram_out	std_logic_vector ( 31 downto 0 )
bytesel	std_logic_vector ( 1 downto 0 )

Attributes
block_ram	boolean
block_ram	ram : signal is TRUE

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Detailed Description

Definition at line 22 of file udp_dualportram_tx.vhd.

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The documentation for this class was generated from the following file:

• src/common/IPBUS/ipbus_core/hdl/udp_dualportram_tx.vhd