striped Architecture Reference

List of all members.

Processes
write	( clk125 )
read	( clk )

Types
ram_type	array ( 2 ** ( BUFWIDTH + ADDRWIDTH - 2 ) - 1 downto 0 ) of std_logic_vector ( 7 downto 0

Signals
ram1	ram_type
ram2	ram_type
ram3	ram_type
ram4	ram_type

Attributes
block_ram	boolean
block_ram	RAM1 : signal is TRUE
block_ram	RAM2 : signal is TRUE
block_ram	RAM3 : signal is TRUE
block_ram	RAM4 : signal is TRUE

---

Detailed Description

Definition at line 22 of file udp_dualportram_rx.vhd.

---

The documentation for this class was generated from the following file:

• src/common/IPBUS/ipbus_core/hdl/udp_dualportram_rx.vhd