RTL Architecture Reference

List of all members.

Processes
PROCESS_960	( STABLE_CLOCK )
PROCESS_961	( STABLE_CLOCK )
retries_recclk_monitor	( STABLE_CLOCK )
timeouts	( STABLE_CLOCK )
mmcm_lock_wait	( STABLE_CLOCK )
PROCESS_962	( RXUSERCLK )
PROCESS_963	( STABLE_CLOCK )
PROCESS_964	( STABLE_CLOCK )
PROCESS_965	( STABLE_CLOCK )
timeout_buffer_bypass	( RXUSERCLK )
reset_fsm	( STABLE_CLOCK )

Components
uHTR_trigPD_sync_block

Constants
MMCM_LOCK_CNT_MAX	integer := 1024
STARTUP_DELAY	integer := 500
WAIT_CYCLES	integer := STARTUP_DELAY /STABLE_CLOCK_PERIOD
WAIT_MAX	integer := WAIT_CYCLES + 10
WAIT_TIMEOUT_2ms	integer := 2000000 /STABLE_CLOCK_PERIOD
WAIT_TLOCK_MAX	integer := 100000 /STABLE_CLOCK_PERIOD
WAIT_TIMEOUT_500us	integer := 500000 /STABLE_CLOCK_PERIOD
WAIT_TIMEOUT_1us	integer := 1000 /STABLE_CLOCK_PERIOD
WAIT_TIMEOUT_100us	integer := 100000 /STABLE_CLOCK_PERIOD
WAIT_TIME_ADAPT	integer := ( 37000000 /integer ( 1 . 6 ) ) /STABLE_CLOCK_PERIOD
MAX_RETRIES	integer := 2 ** RETRY_COUNTER_BITWIDTH - 1
MAX_WAIT_BYPASS	integer := 5000

Types
rx_rst_fsm_type	( INIT , ASSERT_ALL_RESETS , RELEASE_PLL_RESET , VERIFY_RECCLK_STABLE , RELEASE_MMCM_RESET , WAIT_RESET_DONE , DO_PHASE_ALIGNMENT , MONITOR_DATA_VALID , FSM_DONE )

Signals
rx_state	rx_rst_fsm_type := INIT
init_wait_count	integer range 0 to WAIT_MAX := 0
init_wait_done	std_logic := ' 0 '
pll_reset_asserted	std_logic := ' 0 '
rx_fsm_reset_done_int	std_logic := ' 0 '
rx_fsm_reset_done_int_s2	std_logic := ' 0 '
rx_fsm_reset_done_int_s3	std_logic := ' 0 '
rxresetdone_s2	std_logic := ' 0 '
rxresetdone_s3	std_logic := ' 0 '
retry_counter_int	integer range 0 to MAX_RETRIES := 0
time_out_counter	integer range 0 to WAIT_TIMEOUT_2ms := 0
recclk_mon_restart_count	integer range 0 to 3 := 0
recclk_mon_count_reset	std_logic := ' 0 '
reset_time_out	std_logic := ' 0 '
time_out_2ms	std_logic := ' 0 '
time_tlock_max	std_logic := ' 0 '
time_out_500us	std_logic := ' 0 '
time_out_1us	std_logic := ' 0 '
time_out_100us	std_logic := ' 0 '
check_tlock_max	std_logic := ' 0 '
mmcm_lock_count	integer range 0 to MMCM_LOCK_CNT_MAX - 1 := 0
mmcm_lock_int	std_logic := ' 0 '
mmcm_lock_i	std_logic := ' 0 '
mmcm_lock_reclocked	std_logic := ' 0 '
run_phase_alignment_int	std_logic := ' 0 '
run_phase_alignment_int_s2	std_logic := ' 0 '
run_phase_alignment_int_s3	std_logic := ' 0 '
wait_bypass_count	integer range 0 to MAX_WAIT_BYPASS - 1
time_out_wait_bypass	std_logic := ' 0 '
time_out_wait_bypass_s2	std_logic := ' 0 '
time_out_wait_bypass_s3	std_logic := ' 0 '
refclk_lost	std_logic
time_out_adapt	std_logic := ' 0 '
adapt_count_reset	std_logic := ' 0 '
adapt_count	integer range 0 to WAIT_TIME_ADAPT - 1
data_valid_sync	std_logic := ' 0 '
cplllock_sync	std_logic := ' 0 '
qplllock_sync	std_logic := ' 0 '
cplllock_prev	std_logic := ' 0 '
qplllock_prev	std_logic := ' 0 '
cplllock_ris_edge	std_logic := ' 0 '
qplllock_ris_edge	std_logic := ' 0 '

---

Detailed Description

Definition at line 129 of file uhtr_trigpd_rx_startup_fsm.vhd.

---

The documentation for this class was generated from the following files:

• src/HCAL_trig/uHTR_trig/example_design/uhtr_trigpd_rx_startup_fsm.vhd