rtl Architecture Reference

List of all members.

Processes
PROCESS_832	( clk )
PROCESS_833	( clk )
PROCESS_834	( state ,rx_data ,ipb_in.ipb_err ,timer ,write )

Constants
TIMEOUT	integer := 255
TRANS_RD	std_logic_vector ( 3 downto 0 ) := X " 0 "
TRANS_WR	std_logic_vector ( 3 downto 0 ) := X " 1 "
TRANS_RDN	std_logic_vector ( 3 downto 0 ) := X " 2 "
TRANS_WRN	std_logic_vector ( 3 downto 0 ) := X " 3 "
TRANS_RMWB	std_logic_vector ( 3 downto 0 ) := X " 4 "
TRANS_RMWS	std_logic_vector ( 3 downto 0 ) := X " 5 "
TRANS_RD_CFG	std_logic_vector ( 3 downto 0 ) := X " 6 "
TRANS_WR_CFG	std_logic_vector ( 3 downto 0 ) := X " 7 "

Types
state_type	( ST_IDLE , ST_HDR , ST_ADDR , ST_BUS_CYCLE , ST_RMW_1 , ST_RMW_2 )

Signals
state	state_type
rx_ready_d	std_logic
start	std_logic
rmw_cyc	std_logic
cfg_cyc	std_logic
rmw_write	std_logic
write	std_logic
strobe	std_logic
ack	std_logic
last_wd	std_logic
trans_type	std_logic_vector ( 3 downto 0 )
addr	unsigned ( 31 downto 0 )
words_todo	unsigned ( 7 downto 0 )
words_done	unsigned ( 7 downto 0 )
timer	unsigned ( 7 downto 0 )
rmw_coeff	std_logic_vector ( 31 downto 0 )
rmw_input	std_logic_vector ( 31 downto 0 )
rmw_result	std_logic_vector ( 31 downto 0 )
data_out	std_logic_vector ( 31 downto 0 )
err	std_logic_vector ( 3 downto 0 )
err_d	std_logic_vector ( 3 downto 0 )
hdr	std_logic_vector ( 31 downto 0 )

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Detailed Description

Definition at line 39 of file transactor_sm.vhd.

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The documentation for this class was generated from the following file:

• src/common/IPBUS/ipbus_core/hdl/transactor_sm.vhd