rtl Architecture Reference

List of all members.

Processes
PROCESS_829	( clk )
PROCESS_830	( clk )
PROCESS_831	( clk )

Types
state_type	( ST_IDLE , ST_FIRST , ST_HDR , ST_PREBODY , ST_BODY , ST_DONE , ST_GAP )

Signals
state	state_type
dinit	std_logic
dinit_d	std_logic
dnext	std_logic
dnext_d	std_logic
dsel	std_logic
rxd	std_logic_vector ( 31 downto 0 )
rxf	std_logic_vector ( 31 downto 0 )
raddr	unsigned ( addr_width - 1 downto 0 )
waddr	unsigned ( addr_width - 1 downto 0 )
haddr	unsigned ( addr_width - 1 downto 0 )
waddrh	unsigned ( addr_width - 1 downto 0 )
hlen	unsigned ( 15 downto 0 )
blen	unsigned ( 15 downto 0 )
rctr	unsigned ( 15 downto 0 )
wctr	unsigned ( 15 downto 0 )
idata	std_logic_vector ( 31 downto 0 )
rdata	std_logic_vector ( 31 downto 0 )
first	std_logic
start	std_logic
start_d	std_logic

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Detailed Description

Definition at line 33 of file transactor_if.vhd.

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The documentation for this class was generated from the following file:

• src/common/IPBUS/ipbus_core/hdl/transactor_if.vhd