rtl Architecture Reference

List of all members.

Processes
PROCESS_827	( clk )

Signals
src	unsigned ( 1 downto 0 )
sel	integer := 0
busy	std_logic

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Detailed Description

Definition at line 28 of file trans_arb.vhd.

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The documentation for this class was generated from the following file:

• src/common/IPBUS/ipbus_core/hdl/trans_arb.vhd