behavioral Architecture Reference

List of all members.

Processes
PROCESS_128	( reset_clk ,clock )
PROCESS_129	( reset_clk ,clock )
PROCESS_130	( clock )
PROCESS_131	( clock )
PROCESS_132	( reset_clk ,clock )
PROCESS_133	( reset_clk ,clock )
PROCESS_134	( reset_clk ,clock )
PROCESS_135	( reset_clk ,clock )
PROCESS_136	( reset_clk ,clock )
PROCESS_137	( Greset_clk ,clock )

Components
crc_gen_32b	<Entity crc_gen_32b>
resync	<Entity resync>

Signals
pipe_a	std_logic_vector ( 63 downto 0 )
pipe_b	std_logic_vector ( 63 downto 0 )
pipe_c	std_logic_vector ( 63 downto 0 )
pipe_K	std_logic_vector ( 7 downto 0 )
SOF	std_logic_vector ( 2 downto 0 )
EOF	std_logic_vector ( 0 downto 0 )
stage	std_logic_vector ( 1 downto 0 )
cmd_reg	std_logic_vector ( 31 downto 0 )
data_reg	std_logic_vector ( 31 downto 0 )
ena_cmd_reg	std_logic
status_reg	std_logic_vector ( 63 downto 0 )
ena_ack_reg	std_logic
seqnb_reg	std_logic_vector ( 30 downto 0 )
ID_reg	std_logic_vector ( 15 downto 0 )
length_reg	std_logic_vector ( 15 downto 0 )
cmp_crc	std_logic
eoc	std_logic
crc_val	std_logic_vector ( 31 downto 0 )
crc_valid	std_logic
crc_to_be_check	std_logic_vector ( 31 downto 0 )
end_check	std_logic
cmd_pckt	std_logic
ack_pckt	std_logic
mem_error_gen	std_logic_vector ( 1 downto 0 )
pack_counter	std_logic_vector ( 31 downto 0 )

Instantiations
CRC_generate	crc_gen_32b <Entity crc_gen_32b>
resync_ena_ack	resync <Entity resync>
resync_ena_cmd	resync <Entity resync>

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Detailed Description

Definition at line 49 of file rcv_pckt_s.vhd.

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The documentation for this class was generated from the following files:

• src/CMS_DAQ_if/10Gb/slink/rcv_pckt_s.vhd