AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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mig_7series_v1_9_ddr_phy_top Member List

This is the complete list of members for mig_7series_v1_9_ddr_phy_top, including all inherited members.

TCQ (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
nCK_PER_CLK (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
tCK (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
CLK_PERIOD (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
N_CTL_LANES (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
DRAM_TYPE (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
PRBS_WIDTH (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
HIGHEST_LANE (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
HIGHEST_BANK (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
BANK_TYPE (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
DATA_CTL_B0 (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
DATA_CTL_B1 (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
DATA_CTL_B2 (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
DATA_CTL_B3 (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
DATA_CTL_B4 (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
BYTE_LANES_B0 (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
BYTE_LANES_B1 (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
BYTE_LANES_B2 (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
BYTE_LANES_B3 (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
BYTE_LANES_B4 (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
DQS_BYTE_MAP (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
CTL_BYTE_LANE (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
CTL_BANK (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
SLOT_1_CONFIG (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
BANK_WIDTH (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
CA_MIRROR (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
COL_WIDTH (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
nCS_PER_RANK (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
DQ_WIDTH (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
DQS_CNT_WIDTH (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
DQS_WIDTH (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
DRAM_WIDTH (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
ROW_WIDTH (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
RANKS (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
CS_WIDTH (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
CKE_WIDTH (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
DDR2_DQSN_ENABLE (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
PER_BIT_DESKEW (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
NUM_DQSFOUND_CAL (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
CALIB_ROW_ADD (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
CALIB_COL_ADD (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
CALIB_BA_ADD (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
AL (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
TEST_AL (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
ADDR_CMD_MODE (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
BURST_MODE (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
BURST_TYPE (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
nCL (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
nCWL (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
tRFC (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
OUTPUT_DRV (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
REG_CTRL (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
RTT_NOM (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
RTT_WR (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
USE_ODT_PORT (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
WRLVL (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
PRE_REV3ES (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
SIM_INIT_OPTION (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
SIM_CAL_OPTION (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
CKE_ODT_AUX (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
DEBUG_PORT (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
clk (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
rst (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
slot_0_present (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
slot_1_present (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
phy_ctl_ready (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
phy_ctl_full (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
phy_cmd_full (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
phy_data_full (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
write_calib (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
read_calib (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
calib_ctl_wren (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
calib_cmd_wren (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
calib_seq (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
calib_aux_out (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
calib_cke (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
calib_odt (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
calib_cmd (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
calib_wrdata_en (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
calib_rank_cnt (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
calib_cas_slot (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
calib_data_offset_0 (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
calib_data_offset_1 (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
calib_data_offset_2 (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
phy_address (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
phy_bank (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
phy_cs_n (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
phy_ras_n (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
phy_cas_n (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
phy_we_n (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
phy_reset_n (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
calib_sel (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
calib_in_common (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
calib_zero_inputs (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
calib_zero_ctrl (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
phy_if_empty_def (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
phy_if_reset (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
pi_phaselocked (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
pi_phase_locked_all (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
pi_found_dqs (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
pi_dqs_found_all (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
pi_dqs_found_lanes (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
pi_counter_read_val (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
pi_rst_stg1_cal (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
pi_en_stg2_f (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
pi_stg2_f_incdec (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
pi_stg2_load (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
pi_stg2_reg_l (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
idelay_ce (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
idelay_inc (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
idelay_ld (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
po_sel_stg2stg3 (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
po_stg2_c_incdec (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
po_en_stg2_c (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
po_stg2_f_incdec (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
po_en_stg2_f (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
po_counter_load_en (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
po_counter_read_val (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
phy_if_empty (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
idelaye2_init_val (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
oclkdelay_init_val (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
tg_err (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
rst_tg_mc (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
phy_wrdata (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dlyval_dq (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
phy_rddata (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
calib_rd_data_offset_0 (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
calib_rd_data_offset_1 (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
calib_rd_data_offset_2 (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
phy_rddata_valid (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
calib_writes (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
init_calib_complete (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
init_wrcal_complete (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
pi_phase_locked_err (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
pi_dqsfound_err (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
wrcal_err (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dbg_pi_phaselock_start (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dbg_pi_dqsfound_start (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dbg_pi_dqsfound_done (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dbg_wrcal_start (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dbg_wrcal_done (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dbg_wrlvl_start (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dbg_wrlvl_done (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dbg_wrlvl_err (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dbg_wrlvl_fine_tap_cnt (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dbg_wrlvl_coarse_tap_cnt (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dbg_phy_wrlvl (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dbg_tap_cnt_during_wrlvl (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dbg_wl_edge_detect_valid (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dbg_rd_data_edge_detect (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dbg_final_po_fine_tap_cnt (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dbg_final_po_coarse_tap_cnt (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dbg_phy_wrcal (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dbg_rdlvl_start (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dbg_rdlvl_done (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dbg_rdlvl_err (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dbg_cpt_first_edge_cnt (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dbg_cpt_second_edge_cnt (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dbg_cpt_tap_cnt (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dbg_dq_idelay_tap_cnt (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
device_temp (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
tempmon_sample_en (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dbg_sel_pi_incdec (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dbg_sel_po_incdec (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dbg_byte_sel (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dbg_pi_f_inc (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dbg_pi_f_dec (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dbg_po_f_inc (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dbg_po_f_stg23_sel (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dbg_po_f_dec (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dbg_idel_up_all (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dbg_idel_down_all (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dbg_idel_up_cpt (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dbg_idel_down_cpt (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dbg_sel_idel_cpt (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dbg_sel_all_idel_cpt (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dbg_phy_rdlvl (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dbg_calib_top (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dbg_oclkdelay_calib_start (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dbg_oclkdelay_calib_done (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dbg_phy_oclkdelay_cal (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dbg_oclkdelay_rd_data (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dbg_phy_init (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dbg_prbs_rdlvl (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dbg_dqs_found_cal (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
nSLOTS (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
OCAL_EN (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
DQS_FOUND_N_CTL_LANES (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
DQSFOUND_CAL (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
prbs_seed (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
prbs_out (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
prbs_rise0 (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
prbs_fall0 (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
prbs_rise1 (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
prbs_fall1 (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
prbs_rise2 (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
prbs_fall2 (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
prbs_rise3 (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
prbs_fall3 (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
prbs_o (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dqsfound_retry (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dqsfound_retry_done (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
phy_rddata_en (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
prech_done (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
rdlvl_stg1_done (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
rdlvl_stg1_done_r1 (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
pi_dqs_found_done (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
rdlvl_stg1_err (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
pi_dqs_found_err (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
wrcal_pat_resume (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
wrcal_resume_w (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
rdlvl_prech_req (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
rdlvl_last_byte_done (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
rdlvl_stg1_start (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
rdlvl_stg1_rank_done (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
rdlvl_assrt_common (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
pi_dqs_found_start (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
pi_dqs_found_rank_done (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
wl_sm_start (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
wrcal_start (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
wrcal_rd_wait (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
wrcal_prech_req (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
wrcal_pat_err (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
wrcal_done (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
wrlvl_done (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
wrlvl_err (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
wrlvl_start (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
ck_addr_cmd_delay_done (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
po_ck_addr_cmd_delay_done (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
pi_calib_done (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
detect_pi_found_dqs (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
rd_data_offset_0 (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
rd_data_offset_1 (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
rd_data_offset_2 (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
rd_data_offset_ranks_0 (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
rd_data_offset_ranks_1 (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
rd_data_offset_ranks_2 (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
rd_data_offset_ranks_mc_0 (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
rd_data_offset_ranks_mc_1 (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
rd_data_offset_ranks_mc_2 (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
cmd_po_stg2_f_incdec (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
cmd_po_stg2_incdec_ddr2_c (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
cmd_po_en_stg2_f (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
cmd_po_en_stg2_ddr2_c (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
cmd_po_stg2_c_incdec (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
cmd_po_en_stg2_c (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
po_stg2_ddr2_incdec (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
po_en_stg2_ddr2 (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dqs_po_stg2_f_incdec (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dqs_po_en_stg2_f (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dqs_wl_po_stg2_c_incdec (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
wrcal_po_stg2_c_incdec (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dqs_wl_po_en_stg2_c (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
wrcal_po_en_stg2_c (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
ctl_lane_cnt (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
ctl_lane_sel (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
po_stg2_wrcal_cnt (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
po_stg2_wl_cnt (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
po_stg2_ddr2_cnt (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dqs_wl_po_stg2_reg_l (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dqs_wl_po_stg2_load (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dqs_po_stg2_reg_l (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dqs_po_stg2_load (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dqs_po_dec_done (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
pi_fine_dly_dec_done (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
rdlvl_pi_stg2_f_incdec (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
rdlvl_pi_stg2_f_en (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
pi_stg2_rdlvl_cnt (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
byte_sel_cnt (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
wl_po_coarse_cnt (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
wl_po_fine_cnt (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
phase_locked_err (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
phy_ctl_rdy_dly (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
idelay_ce_int (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
idelay_inc_int (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
idelay_ce_r1 (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
idelay_ce_r2 (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
idelay_inc_r1 (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
po_dly_req_r (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
wrcal_read_req (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
wrcal_act_req (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
temp_wrcal_done (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
tg_timer_done (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
no_rst_tg_mc (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
calib_complete (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
reset_if_r1 (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
reset_if_r2 (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
reset_if_r3 (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
reset_if_r4 (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
reset_if_r5 (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
reset_if_r6 (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
reset_if_r7 (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
reset_if_r8 (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
reset_if_r9 (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
reset_if (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
phy_if_reset_w (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
pi_phaselock_start (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dbg_pi_f_inc_r (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dbg_pi_f_en_r (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dbg_sel_pi_incdec_r (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dbg_po_f_inc_r (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dbg_po_f_stg23_sel_r (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dbg_po_f_en_r (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dbg_sel_po_incdec_r (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
tempmon_pi_f_inc_r (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
tempmon_pi_f_en_r (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
tempmon_sel_pi_incdec_r (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
ck_addr_cmd_delay_done_r1 (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
ck_addr_cmd_delay_done_r2 (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
ck_addr_cmd_delay_done_r3 (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
ck_addr_cmd_delay_done_r4 (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
ck_addr_cmd_delay_done_r5 (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
ck_addr_cmd_delay_done_r6 (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
oclk_init_delay_start (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
oclk_prech_req (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
oclk_calib_resume (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
oclk_init_delay_done (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
oclkdelay_calib_cnt (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
oclkdelay_calib_start (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
oclkdelay_calib_done (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
oclkdelay_calib_done_temp (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
wrlvl_final (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
wrlvl_final_if_rst (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
wrlvl_byte_redo (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
wrlvl_byte_done (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
early1_data (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
early2_data (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
po_stg3_incdec (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
po_en_stg3 (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
po_stg23_sel (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
po_stg23_incdec (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
po_en_stg23 (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
mpr_rdlvl_done (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
mpr_rdlvl_start (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
mpr_last_byte_done (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
mpr_rnk_done (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
mpr_end_if_reset (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
mpr_rdlvl_err (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
rdlvl_err (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
prbs_rdlvl_start (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
prbs_rdlvl_done (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
prbs_rdlvl_done_r1 (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
prbs_last_byte_done (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
prbs_rdlvl_prech_req (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
prbs_pi_stg2_f_incdec (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
prbs_pi_stg2_f_en (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
pi_stg2_prbs_rdlvl_cnt (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
prbs_gen_clk_en (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
rd_data_offset_cal_done (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
fine_adjust_done (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
fine_adjust_lane_cnt (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
ck_po_stg2_f_indec (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
ck_po_stg2_f_en (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
dqs_found_prech_req (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
tempmon_pi_f_inc (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
tempmon_pi_f_dec (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
tempmon_sel_pi_incdec (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
wrcal_sanity_chk (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
wrcal_sanity_chk_done (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
TCQ (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
tCK (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
BANK_TYPE (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
DATA_IO_PRIM_TYPE (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
DATA_IO_IDLE_PWRDWN (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
IODELAY_GRP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
nCK_PER_CLK (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
nCS_PER_RANK (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
BANK_WIDTH (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
CKE_WIDTH (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
CS_WIDTH (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
CK_WIDTH (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
CWL (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
DDR2_DQSN_ENABLE (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
DM_WIDTH (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
DQ_WIDTH (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
DQS_CNT_WIDTH (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
DQS_WIDTH (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
DRAM_TYPE (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
RANKS (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
ODT_WIDTH (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
REG_CTRL (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
ROW_WIDTH (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
USE_CS_PORT (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
USE_DM_PORT (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
USE_ODT_PORT (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
IBUF_LPWR_MODE (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
LP_DDR_CK_WIDTH (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
PHYCTL_CMD_FIFO (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
DATA_CTL_B0 (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
DATA_CTL_B1 (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
DATA_CTL_B2 (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
DATA_CTL_B3 (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
DATA_CTL_B4 (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
BYTE_LANES_B0 (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
BYTE_LANES_B1 (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
BYTE_LANES_B2 (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
BYTE_LANES_B3 (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
BYTE_LANES_B4 (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
PHY_0_BITLANES (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
PHY_1_BITLANES (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
PHY_2_BITLANES (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
HIGHEST_BANK (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
HIGHEST_LANE (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
CK_BYTE_MAP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
ADDR_MAP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
BANK_MAP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
CAS_MAP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
CKE_ODT_BYTE_MAP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
CKE_MAP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
ODT_MAP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
CKE_ODT_AUX (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
CS_MAP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
PARITY_MAP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
RAS_MAP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
WE_MAP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
DQS_BYTE_MAP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
DATA0_MAP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
DATA1_MAP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
DATA2_MAP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
DATA3_MAP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
DATA4_MAP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
DATA5_MAP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
DATA6_MAP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
DATA7_MAP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
DATA8_MAP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
DATA9_MAP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
DATA10_MAP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
DATA11_MAP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
DATA12_MAP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
DATA13_MAP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
DATA14_MAP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
DATA15_MAP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
DATA16_MAP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
DATA17_MAP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
MASK0_MAP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
MASK1_MAP (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
SIM_CAL_OPTION (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
MASTER_PHY_CTL (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
rst (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
clk (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
freq_refclk (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
mem_refclk (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
pll_lock (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
sync_pulse (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
idelayctrl_refclk (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
phy_cmd_wr_en (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
phy_data_wr_en (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
phy_ctl_wd (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
phy_ctl_wr (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
phy_if_empty_def (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
phy_if_reset (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
data_offset_1 (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
data_offset_2 (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
aux_in_1 (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
aux_in_2 (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
idelaye2_init_val (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
oclkdelay_init_val (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
if_empty (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
phy_ctl_full (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
phy_cmd_full (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
phy_data_full (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
phy_pre_data_a_full (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
ddr_clk (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
phy_mc_go (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
phy_write_calib (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
phy_read_calib (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
calib_in_common (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
calib_sel (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
calib_zero_inputs (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
calib_zero_ctrl (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
po_fine_enable (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
po_coarse_enable (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
po_fine_inc (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
po_coarse_inc (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
po_counter_load_en (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
po_counter_read_en (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
po_sel_fine_oclk_delay (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
po_counter_load_val (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
po_counter_read_val (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
pi_counter_read_val (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
pi_rst_dqs_find (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
pi_fine_enable (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
pi_fine_inc (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
pi_counter_load_en (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
pi_counter_load_val (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
idelay_ce (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
idelay_inc (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
idelay_ld (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
idle (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
pi_phase_locked (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
pi_phase_locked_all (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
pi_dqs_found (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
pi_dqs_found_all (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
pi_dqs_out_of_range (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
phy_init_data_sel (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
mux_address (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
mux_bank (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
mux_cas_n (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
mux_cs_n (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
mux_ras_n (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
mux_odt (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
mux_cke (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
mux_we_n (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
parity_in (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
mux_wrdata (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
mux_wrdata_mask (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
mux_reset_n (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
rd_data (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
ddr_addr (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
ddr_ba (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
ddr_cas_n (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
ddr_cke (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
ddr_cs_n (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
ddr_dm (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
ddr_odt (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
ddr_parity (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
ddr_ras_n (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
ddr_we_n (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
ddr_reset_n (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
ddr_dq (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
ddr_dqs (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
ddr_dqs_n (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
dbg_pi_counter_read_en (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
ref_dll_lock (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
rst_phaser_ref (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
dbg_pi_phase_locked_phy4lanes (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
dbg_pi_dqs_found_lanes_phy4lanes (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
ADDR_CMD_MODE (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
ADDR_MAP (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
AL (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
BANK_MAP (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
BANK_TYPE (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
BANK_WIDTH (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
BURST_MODE (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
BURST_TYPE (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
BYTE_LANES_B0 (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
BYTE_LANES_B1 (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
BYTE_LANES_B2 (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
BYTE_LANES_B3 (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
BYTE_LANES_B4 (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
CA_MIRROR (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
calc_phy_bitlanes_outonlydata_mask_in (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
CALIB_BA_ADD (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
CALIB_COL_ADD (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
calib_rd_data_offset_0 (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
calib_rd_data_offset_1 (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
calib_rd_data_offset_2 (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
CALIB_ROW_ADD (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
CAS_MAP (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
CK_BYTE_MAP (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
CK_WIDTH (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
CKE_MAP (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
CKE_ODT_AUX (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
CKE_ODT_BYTE_MAP (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
CKE_WIDTH (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
CL (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
clk (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
clk_ref (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
COL_WIDTH (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
CS_MAP (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
CS_WIDTH (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
CWL (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
DATA0_MAP (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
DATA10_MAP (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
DATA11_MAP (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
DATA12_MAP (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
DATA13_MAP (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
DATA14_MAP (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
DATA15_MAP (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
DATA16_MAP (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
DATA17_MAP (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
DATA1_MAP (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
DATA2_MAP (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
DATA3_MAP (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
DATA4_MAP (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
DATA5_MAP (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
DATA6_MAP (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
DATA7_MAP (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
DATA8_MAP (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
DATA9_MAP (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
DATA_CTL_B0 (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
DATA_CTL_B1 (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
DATA_CTL_B2 (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
DATA_CTL_B3 (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
DATA_CTL_B4 (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
DATA_IO_IDLE_PWRDWN (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
DATA_IO_PRIM_TYPE (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
dbg_byte_sel (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
dbg_calib_top (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
dbg_cpt_first_edge_cnt (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
dbg_cpt_second_edge_cnt (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
dbg_cpt_tap_cnt (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
dbg_dq_idelay_tap_cnt (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
dbg_dqs_found_cal (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
dbg_final_po_coarse_tap_cnt (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
dbg_final_po_fine_tap_cnt (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
dbg_idel_down_all (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
dbg_idel_down_cpt (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
dbg_idel_up_all (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
dbg_idel_up_cpt (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
dbg_oclkdelay_calib_done (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
dbg_oclkdelay_calib_start (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
dbg_oclkdelay_rd_data (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
dbg_phy_init (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
dbg_phy_oclkdelay_cal (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
dbg_phy_rdlvl (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
dbg_phy_wrcal (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
dbg_phy_wrlvl (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
dbg_pi_counter_read_val (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
dbg_pi_dqs_found_lanes_phy4lanes (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
dbg_pi_dqsfound_done (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
dbg_pi_dqsfound_err (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
dbg_pi_dqsfound_start (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
dbg_pi_f_dec (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
dbg_pi_f_inc (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
dbg_pi_phase_locked_phy4lanes (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
dbg_pi_phaselock_err (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
dbg_pi_phaselock_start (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
dbg_pi_phaselocked_done (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
dbg_po_counter_read_val (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
dbg_po_f_dec (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
dbg_po_f_inc (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
dbg_po_f_stg23_sel (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
dbg_prbs_rdlvl (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
dbg_rd_data_edge_detect (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
dbg_rd_data_offset (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
dbg_rddata (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
dbg_rddata_valid (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
dbg_rdlvl_done (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
dbg_rdlvl_err (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
dbg_rdlvl_start (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
dbg_sel_all_idel_cpt (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
dbg_sel_idel_cpt (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
dbg_sel_pi_incdec (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
dbg_sel_po_incdec (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
dbg_tap_cnt_during_wrlvl (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
dbg_wl_edge_detect_valid (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
dbg_wrcal_done (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
dbg_wrcal_err (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
dbg_wrcal_start (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
dbg_wrlvl_coarse_tap_cnt (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
dbg_wrlvl_done (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
dbg_wrlvl_err (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
dbg_wrlvl_fine_tap_cnt (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
dbg_wrlvl_start (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
DDR2_DQSN_ENABLE (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
ddr_addr (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
ddr_ba (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
ddr_cas_n (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
ddr_ck (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
ddr_ck_n (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
ddr_cke (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
ddr_cs_n (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
ddr_dm (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
ddr_dq (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
ddr_dqs (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
ddr_dqs_n (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
ddr_odt (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
ddr_parity (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
ddr_ras_n (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
ddr_reset_n (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
ddr_we_n (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
DEBUG_PORT (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
device_temp (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
DM_WIDTH (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
DQ_WIDTH (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
DQS_BYTE_MAP (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
DQS_CNT_WIDTH (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
DQS_WIDTH (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
DRAM_TYPE (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
DRAM_WIDTH (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
error (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
freq_refclk (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
generate_bytelanes_ddr_ckck_byte_map (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
generate_ddr_ck_map (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
IBUF_LPWR_MODE (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
idle (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
init_calib_complete (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
init_wrcal_complete (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
IOBUF (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
IOBUF (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
IOBUF_DCIEN (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
IOBUF_DCIEN (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
IOBUF_INTERMDISABLE (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
IOBUF_INTERMDISABLE (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
IOBUFDS (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
IOBUFDS_DCIEN (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
IOBUFDS_INTERMDISABLE (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
IODELAY_GRP (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
IODELAY_HP_MODE (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
LP_DDR_CK_WIDTH (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
MASK0_MAP (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
MASK1_MAP (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
MASTER_PHY_CTL (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
mc_address (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
mc_aux_out0 (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
mc_aux_out1 (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
mc_bank (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
mc_cas_n (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
mc_cas_slot (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
mc_cke (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
mc_cmd (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
mc_cmd_wren (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
mc_cs_n (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
mc_ctl_wren (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
mc_data_offset (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
mc_data_offset_1 (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
mc_data_offset_2 (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
mc_odt (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
mc_rank_cnt (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
mc_ras_n (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
mc_reset_n (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
mc_we_n (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
mc_wrdata (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
mc_wrdata_en (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
mc_wrdata_mask (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
mem_refclk (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
mig_7series_v1_9_ddr_mc_phy (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
mig_7series_v1_9_ddr_of_pre_fifo (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
mig_7series_v1_9_ddr_of_pre_fifo (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
mig_7series_v1_9_ddr_of_pre_fifo (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
mig_7series_v1_9_ddr_phy_ck_addr_cmd_delay (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
mig_7series_v1_9_ddr_phy_dqs_found_cal (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
mig_7series_v1_9_ddr_phy_dqs_found_cal_hr (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
mig_7series_v1_9_ddr_phy_init (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
mig_7series_v1_9_ddr_phy_oclkdelay_cal (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
mig_7series_v1_9_ddr_phy_prbs_rdlvl (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
mig_7series_v1_9_ddr_phy_rdlvl (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
mig_7series_v1_9_ddr_phy_tempmon (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
mig_7series_v1_9_ddr_phy_wrcal (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
mig_7series_v1_9_ddr_phy_wrlvl (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
mig_7series_v1_9_ddr_phy_wrlvl_off_delay (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
mig_7series_v1_9_ddr_prbs_gen (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
nCK_PER_CLK (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
nCS_PER_RANK (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
numeric_std (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topuse clause
OBUF (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
OBUF (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
OBUF (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
OBUF (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
OBUF (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
OBUF (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
OBUF (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
OBUF (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
OBUF (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
OBUF (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
OBUF (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
OBUF (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
OBUF (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
OBUFT (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
ODT_MAP (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
ODT_WIDTH (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
OUTPUT_DRV (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
PARITY_MAP (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
PHY_0_BITLANES (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
PHY_1_BITLANES (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
PHY_2_BITLANES (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
phy_mc_cmd_full (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
phy_mc_ctl_full (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
phy_mc_data_full (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
phy_rd_data (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
phy_rddata_valid (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
PHYCTL_CMD_FIFO (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
pi_dqs_out_of_range (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
pll_lock (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
PRE_REV3ES (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
PROCESS_492clk (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
PROCESS_493clk (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
PROCESS_494clk (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
PROCESS_495clk (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
PROCESS_496clk (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
PROCESS_497clk (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
PROCESS_498clk (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
PROCESS_499clk (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
PROCESS_500clk (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
PROCESS_501clk (defined in mig_7series_v1_9_ddr_calib_top)mig_7series_v1_9_ddr_calib_topClass
PROCESS_511clk (defined in mig_7series_v1_9_ddr_mc_phy_wrapper)mig_7series_v1_9_ddr_mc_phy_wrapperClass
RANKS (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
RAS_MAP (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
RD_PATH_REG (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
ref_dll_lock (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
REFCLK_FREQ (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
REG_CTRL (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
ROW_WIDTH (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
rst (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
rst_phaser_ref (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
rst_tg_mc (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
RTT_NOM (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
RTT_WR (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
SIM_BYPASS_INIT_CAL (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
slot_0_present (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
SLOT_1_CONFIG (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
slot_1_present (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
sync_pulse (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
tCK (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
TCQ (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
tempmon_sample_en (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topPort
tRFC (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
USE_CS_PORT (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
USE_DM_PORT (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
USE_ODT_PORT (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
WE_MAP (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
WRLVL (defined in mig_7series_v1_9_ddr_phy_top)mig_7series_v1_9_ddr_phy_topGeneric
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