Behavioral Architecture Reference

List of all members.

Processes
PROCESS_53	( wclk ,reset )
PROCESS_54	( rclk ,reset )

Constants
N	integer := 9

Signals
ce_ra	std_logic := ' 0 '
RDEN	std_logic := ' 0 '
REGCE	std_logic := ' 0 '
RAM_dav	std_logic := ' 0 '
RAM_Do_vld	std_logic := ' 0 '
Do_vld	std_logic := ' 0 '
wa_g	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
wa_g_sync	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
wa_g_sync1	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
wa_g_sync2	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
wc_w	std_logic_vector ( N downto 0 ) := ( others = > ' 0 ' )
wc_r	std_logic_vector ( N downto 0 ) := ( others = > ' 0 ' )
wa	std_logic_vector ( N downto 0 ) := ( others = > ' 0 ' )
wap	std_logic_vector ( N downto 0 ) := ( others = > ' 0 ' )
ra_g	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
ra_g_sync	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
ra_g_sync1	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
ra_g_sync2	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
ra	std_logic_vector ( N downto 0 ) := ( others = > ' 0 ' )
rap	std_logic_vector ( N downto 0 ) := ( others = > ' 0 ' )

Attributes
ASYNC_REG	string
ASYNC_REG	wa_g_sync : signal is " TRUE "
ASYNC_REG	wa_g_sync1 : signal is " TRUE "
ASYNC_REG	wa_g_sync2 : signal is " TRUE "
ASYNC_REG	ra_g_sync : signal is " TRUE "
ASYNC_REG	ra_g_sync1 : signal is " TRUE "
ASYNC_REG	ra_g_sync2 : signal is " TRUE "
shreg_extract	string
shreg_extract	wa_g_sync : signal is " TRUE "
shreg_extract	wa_g_sync1 : signal is " TRUE "
shreg_extract	wa_g_sync2 : signal is " TRUE "
shreg_extract	ra_g_sync : signal is " TRUE "
shreg_extract	ra_g_sync1 : signal is " TRUE "
shreg_extract	ra_g_sync2 : signal is " TRUE "

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Detailed Description

Definition at line 53 of file fifo66X512.vhd.

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The documentation for this class was generated from the following file:

• src/AMC_DAQ_LINK/fifo66X512.vhd