Behavioral Architecture Reference

List of all members.

Processes
PROCESS_361	( clk )
PROCESS_362	( clk )
PROCESS_363	( clk )
PROCESS_364	( clk )
PROCESS_365	( clk )
PROCESS_366	( clk )
PROCESS_367	( clk )

Components
EthernetCRCD64	<Entity EthernetCRCD64>
cmsCRC64	<Entity cmsCRC64>
RAM32x6Db	<Entity RAM32x6Db>

Types
array8X12	array ( 0 to 7 ) of std_logic_vector ( 11 downto 0 )

Signals
fifo_we	std_logic := ' 0 '
fifo_re	std_logic := ' 0 '
fifo_empty	std_logic := ' 1 '
fifo_full	std_logic := ' 0 '
FIFO_di	std_logic_vector ( 66 downto 0 ) := ( others = > ' 0 ' )
FIFO_do	std_logic_vector ( 66 downto 0 ) := ( others = > ' 0 ' )
channel	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
evt_data_we_i	std_logic := ' 0 '
en_output	std_logic := ' 0 '
evt_data_vld	std_logic := ' 0 '
evt_buf_do_vld	std_logic := ' 0 '
evt_buf_re	std_logic := ' 0 '
evt_cnt	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
evt_buf_regce	std_logic := ' 0 '
evt_buf_we	std_logic_vector ( 0 downto 0 ) := ( others = > ' 0 ' )
buf_full	std_logic := ' 0 '
AMC_DATA_re_i	std_logic := ' 0 '
AMC_header_avl	std_logic := ' 0 '
AMC_header_re	std_logic := ' 0 '
header_ra_selected	std_logic := ' 0 '
AMC_header_vld	std_logic := ' 0 '
evt_buf_avl	std_logic := ' 0 '
FIFO_Di_vld	std_logic := ' 0 '
evt_buf_wc	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
evt_buf_wa	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
FIFO_data_wa	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
FIFO_data_wa_q	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
header_fifo_wc	std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
header_wa	std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
header_ra	std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
evt_buf_din	std_logic_vector ( 66 downto 0 ) := ( others = > ' 0 ' )
evt_buf_doa	std_logic_vector ( 66 downto 0 ) := ( others = > ' 0 ' )
evt_buf_ra	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
evt_buf_dout	std_logic_vector ( 66 downto 0 ) := ( others = > ' 0 ' )
wc_fifo_wa	std_logic_vector ( 5 downto 0 ) := ( others = > ' 0 ' )
wc_fifo_ra	std_logic_vector ( 5 downto 0 ) := ( others = > ' 0 ' )
wc_fifo_di	std_logic_vector ( 18 downto 0 ) := ( others = > ' 0 ' )
wc_fifo_do	std_logic_vector ( 18 downto 0 ) := ( others = > ' 0 ' )
wc_fifo_we	std_logic := ' 0 '
wc_fifo_full	std_logic := ' 0 '
header_full	std_logic := ' 0 '
HeaderWC_full	std_logic := ' 0 '
wc_fifo_empty	std_logic := ' 0 '
wc_fifo_di_vld	std_logic := ' 0 '
NoAMCenabled	std_logic := ' 1 '
idle	std_logic := ' 1 '
read_AMC	std_logic := ' 0 '
read_AMC_q	std_logic := ' 0 '
last_channel	std_logic := ' 0 '
wc	std_logic_vector ( 12 downto 0 ) := ( others = > ' 0 ' )
HeaderWC	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
HeaderWC_i	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
HeaderWC_o	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
HeaderWC_a	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
HeaderWC_we	std_logic := ' 0 '
HeaderWC_re	std_logic := ' 0 '
crc_init	std_logic := ' 0 '
crc_ce	std_logic := ' 0 '
rd_last_header	std_logic := ' 0 '
rd_last_header_q	std_logic := ' 0 '
crc_data	std_logic_vector ( 63 downto 0 ) := ( others = > ' 0 ' )
BlockCRC_init	std_logic := ' 0 '
BlockCRC_ce	std_logic := ' 0 '
BlockCRC_ce_q	std_logic := ' 0 '
BlockCRC	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
BlockCRC_data	std_logic_vector ( 63 downto 0 ) := ( others = > ' 0 ' )
BlockCRC_data_r	std_logic_vector ( 63 downto 0 ) := ( others = > ' 0 ' )
block_num	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
Lv1bx	std_logic_vector ( 19 downto 0 ) := ( others = > ' 0 ' )
trailer_we	std_logic := ' 0 '
inject_err	std_logic := ' 0 '
first_block	std_logic := ' 0 '
last_block	std_logic := ' 0 '
block_wc_a	std_logic_vector ( 3 downto 0 ) := ( others = > ' 1 ' )
block_wc_o	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
block_trailer	std_logic := ' 0 '
block_trailer_dl	std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
trailer	std_logic_vector ( 63 downto 0 ) := ( others = > ' 0 ' )
trailer_dl	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
rdcount	array8X12 := ( others = > ( others = > ' 0 ' ) )
wrcount	array8X12 := ( others = > ( others = > ' 0 ' ) )
evt_data_rdy_i	std_logic := ' 0 '
AMCCRC_init	std_logic := ' 0 '
init_AMCCRC	std_logic := ' 0 '
AMCCRC_ce	std_logic := ' 0 '
AMC_trailer	std_logic := ' 0 '
AMClastWord	std_logic := ' 0 '
bad_AMCCRC	std_logic := ' 0 '
chk_AMCCRC	std_logic := ' 0 '
bad_AMCCRC_l	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
AMCCRC	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
saved_AMCCRC	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
saved_AMCCRC_di	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
saved_AMCCRC_do	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
saved_AMCCRC_a	std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )

Instantiations
i_BlockCRC	EthernetCRCD64 <Entity EthernetCRCD64>
i_EventCRC	cmsCRC64 <Entity cmsCRC64>
i_AMCCRC	EthernetCRCD64 <Entity EthernetCRCD64>

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Detailed Description

Definition at line 67 of file evt_bldrNew.vhd.

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The documentation for this class was generated from the following files:

• src/common/AMC_if/evt_bldrNew.vhd