xilinx Architecture Reference

List of all members.

Processes
PROCESS_900	( CLK )
PROCESS_901	( b5 ,k28 ,disp_in_i )
PROCESS_902	( b5 ,k28 ,disp_in_i )
PROCESS_903	( b3 ,k28 ,pdes6 ,a7 )
PROCESS_904	( b3 ,pdes6 )
PROCESS_905	( CLK )
PROCESS_906	( CLK )
PROCESS_907	( CLK )
PROCESS_908	( FORCE_DISP ,DISP_IN ,disp_run )
PROCESS_909	( CLK )
PROCESS_910	( CLK )

Constants
POS	STD_LOGIC := ' 1 '
NEG	STD_LOGIC := ' 0 '

Signals
b6	STD_LOGIC_VECTOR ( 5 downto 0 ) := ( others = > ' 0 ' )
b4	STD_LOGIC_VECTOR ( 3 downto 0 ) := ( others = > ' 0 ' )
pdes6	STD_LOGIC := ' 0 '
pdes4	STD_LOGIC := ' 0 '
k28	STD_LOGIC := ' 0 '
l13	STD_LOGIC := ' 0 '
l31	STD_LOGIC := ' 0 '
a7	STD_LOGIC := ' 0 '
disp_in_i	STD_LOGIC := ' 0 '
disp_run	STD_LOGIC := bint_2_sl ( C_FORCE_CODE_DISP )
kerr_i	STD_LOGIC := ' 0 '

Aliases
a	, STD_LOGIC is DIN ( 0 )
b	, STD_LOGIC is DIN ( 1 )
c	, STD_LOGIC is DIN ( 2 )
d	, STD_LOGIC is DIN ( 3 )
e	, STD_LOGIC is DIN ( 4 )
b5	, STD_LOGIC_VECTOR ( 4 downto 0 ) is DIN ( 4 downto 0 )
b3	, STD_LOGIC_VECTOR ( 2 downto 0 ) is DIN ( 7 downto 5 )

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Detailed Description

Definition at line 97 of file encode_8b10b_lut_base.vhd.

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The documentation for this class was generated from the following file:

• src/common/TTS/encode_8b10b_lut_base.vhd