drp_wr_fsm_bevh Architecture Reference

List of all members.

Processes
PROCESS_859	( clk )

Libraries
IEEE

Use Clauses
STD_LOGIC_1164
STD_LOGIC_UNSIGNED
STD_LOGIC_ARITH

Constants
load_addr_kl	std_logic_vector ( 4 downto 0 ) := " 00001 "
rd_drp_kl	std_logic_vector ( 4 downto 0 ) := " 00010 "
wait_drprdy_kl	std_logic_vector ( 4 downto 0 ) := " 00011 "
mod_drp_kl	std_logic_vector ( 4 downto 0 ) := " 00100 "
load_drp_kl	std_logic_vector ( 4 downto 0 ) := " 00101 "
pulse_wr_kl	std_logic_vector ( 4 downto 0 ) := " 00110 "
wait_drp_dy_kl	std_logic_vector ( 4 downto 0 ) := " 00111 "
load_addr_kh	std_logic_vector ( 4 downto 0 ) := " 01000 "
rd_drp_kh	std_logic_vector ( 4 downto 0 ) := " 01001 "
wait_drprdy_kh	std_logic_vector ( 4 downto 0 ) := " 01010 "
mod_drp_kh	std_logic_vector ( 4 downto 0 ) := " 01011 "
load_drp_kh	std_logic_vector ( 4 downto 0 ) := " 01100 "
pulse_wr_kh	std_logic_vector ( 4 downto 0 ) := " 01101 "
wait_drp_dy_kh	std_logic_vector ( 4 downto 0 ) := " 01110 "
endstate	std_logic_vector ( 4 downto 0 ) := " 01111 "
resetstate	std_logic_vector ( 4 downto 0 ) := " 10000 "

Signals
holds_reg	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
store_di0_reg	std_logic_vector ( 15 downto 0 ) := ( others = > ' 0 ' )
Address_reg	std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )
state_reg	std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
rd_drp_reg	std_logic := ' 0 '
kill0_reg	std_logic := ' 0 '
kill1_reg	std_logic := ' 0 '
kill2_reg	std_logic := ' 0 '
kill3_reg	std_logic := ' 0 '
done0	std_logic := ' 0 '
done1	std_logic := ' 0 '
done2	std_logic := ' 0 '
done3	std_logic := ' 0 '

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Detailed Description

Definition at line 92 of file s6link_lpm_loop_fsm.vhd.

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The documentation for this class was generated from the following file:

• src/common/IPBUS/S6Link/s6link_lpm_loop_fsm.vhd