daqlink_7s_sync_block Entity Reference

List of all members.

Entities
structural	architecture

Libraries
unisim

Use Clauses
vcomponents

Generics
INITIALISE	bit_vector ( 1 downto 0 ) := " 00 "

Ports
clk	in std_logic
data_in	in std_logic
data_out	out std_logic

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Detailed Description

Definition at line 81 of file daqlink_7s_sync_block.vhd.

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The documentation for this class was generated from the following file:

• src/AMC_DAQ_LINK/daqlink_7s_sync_block.vhd