clock_div Entity Reference

Inheritance diagram for clock_div:

List of all members.

Entities
rtl	architecture

Libraries
unisim

Use Clauses
VComponents

Ports
clk	in std_logic
d17	out std_logic
d25	out std_logic
d28	out std_logic

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Detailed Description

Definition at line 15 of file clock_div.vhd.

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The documentation for this class was generated from the following file:

• src/common/IPBUS/clock_div.vhd