behavioral Architecture Reference

List of all members.

Processes
PROCESS_55	( Greset_CLK ,clock )
PROCESS_56	( reset_CLK ,clock )
state_clk	( clock ,reset_CLK )
state_step	( packet ,start_pckt ,pckt_type ,wc_val ,crc_valid )
PROCESS_57	( reset_CLK ,clock )
PROCESS_58	( reset_CLK ,clock )
PROCESS_59	( reset_CLK ,clock )
PROCESS_60	( clock )
PROCESS_61	( clock )
PROCESS_62	( reset_CLK ,clock )
PROCESS_63	( Greset_CLK ,clock )
PROCESS_64	( pipe_dtc ,pipe_kc )

Components
crc_gen_32b	<Entity crc_gen_32b>

Types
packet_type	( idle , preamble , start_of_frame , status_s , command , data , CRC_end_frame , wait_crc , gap0 , gap1 , gap2 , gap3 )

Signals
packet	packet_type
packetNext	packet_type
cmp_crc	std_logic
val_crc	std_logic_vector ( 31 downto 0 )
crc_valid	std_logic
end_crc	std_logic
pckt_type	std_logic_vector ( 2 downto 0 )
seqnb_mem	std_logic_vector ( 31 downto 0 )
len_mem	std_logic_vector ( 15 downto 0 )
cmd_mem	std_logic_vector ( 63 downto 0 )
del_crc	std_logic_vector ( 2 downto 0 )
tmp_dt_crc	std_logic_vector ( 63 downto 0 )
pipe_dta	std_logic_vector ( 63 downto 0 )
pipe_dtb	std_logic_vector ( 63 downto 0 )
pipe_dtc	std_logic_vector ( 63 downto 0 )
pipe_ka	std_logic_vector ( 7 downto 0 )
pipe_kb	std_logic_vector ( 7 downto 0 )
pipe_kc	std_logic_vector ( 7 downto 0 )
nxt_dt	std_logic
wc_val	std_logic_vector ( 15 downto 0 )
mem_error	std_logic_vector ( 3 downto 0 )
mem_error_gen	std_logic_vector ( 3 downto 0 )
cnt_pck	std_logic_vector ( 31 downto 0 )

Instantiations
CRC_engine	crc_gen_32b <Entity crc_gen_32b>

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Detailed Description

Definition at line 48 of file build_pckt_s.vhd.

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The documentation for this class was generated from the following files:

• src/CMS_DAQ_if/10Gb/slink/build_pckt_s.vhd