RTL Architecture Reference

List of all members.

Processes
PROCESS_297	( STABLE_CLOCK ,SOFT_RESET )
timeouts	( STABLE_CLOCK )
mmcm_lock_wait	( STABLE_CLOCK )
PROCESS_298	( TXUSERCLK )
PROCESS_299	( STABLE_CLOCK )
PROCESS_300	( STABLE_CLOCK )
PROCESS_301	( STABLE_CLOCK )
timeout_buffer_bypass	( TXUSERCLK )
timeout_max	( STABLE_CLOCK )
reset_fsm	( STABLE_CLOCK )

Components
amc_gtx5Gpd_sync_block	<Entity amc_gtx5Gpd_sync_block>

Constants
MMCM_LOCK_CNT_MAX	integer := 256
STARTUP_DELAY	integer := 500
WAIT_CYCLES	integer := STARTUP_DELAY /STABLE_CLOCK_PERIOD
WAIT_MAX	integer := WAIT_CYCLES + 10
WAIT_TIMEOUT_2ms	integer := 2000000 /STABLE_CLOCK_PERIOD
WAIT_TLOCK_MAX	integer := 100000 /STABLE_CLOCK_PERIOD
WAIT_TIMEOUT_500us	integer := 500000 /STABLE_CLOCK_PERIOD
WAIT_1us_cycles	integer := 1000 /STABLE_CLOCK_PERIOD
WAIT_1us	integer := WAIT_1us_cycles + 10
MAX_RETRIES	integer := 2 ** RETRY_COUNTER_BITWIDTH - 1
MAX_WAIT_BYPASS	integer := 91648
WAIT_TIME_MAX	integer := 100

Types
tx_rst_fsm_type	( INIT , ASSERT_ALL_RESETS , WAIT_FOR_PLL_LOCK , RELEASE_PLL_RESET , WAIT_FOR_TXOUTCLK , RELEASE_MMCM_RESET , WAIT_FOR_TXUSRCLK , WAIT_RESET_DONE , DO_PHASE_ALIGNMENT , RESET_FSM_DONE )

Signals
tx_state	tx_rst_fsm_type := INIT
init_wait_count	integer range 0 to WAIT_MAX := 0
init_wait_done	std_logic := ' 0 '
pll_reset_asserted	std_logic := ' 0 '
tx_fsm_reset_done_int	std_logic := ' 0 '
tx_fsm_reset_done_int_s2	std_logic := ' 0 '
tx_fsm_reset_done_int_s3	std_logic := ' 0 '
txresetdone_s2	std_logic := ' 0 '
txresetdone_s3	std_logic := ' 0 '
retry_counter_int	integer range 0 to MAX_RETRIES
time_out_counter	integer range 0 to WAIT_TIMEOUT_2ms := 0
reset_time_out	std_logic := ' 0 '
time_out_2ms	std_logic := ' 0 '
time_tlock_max	std_logic := ' 0 '
time_out_500us	std_logic := ' 0 '
mmcm_lock_count	integer range 0 to MMCM_LOCK_CNT_MAX - 1 := 0
mmcm_lock_int	std_logic := ' 0 '
mmcm_lock_i	std_logic := ' 0 '
mmcm_lock_reclocked	std_logic := ' 0 '
run_phase_alignment_int	std_logic := ' 0 '
run_phase_alignment_int_s2	std_logic := ' 0 '
run_phase_alignment_int_s3	std_logic := ' 0 '
wait_bypass_count	integer range 0 to MAX_WAIT_BYPASS - 1
time_out_wait_bypass	std_logic := ' 0 '
time_out_wait_bypass_s2	std_logic := ' 0 '
time_out_wait_bypass_s3	std_logic := ' 0 '
txuserrdy_i	std_logic := ' 0 '
refclk_lost	std_logic
gttxreset_i	std_logic := ' 0 '
txpmaresetdone_i	std_logic := ' 0 '
txpmaresetdone_sync	std_logic
cplllock_sync	std_logic := ' 0 '
qplllock_sync	std_logic := ' 0 '
cplllock_prev	std_logic := ' 0 '
qplllock_prev	std_logic := ' 0 '
cplllock_ris_edge	std_logic := ' 0 '
qplllock_ris_edge	std_logic := ' 0 '
wait_time_cnt	integer range 0 to WAIT_TIME_MAX
wait_time_done	std_logic

Instantiations
sync_run_phase_alignment_int	amc_gtx5Gpd_sync_block <Entity amc_gtx5Gpd_sync_block>
sync_tx_fsm_reset_done_int	amc_gtx5Gpd_sync_block <Entity amc_gtx5Gpd_sync_block>
sync_TXRESETDONE	amc_gtx5Gpd_sync_block <Entity amc_gtx5Gpd_sync_block>
sync_time_out_wait_bypass	amc_gtx5Gpd_sync_block <Entity amc_gtx5Gpd_sync_block>
sync_mmcm_lock_reclocked	amc_gtx5Gpd_sync_block <Entity amc_gtx5Gpd_sync_block>
sync_CPLLLOCK	amc_gtx5Gpd_sync_block <Entity amc_gtx5Gpd_sync_block>
sync_QPLLLOCK	amc_gtx5Gpd_sync_block <Entity amc_gtx5Gpd_sync_block>

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Detailed Description

Definition at line 120 of file amc_gtx5gpd_tx_startup_fsm.vhd.

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The documentation for this class was generated from the following files:

• src/common/AMC_if/amc_gtx5Gpd/amc_gtx5gpd_tx_startup_fsm.vhd