Behavioral Architecture Reference

List of all members.

Processes
PROCESS_895	( sysClk ,rst_cntr ,reset )
PROCESS_896	( sysClk )
PROCESS_897	( sysClk ,CntrRstCycle )
PROCESS_898	( ipb_clk )
PROCESS_899	( clk125 )

Signals
TTC_serr_cntr	std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )
TTC_derr_cntr	std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )
TTC_BcntErr_cntr	std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )
L1A_cntr	std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )
L1A_OFW_cntr	std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )
L1A_BUSY_cntr	std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )
L1A_LOS_cntr	std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )
run_cntr	std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )
ready_cntr	std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )
busy_cntr	std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )
sync_cntr	std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )
ovfl_cntr	std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )
daq_ovfl_cntr	std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )
state0x9_cntr	std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )
state0xa_cntr	std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )
state0xb_cntr	std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )
ReSync_cntr	std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )
state0x9_cntrb	std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )
state0xa_cntrb	std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )
state0xb_cntrb	std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )
state_was_9	std_logic := ' 0 '
state_was_a	std_logic := ' 0 '
state_was_b	std_logic := ' 0 '
startSyncRegs	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
div	std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
start	std_logic := ' 0 '
CntrRstCycle	std_logic := ' 0 '
cntr	std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )
ram_di	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
ram_dpo	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
ram_spo	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
we_ram	std_logic := ' 0 '
ram_wa	std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
ram_ra	std_logic_vector ( 6 downto 0 ) := ( others = > ' 0 ' )
ec_div	std_logic := ' 0 '
channel	std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
DB_cmd_l	std_logic := ' 0 '
DB_en	std_logic := ' 0 '
carry	std_logic := ' 0 '
sr	std_logic_vector ( 5 downto 0 ) := ( others = > ' 0 ' )
toggle	std_logic := ' 0 '
toggle_q	std_logic := ' 0 '
ec_rdata	std_logic := ' 0 '
ec_wdata	std_logic := ' 0 '

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Detailed Description

Definition at line 53 of file TTC_cntr.vhd.

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The documentation for this class was generated from the following files:

• src/common/TTC_cntr.vhd