Behavioral Architecture Reference

List of all members.

Processes
PROCESS_283	( UsrClk ,Cntr_Data ,CntrRstCycle )
PROCESS_284	( UsrClk ,CntrRstCycle )
PROCESS_285	( ipb_clk )
PROCESS_286	( clk125 )

Signals
div	std_logic_vector ( 11 downto 0 ) := ( others = > ' 0 ' )
div_l	std_logic_vector ( 10 downto 0 ) := ( others = > ' 0 ' )
div_l2	std_logic_vector ( 10 downto 0 ) := ( others = > ' 0 ' )
CntrRstCycle	std_logic := ' 0 '
counter_wa	std_logic_vector ( 10 downto 0 ) := ( others = > ' 0 ' )
counter_ra	std_logic_vector ( 10 downto 0 ) := ( others = > ' 0 ' )
counter_DIA	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
counter_DOA	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
counter_DOB	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
we_counter	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
buffer_DOB	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
buffer_RSTB	std_logic := ' 0 '
we_buffer	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
startSyncRegs	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
DataType	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
DataType_l	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
DataType_l2	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
DataType_q	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
tmp	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
ec_div	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
start	std_logic := ' 0 '
data	std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' )
DB_cmd_l	std_logic := ' 0 '
carry_m	std_logic := ' 0 '
DB_en	std_logic := ' 0 '
carry_h	std_logic := ' 0 '
sr	std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
toggle	std_logic := ' 0 '
toggle_q	std_logic := ' 0 '
ec_rdata	std_logic := ' 0 '
ec_wdata	std_logic := ' 0 '

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Detailed Description

Definition at line 51 of file AMC_cntr.vhd.

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The documentation for this class was generated from the following files:

• src/common/AMC_if/AMC_cntr.vhd