AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
 All Classes Variables
amc_gtx5gpd_common.vhd
1 ---------------------------------------------------------------------------------------------------
2 -- ____ ____
3 -- / /\/ /
4 -- /___/ \ / Vendor: Xilinx
5 -- \ \ \/ Version : 3.6
6 -- \ \ Application : 7 Series FPGAs Transceivers Wizard
7 -- / / Filename : amc_gtx5gpd_common.vhd
8 -- /___/ /\
9 -- \ \ / \
10 -- \___\/\___\
11 --
12 --
13 -- Module amc_gtx5Gpd_common
14 -- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
15 --
16 --
17 -- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
18 --
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62 
63 
64 library ieee;
65 use ieee.std_logic_1164.all;
66 use ieee.numeric_std.all;
67 library UNISIM;
68 use UNISIM.VCOMPONENTS.ALL;
69 
70 
71 --***************************** Entity Declaration ****************************
72 entity amc_gtx5Gpd_common is
73 generic
74 (
75  -- Simulation attributes
76  WRAPPER_SIM_GTRESET_SPEEDUP : string := "TRUE"; -- Set to "true" to speed up sim reset
77  SIM_QPLLREFCLK_SEL : bit_vector := "001"
78 );
79 port
80 (
81  QPLLREFCLKSEL_IN : in std_logic_vector(2 downto 0);
82  GTREFCLK1_IN : in std_logic;
83  GTREFCLK0_IN : in std_logic;
84  QPLLLOCK_OUT : out std_logic;
85  QPLLLOCKDETCLK_IN : in std_logic;
86  QPLLOUTCLK_OUT : out std_logic;
87  QPLLOUTREFCLK_OUT : out std_logic;
88  QPLLREFCLKLOST_OUT : out std_logic;
89  QPLLRESET_IN : in std_logic
90 );
91 
92 end amc_gtx5Gpd_common;
93 
94 architecture RTL of amc_gtx5Gpd_common is
95 
96  attribute CORE_GENERATION_INFO : string;
97  attribute CORE_GENERATION_INFO of RTL : architecture is "amc_gtx5Gpd_common,gtwizard_v3_6_1,{protocol_file=Start_from_scratch}";
98 
99 
100 
101 --***********************************Parameter Declarations********************
102 
103  constant DLY : time := 1 ns;
104 
105 --*************************Logic to set Attribute QPLL_FB_DIV*****************************
106  impure function conv_qpll_fbdiv_top (qpllfbdiv_top : in integer) return bit_vector is
107  begin
108  if (qpllfbdiv_top = 16) then
109  return "0000100000";
110  elsif (qpllfbdiv_top = 20) then
111  return "0000110000" ;
112  elsif (qpllfbdiv_top = 32) then
113  return "0001100000" ;
114  elsif (qpllfbdiv_top = 40) then
115  return "0010000000" ;
116  elsif (qpllfbdiv_top = 64) then
117  return "0011100000" ;
118  elsif (qpllfbdiv_top = 66) then
119  return "0101000000" ;
120  elsif (qpllfbdiv_top = 80) then
121  return "0100100000" ;
122  elsif (qpllfbdiv_top = 100) then
123  return "0101110000" ;
124  else
125  return "0000000000" ;
126  end if;
127  end function;
128 
129  impure function conv_qpll_fbdiv_ratio (qpllfbdiv_top : in integer) return bit is
130  begin
131  if (qpllfbdiv_top = 16) then
132  return '1';
133  elsif (qpllfbdiv_top = 20) then
134  return '1' ;
135  elsif (qpllfbdiv_top = 32) then
136  return '1' ;
137  elsif (qpllfbdiv_top = 40) then
138  return '1' ;
139  elsif (qpllfbdiv_top = 64) then
140  return '1' ;
141  elsif (qpllfbdiv_top = 66) then
142  return '0' ;
143  elsif (qpllfbdiv_top = 80) then
144  return '1' ;
145  elsif (qpllfbdiv_top = 100) then
146  return '1' ;
147  else
148  return '1' ;
149  end if;
150  end function;
151 
152  constant QPLL_FBDIV_TOP : integer := 40;
153  constant QPLL_FBDIV_IN : bit_vector(9 downto 0) := conv_qpll_fbdiv_top(QPLL_FBDIV_TOP);
154  constant QPLL_FBDIV_RATIO : bit := conv_qpll_fbdiv_ratio(QPLL_FBDIV_TOP);
155 
156  -- ground and tied_to_vcc_i signals
157  signal tied_to_ground_i : std_logic;
158  signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
159  signal tied_to_vcc_i : std_logic;
160  signal tied_to_vcc_vec_i : std_logic_vector(63 downto 0);
161 
162 begin
163  tied_to_ground_i <= '0';
164  tied_to_ground_vec_i(63 downto 0) <= (others => '0');
165  tied_to_vcc_i <= '1';
166  tied_to_vcc_vec_i(63 downto 0) <= (others => '1');
167 
168  --_________________________________________________________________________
169  --_________________________________________________________________________
170  --_________________________GTXE2_COMMON____________________________________
171 
172  gtxe2_common_i : GTXE2_COMMON
173  generic map
174  (
175  -- Simulation attributes
176  SIM_RESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP ,
177  SIM_QPLLREFCLK_SEL => (SIM_QPLLREFCLK_SEL),
178  SIM_VERSION => "4.0",
179 
180 
181  ------------------COMMON BLOCK Attributes---------------
182  BIAS_CFG => (x"0000040000001000"),
183  COMMON_CFG => (x"00000000"),
184  QPLL_CFG => (x"0680181"),
185  QPLL_CLKOUT_CFG => ("0000"),
186  QPLL_COARSE_FREQ_OVRD => ("010000"),
187  QPLL_COARSE_FREQ_OVRD_EN => ('0'),
188  QPLL_CP => ("0000011111"),
189  QPLL_CP_MONITOR_EN => ('0'),
190  QPLL_DMONITOR_SEL => ('0'),
191  QPLL_FBDIV => (QPLL_FBDIV_IN),
192  QPLL_FBDIV_MONITOR_EN => ('0'),
193  QPLL_FBDIV_RATIO => (QPLL_FBDIV_RATIO),
194  QPLL_INIT_CFG => (x"000006"),
195  QPLL_LOCK_CFG => (x"21E8"),
196  QPLL_LPF => ("1111"),
197  QPLL_REFCLK_DIV => (1)
198 
199 
200  )
201  port map
202  (
203  ------------- Common Block - Dynamic Reconfiguration Port (DRP) -----------
204  DRPADDR => tied_to_ground_vec_i (7 downto 0),
205  DRPCLK => tied_to_ground_i,
206  DRPDI => tied_to_ground_vec_i (15 downto 0),
207  DRPDO => open,
208  DRPEN => tied_to_ground_i,
209  DRPRDY => open,
210  DRPWE => tied_to_ground_i,
211  ---------------------- Common Block - Ref Clock Ports ---------------------
212  GTGREFCLK => tied_to_ground_i,
213  GTNORTHREFCLK0 => tied_to_ground_i,
214  GTNORTHREFCLK1 => tied_to_ground_i,
215  GTREFCLK0 => GTREFCLK0_IN,
216  GTREFCLK1 => GTREFCLK1_IN,
217  GTSOUTHREFCLK0 => tied_to_ground_i,
218  GTSOUTHREFCLK1 => tied_to_ground_i,
219  ------------------------- Common Block - QPLL Ports -----------------------
220  QPLLDMONITOR => open,
221  ----------------------- Common Block - Clocking Ports ----------------------
222  QPLLOUTCLK => QPLLOUTCLK_OUT,
223  QPLLOUTREFCLK => QPLLOUTREFCLK_OUT,
224  REFCLKOUTMONITOR => open,
225  ------------------------- Common Block - QPLL Ports ------------------------
226  QPLLFBCLKLOST => open,
227  QPLLLOCK => QPLLLOCK_OUT,
228  QPLLLOCKDETCLK => QPLLLOCKDETCLK_IN,
229  QPLLLOCKEN => tied_to_vcc_i,
230  QPLLOUTRESET => tied_to_ground_i,
231  QPLLPD => tied_to_ground_i,
232  QPLLREFCLKLOST => QPLLREFCLKLOST_OUT,
233  QPLLREFCLKSEL => QPLLREFCLKSEL_IN,
234  QPLLRESET => QPLLRESET_IN,
235  QPLLRSVD1 => "0000000000000000",
236  QPLLRSVD2 => "11111",
237  --------------------------------- QPLL Ports -------------------------------
238  BGBYPASSB => tied_to_vcc_i,
239  BGMONITORENB => tied_to_vcc_i,
240  BGPDB => tied_to_vcc_i,
241  BGRCALOVRD => "11111",
242  PMARSVD => "00000000",
243  RCALENB => tied_to_vcc_i
244 
245  );
246 
247 end RTL;
Generated on Wed Apr 18 2018 10:55:26 for AMC13 by   doxygen 1.8.1