AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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XGMII_serdes_wapper.vhd
1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 14:05:44 12/07/2015
6 -- Design Name:
7 -- Module Name: XGMII_serdes_wapper - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 library IEEE;
21 use IEEE.STD_LOGIC_1164.ALL;
22 use IEEE.STD_LOGIC_ARITH.ALL;
23 use IEEE.STD_LOGIC_UNSIGNED.ALL;
24 use IEEE.std_logic_misc.all;
25 use work.amc13_pack.all;
26 
27 -- Uncomment the following library declaration if using
28 -- arithmetic functions with Signed or Unsigned values
29 --use IEEE.NUMERIC_STD.ALL;
30 
31 -- Uncomment the following library declaration if instantiating
32 -- any Xilinx primitives in this code.
33 library UNISIM;
34 use UNISIM.VComponents.all;
35 
36 entity XGMII_serdes_wapper is
37  generic(N_SFP : integer := 3);
38  Port (
39  DRPclk : in STD_LOGIC;
40  reset : in STD_LOGIC;
41  gtx_reset : in STD_LOGIC;
42  sfp_pd : in array3x2;
43 -- SFP ports
44  SFP0_RXN : in STD_LOGIC;
45  SFP0_RXP : in STD_LOGIC;
46  SFP1_RXN : in STD_LOGIC;
47  SFP1_RXP : in STD_LOGIC;
48  SFP2_RXN : in STD_LOGIC;
49  SFP2_RXP : in STD_LOGIC;
50  SFP0_TXN : out STD_LOGIC;
51  SFP0_TXP : out STD_LOGIC;
52  SFP1_TXN : out STD_LOGIC;
53  SFP1_TXP : out STD_LOGIC;
54  SFP2_TXN : out STD_LOGIC;
55  SFP2_TXP : out STD_LOGIC;
56  SFP_REFCLK_P : in STD_LOGIC;
57  SFP_REFCLK_N : in STD_LOGIC;
58  clk156 : out STD_LOGIC;
59  PCS_lock : out STD_LOGIC_VECTOR(2 downto 0);
60  gtx_rxresetdone : out STD_LOGIC_VECTOR(2 downto 0);
61  xgmii_txd : in array3x64;
62  xgmii_txc : in array3x8;
63  xgmii_rxd : out array3x64;
64  xgmii_rxc : out array3x8);
65 end XGMII_serdes_wapper;
66 
67 architecture Behavioral of XGMII_serdes_wapper is
68 COMPONENT XGbEPCS32
69  PORT(
70  reset : IN std_logic;
71  clk2x : IN std_logic;
72  clk : IN std_logic;
73  TXUSRCLK : IN std_logic;
74  TX_high : IN std_logic;
75  RXUSRCLK : IN std_logic;
76  RXRESETDONE : IN std_logic;
77  inh_TX : IN std_logic;
78  RESET_TXSync : IN std_logic;
79  GTX_TXD : OUT std_logic_vector(31 downto 0);
80  GTX_TXHEADER : OUT std_logic_vector(1 downto 0);
81  GTX_TX_PAUSE : IN std_logic;
82  GTX_RXD : IN std_logic_vector(31 downto 0);
83  GTX_RXDVLD : IN std_logic;
84  GTX_RXHEADER : IN std_logic_vector(1 downto 0);
85  GTX_RXHEADERVLD : IN std_logic;
86  GTX_RXGOOD : OUT std_logic;
87  GTX_RXGEARBOXSLIP_OUT : OUT std_logic;
88  EmacPhyTxC : IN std_logic_vector(3 downto 0);
89  EmacPhyTxD : IN std_logic_vector(31 downto 0);
90  PhyEmacRxC : OUT std_logic_vector(3 downto 0);
91  PhyEmacRxD : OUT std_logic_vector(31 downto 0)
92  );
93 END COMPONENT;
94 component SFP3_v2_7_init
95 generic
96 (
97  N_SFP : integer := 3;
98  EXAMPLE_SIM_GTRESET_SPEEDUP : string := "TRUE"; -- simulation setting for GT SecureIP model
99  EXAMPLE_SIMULATION : integer := 0; -- Set to 1 for simulation
100  STABLE_CLOCK_PERIOD : integer := 20; --Period of the stable clock driving this state-machine, unit is [ns]
101  EXAMPLE_USE_CHIPSCOPE : integer := 0 -- Set to 1 to use Chipscope to drive resets
102 
103 );
104 port
105 (
106  SYSCLK_IN : in std_logic;
107  SOFT_RESET_IN : in std_logic;
108  DONT_RESET_ON_DATA_ERROR_IN : in std_logic;
109  GT0_TX_FSM_RESET_DONE_OUT : out std_logic;
110  GT0_RX_FSM_RESET_DONE_OUT : out std_logic;
111  GT0_DATA_VALID_IN : in std_logic;
112  GT1_TX_FSM_RESET_DONE_OUT : out std_logic;
113  GT1_RX_FSM_RESET_DONE_OUT : out std_logic;
114  GT1_DATA_VALID_IN : in std_logic;
115  GT2_TX_FSM_RESET_DONE_OUT : out std_logic;
116  GT2_RX_FSM_RESET_DONE_OUT : out std_logic;
117  GT2_DATA_VALID_IN : in std_logic;
118 
119  --_________________________________________________________________________
120  --GT0 (X1Y12)
121  --____________________________CHANNEL PORTS________________________________
122  ---------------------------- Channel - DRP Ports --------------------------
123  GT0_DRPADDR_IN : in std_logic_vector(8 downto 0);
124  GT0_DRPCLK_IN : in std_logic;
125  GT0_DRPDI_IN : in std_logic_vector(15 downto 0);
126  GT0_DRPDO_OUT : out std_logic_vector(15 downto 0);
127  GT0_DRPEN_IN : in std_logic;
128  GT0_DRPRDY_OUT : out std_logic;
129  GT0_DRPWE_IN : in std_logic;
130  ------------------------------- Loopback Ports -----------------------------
131  GT0_LOOPBACK_IN : in std_logic_vector(2 downto 0);
132  ------------------------------ Power-Down Ports ----------------------------
133  GT0_RXPD_IN : in std_logic_vector(1 downto 0);
134  GT0_TXPD_IN : in std_logic_vector(1 downto 0);
135  --------------------- RX Initialization and Reset Ports --------------------
136  GT0_RXUSERRDY_IN : in std_logic;
137  -------------------------- RX Margin Analysis Ports ------------------------
138  GT0_EYESCANDATAERROR_OUT : out std_logic;
139  ------------------------- Receive Ports - CDR Ports ------------------------
140  GT0_RXCDRLOCK_OUT : out std_logic;
141  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
142  GT0_RXUSRCLK_IN : in std_logic;
143  GT0_RXUSRCLK2_IN : in std_logic;
144  ------------------ Receive Ports - FPGA RX interface Ports -----------------
145  GT0_RXDATA_OUT : out std_logic_vector(31 downto 0);
146  ------------------- Receive Ports - Pattern Checker Ports ------------------
147  GT0_RXPRBSERR_OUT : out std_logic;
148  GT0_RXPRBSSEL_IN : in std_logic_vector(2 downto 0);
149  ------------------- Receive Ports - Pattern Checker ports ------------------
150  GT0_RXPRBSCNTRESET_IN : in std_logic;
151  --------------------------- Receive Ports - RX AFE -------------------------
152  GT0_GTXRXP_IN : in std_logic;
153  ------------------------ Receive Ports - RX AFE Ports ----------------------
154  GT0_GTXRXN_IN : in std_logic;
155  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
156  GT0_RXBUFRESET_IN : in std_logic;
157  GT0_RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
158  --------------- Receive Ports - RX Fabric Output Control Ports -------------
159  GT0_RXOUTCLK_OUT : out std_logic;
160  ---------------------- Receive Ports - RX Gearbox Ports --------------------
161  GT0_RXDATAVALID_OUT : out std_logic;
162  GT0_RXHEADER_OUT : out std_logic_vector(1 downto 0);
163  GT0_RXHEADERVALID_OUT : out std_logic;
164  --------------------- Receive Ports - RX Gearbox Ports --------------------
165  GT0_RXGEARBOXSLIP_IN : in std_logic;
166  ------------- Receive Ports - RX Initialization and Reset Ports ------------
167  GT0_GTRXRESET_IN : in std_logic;
168  GT0_RXPMARESET_IN : in std_logic;
169  ------------------ Receive Ports - RX Margin Analysis ports ----------------
170  GT0_RXLPMEN_IN : in std_logic;
171  -------------- Receive Ports -RX Initialization and Reset Ports ------------
172  GT0_RXRESETDONE_OUT : out std_logic;
173  --------------------- TX Initialization and Reset Ports --------------------
174  GT0_GTTXRESET_IN : in std_logic;
175  GT0_TXUSERRDY_IN : in std_logic;
176  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
177  GT0_TXUSRCLK_IN : in std_logic;
178  GT0_TXUSRCLK2_IN : in std_logic;
179  --------------- Transmit Ports - TX Configurable Driver Ports --------------
180  GT0_TXDIFFCTRL_IN : in std_logic_vector(3 downto 0);
181  GT0_TXINHIBIT_IN : in std_logic;
182  GT0_TXMAINCURSOR_IN : in std_logic_vector(6 downto 0);
183  ------------------ Transmit Ports - TX Data Path interface -----------------
184  GT0_TXDATA_IN : in std_logic_vector(31 downto 0);
185  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
186  GT0_GTXTXN_OUT : out std_logic;
187  GT0_GTXTXP_OUT : out std_logic;
188  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
189  GT0_TXOUTCLK_OUT : out std_logic;
190  GT0_TXOUTCLKFABRIC_OUT : out std_logic;
191  GT0_TXOUTCLKPCS_OUT : out std_logic;
192  --------------------- Transmit Ports - TX Gearbox Ports --------------------
193  GT0_TXHEADER_IN : in std_logic_vector(1 downto 0);
194  GT0_TXSEQUENCE_IN : in std_logic_vector(6 downto 0);
195  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
196  GT0_TXRESETDONE_OUT : out std_logic;
197  ------------------ Transmit Ports - pattern Generator Ports ----------------
198  GT0_TXPRBSSEL_IN : in std_logic_vector(2 downto 0);
199 
200  --GT1 (X1Y13)
201  --____________________________CHANNEL PORTS________________________________
202  ---------------------------- Channel - DRP Ports --------------------------
203  GT1_DRPADDR_IN : in std_logic_vector(8 downto 0);
204  GT1_DRPCLK_IN : in std_logic;
205  GT1_DRPDI_IN : in std_logic_vector(15 downto 0);
206  GT1_DRPDO_OUT : out std_logic_vector(15 downto 0);
207  GT1_DRPEN_IN : in std_logic;
208  GT1_DRPRDY_OUT : out std_logic;
209  GT1_DRPWE_IN : in std_logic;
210  ------------------------------- Loopback Ports -----------------------------
211  GT1_LOOPBACK_IN : in std_logic_vector(2 downto 0);
212  ------------------------------ Power-Down Ports ----------------------------
213  GT1_RXPD_IN : in std_logic_vector(1 downto 0);
214  GT1_TXPD_IN : in std_logic_vector(1 downto 0);
215  --------------------- RX Initialization and Reset Ports --------------------
216  GT1_RXUSERRDY_IN : in std_logic;
217  -------------------------- RX Margin Analysis Ports ------------------------
218  GT1_EYESCANDATAERROR_OUT : out std_logic;
219  ------------------------- Receive Ports - CDR Ports ------------------------
220  GT1_RXCDRLOCK_OUT : out std_logic;
221  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
222  GT1_RXUSRCLK_IN : in std_logic;
223  GT1_RXUSRCLK2_IN : in std_logic;
224  ------------------ Receive Ports - FPGA RX interface Ports -----------------
225  GT1_RXDATA_OUT : out std_logic_vector(31 downto 0);
226  ------------------- Receive Ports - Pattern Checker Ports ------------------
227  GT1_RXPRBSERR_OUT : out std_logic;
228  GT1_RXPRBSSEL_IN : in std_logic_vector(2 downto 0);
229  ------------------- Receive Ports - Pattern Checker ports ------------------
230  GT1_RXPRBSCNTRESET_IN : in std_logic;
231  --------------------------- Receive Ports - RX AFE -------------------------
232  GT1_GTXRXP_IN : in std_logic;
233  ------------------------ Receive Ports - RX AFE Ports ----------------------
234  GT1_GTXRXN_IN : in std_logic;
235  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
236  GT1_RXBUFRESET_IN : in std_logic;
237  GT1_RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
238  --------------- Receive Ports - RX Fabric Output Control Ports -------------
239  GT1_RXOUTCLK_OUT : out std_logic;
240  ---------------------- Receive Ports - RX Gearbox Ports --------------------
241  GT1_RXDATAVALID_OUT : out std_logic;
242  GT1_RXHEADER_OUT : out std_logic_vector(1 downto 0);
243  GT1_RXHEADERVALID_OUT : out std_logic;
244  --------------------- Receive Ports - RX Gearbox Ports --------------------
245  GT1_RXGEARBOXSLIP_IN : in std_logic;
246  ------------- Receive Ports - RX Initialization and Reset Ports ------------
247  GT1_GTRXRESET_IN : in std_logic;
248  GT1_RXPMARESET_IN : in std_logic;
249  ------------------ Receive Ports - RX Margin Analysis ports ----------------
250  GT1_RXLPMEN_IN : in std_logic;
251  -------------- Receive Ports -RX Initialization and Reset Ports ------------
252  GT1_RXRESETDONE_OUT : out std_logic;
253  --------------------- TX Initialization and Reset Ports --------------------
254  GT1_GTTXRESET_IN : in std_logic;
255  GT1_TXUSERRDY_IN : in std_logic;
256  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
257  GT1_TXUSRCLK_IN : in std_logic;
258  GT1_TXUSRCLK2_IN : in std_logic;
259  --------------- Transmit Ports - TX Configurable Driver Ports --------------
260  GT1_TXDIFFCTRL_IN : in std_logic_vector(3 downto 0);
261  GT1_TXINHIBIT_IN : in std_logic;
262  GT1_TXMAINCURSOR_IN : in std_logic_vector(6 downto 0);
263  ------------------ Transmit Ports - TX Data Path interface -----------------
264  GT1_TXDATA_IN : in std_logic_vector(31 downto 0);
265  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
266  GT1_GTXTXN_OUT : out std_logic;
267  GT1_GTXTXP_OUT : out std_logic;
268  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
269  GT1_TXOUTCLK_OUT : out std_logic;
270  GT1_TXOUTCLKFABRIC_OUT : out std_logic;
271  GT1_TXOUTCLKPCS_OUT : out std_logic;
272  --------------------- Transmit Ports - TX Gearbox Ports --------------------
273  GT1_TXHEADER_IN : in std_logic_vector(1 downto 0);
274  GT1_TXSEQUENCE_IN : in std_logic_vector(6 downto 0);
275  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
276  GT1_TXRESETDONE_OUT : out std_logic;
277  ------------------ Transmit Ports - pattern Generator Ports ----------------
278  GT1_TXPRBSSEL_IN : in std_logic_vector(2 downto 0);
279 
280  --GT2 (X1Y14)
281  --____________________________CHANNEL PORTS________________________________
282  ---------------------------- Channel - DRP Ports --------------------------
283  GT2_DRPADDR_IN : in std_logic_vector(8 downto 0);
284  GT2_DRPCLK_IN : in std_logic;
285  GT2_DRPDI_IN : in std_logic_vector(15 downto 0);
286  GT2_DRPDO_OUT : out std_logic_vector(15 downto 0);
287  GT2_DRPEN_IN : in std_logic;
288  GT2_DRPRDY_OUT : out std_logic;
289  GT2_DRPWE_IN : in std_logic;
290  ------------------------------- Loopback Ports -----------------------------
291  GT2_LOOPBACK_IN : in std_logic_vector(2 downto 0);
292  ------------------------------ Power-Down Ports ----------------------------
293  GT2_RXPD_IN : in std_logic_vector(1 downto 0);
294  GT2_TXPD_IN : in std_logic_vector(1 downto 0);
295  --------------------- RX Initialization and Reset Ports --------------------
296  GT2_RXUSERRDY_IN : in std_logic;
297  -------------------------- RX Margin Analysis Ports ------------------------
298  GT2_EYESCANDATAERROR_OUT : out std_logic;
299  ------------------------- Receive Ports - CDR Ports ------------------------
300  GT2_RXCDRLOCK_OUT : out std_logic;
301  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
302  GT2_RXUSRCLK_IN : in std_logic;
303  GT2_RXUSRCLK2_IN : in std_logic;
304  ------------------ Receive Ports - FPGA RX interface Ports -----------------
305  GT2_RXDATA_OUT : out std_logic_vector(31 downto 0);
306  ------------------- Receive Ports - Pattern Checker Ports ------------------
307  GT2_RXPRBSERR_OUT : out std_logic;
308  GT2_RXPRBSSEL_IN : in std_logic_vector(2 downto 0);
309  ------------------- Receive Ports - Pattern Checker ports ------------------
310  GT2_RXPRBSCNTRESET_IN : in std_logic;
311  --------------------------- Receive Ports - RX AFE -------------------------
312  GT2_GTXRXP_IN : in std_logic;
313  ------------------------ Receive Ports - RX AFE Ports ----------------------
314  GT2_GTXRXN_IN : in std_logic;
315  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
316  GT2_RXBUFRESET_IN : in std_logic;
317  GT2_RXBUFSTATUS_OUT : out std_logic_vector(2 downto 0);
318  --------------- Receive Ports - RX Fabric Output Control Ports -------------
319  GT2_RXOUTCLK_OUT : out std_logic;
320  ---------------------- Receive Ports - RX Gearbox Ports --------------------
321  GT2_RXDATAVALID_OUT : out std_logic;
322  GT2_RXHEADER_OUT : out std_logic_vector(1 downto 0);
323  GT2_RXHEADERVALID_OUT : out std_logic;
324  --------------------- Receive Ports - RX Gearbox Ports --------------------
325  GT2_RXGEARBOXSLIP_IN : in std_logic;
326  ------------- Receive Ports - RX Initialization and Reset Ports ------------
327  GT2_GTRXRESET_IN : in std_logic;
328  GT2_RXPMARESET_IN : in std_logic;
329  ------------------ Receive Ports - RX Margin Analysis ports ----------------
330  GT2_RXLPMEN_IN : in std_logic;
331  -------------- Receive Ports -RX Initialization and Reset Ports ------------
332  GT2_RXRESETDONE_OUT : out std_logic;
333  --------------------- TX Initialization and Reset Ports --------------------
334  GT2_GTTXRESET_IN : in std_logic;
335  GT2_TXUSERRDY_IN : in std_logic;
336  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
337  GT2_TXUSRCLK_IN : in std_logic;
338  GT2_TXUSRCLK2_IN : in std_logic;
339  --------------- Transmit Ports - TX Configurable Driver Ports --------------
340  GT2_TXDIFFCTRL_IN : in std_logic_vector(3 downto 0);
341  GT2_TXINHIBIT_IN : in std_logic;
342  GT2_TXMAINCURSOR_IN : in std_logic_vector(6 downto 0);
343  ------------------ Transmit Ports - TX Data Path interface -----------------
344  GT2_TXDATA_IN : in std_logic_vector(31 downto 0);
345  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
346  GT2_GTXTXN_OUT : out std_logic;
347  GT2_GTXTXP_OUT : out std_logic;
348  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
349  GT2_TXOUTCLK_OUT : out std_logic;
350  GT2_TXOUTCLKFABRIC_OUT : out std_logic;
351  GT2_TXOUTCLKPCS_OUT : out std_logic;
352  --------------------- Transmit Ports - TX Gearbox Ports --------------------
353  GT2_TXHEADER_IN : in std_logic_vector(1 downto 0);
354  GT2_TXSEQUENCE_IN : in std_logic_vector(6 downto 0);
355  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
356  GT2_TXRESETDONE_OUT : out std_logic;
357  ------------------ Transmit Ports - pattern Generator Ports ----------------
358  GT2_TXPRBSSEL_IN : in std_logic_vector(2 downto 0);
359 
360 
361  --____________________________COMMON PORTS________________________________
362  ---------------------- Common Block - Ref Clock Ports ---------------------
363  GT0_GTREFCLK0_COMMON_IN : in std_logic;
364  ------------------------- Common Block - QPLL Ports ------------------------
365  GT0_QPLLLOCK_OUT : out std_logic;
366  GT0_QPLLLOCKDETCLK_IN : in std_logic;
367  GT0_QPLLRESET_IN : in std_logic
368 
369 
370 );
371 end component;
372 signal gtx_resetSyncRegs : std_logic_vector(2 downto 0) := (others => '0');
373 signal SFP_REFCLK : std_logic := '0';
374 signal REFCLK2XPLLRST : std_logic := '0';
375 signal refclk2x_in : std_logic := '0';
376 signal ClientClk2x_dcm : std_logic := '0';
377 signal ClientClk2x : std_logic := '0';
378 signal ClientClk_dcm : std_logic := '0';
379 signal ClientClk : std_logic := '0';
380 signal ClientClk_lock : std_logic := '0';
381 signal txusrclk : std_logic := '0';
382 signal TX_high : std_logic := '0';
383 signal qplllock : std_logic := '0';
384 signal qpllreset : std_logic := '0';
385 signal TXSEQ_cntr : std_logic_vector(6 downto 0) := (others => '0');
386 signal inh_TX : std_logic_vector(2 downto 0) := (others => '0');
387 signal inh_TX_q : std_logic_vector(2 downto 0) := (others => '0');
388 signal reset_TXSyncRegs : std_logic_vector(2 downto 0) := (others => '0');
389 signal ClientClkToggle : std_logic := '0';
390 signal ClientClkToggle_q : std_logic := '0';
391 signal SFP_TXOUTCLK : std_logic_vector(2 downto 0) := (others => '0');
392 signal SFP_TXSEQUENCE : array3X7 := (others => (others => '0'));
393 signal SFP_rxoutclk : std_logic_vector(2 downto 0) := (others => '0');
394 signal SFP_rxusrclk : std_logic_vector(2 downto 0) := (others => '0');
395 signal SFP_txresetdone : std_logic_vector(2 downto 0) := (others => '0');
396 signal SFP_txuserrdy : std_logic_vector(2 downto 0) := (others => '0');
397 signal SFP_rxresetdone : std_logic_vector(2 downto 0) := (others => '0');
398 signal SFP_rxuserrdy : std_logic_vector(2 downto 0) := (others => '0');
399 signal SFP_drprdy : std_logic_vector(2 downto 0) := (others => '0');
400 signal SFP_drpen : std_logic_vector(2 downto 0) := (others => '0');
401 signal SFP_drpwe : std_logic_vector(2 downto 0) := (others => '0');
402 signal SFP_rxdfeagchold : std_logic_vector(2 downto 0) := (others => '0');
403 signal SFP_adapt_done : std_logic_vector(2 downto 0) := (others => '0');
404 signal SFP_rxmonitor : array3X7 := (others => (others => '0'));
405 signal SFP_drpdo : array3X16 := (others => (others => '0'));
406 signal SFP_rxmonitorsel : array3X2 := (others => (others => '0'));
407 signal SFP_drpaddr : array3X9 := (others => (others => '0'));
408 signal SFP_drpdi : array3X16 := (others => (others => '0'));
409 signal GTX_TX_PAUSE : std_logic := '0';
410 signal SFP_LOOPBACK_IN : array3X3 := (others => (others => '0'));
411 signal SFP_RX_FSM_RESET_DONE : std_logic_vector(2 downto 0) := (others => '0');
412 signal SFP_TX_FSM_RESET_DONE : std_logic_vector(2 downto 0) := (others => '0');
413 signal SFP_RXDVLD : std_logic_vector(2 downto 0) := (others => '0');
414 signal SFP_RXHEADERVLD : std_logic_vector(2 downto 0) := (others => '0');
415 signal SFP_RXGEARBOXSLIP : std_logic_vector(2 downto 0) := (others => '0');
416 signal SFP_RXPRBSERR_OUT : std_logic_vector(2 downto 0) := (others => '0');
417 signal SFP_RXPRBSSEL_IN : array3X3 := (others => (others => '0'));
418 signal SFP_TXPRBSSEL_IN : array3X3 := (others => (others => '0'));
419 signal SFP_EYESCANDATAERROR_OUT : std_logic_vector(2 downto 0) := (others => '0');
420 signal SFP_RXGOOD : std_logic_vector(2 downto 0) := (others => '0');
421 signal SFP_TXD : array3X32 := (others => (others => '0'));
422 signal SFP_TXD_inv : array3X32 := (others => (others => '0'));
423 signal SFP_TXHEADER : array3X2 := (others => (others => '0'));
424 signal SFP_RXD : array3X32 := (others => (others => '0'));
425 signal SFP_RXD_inv : array3X32 := (others => (others => '0'));
426 signal SFP_RXHEADER : array3X2 := (others => (others => '0'));
427 signal SFP_EmacPhyTxD : array3X32 := (others => (others => '0'));
428 signal SFP_EmacPhyTxC : array3X4 := (others => (others => '0'));
429 signal SFP_PhyEmacRxD : array3X32 := (others => (others => '0'));
430 signal SFP_PhyEmacRxC : array3X4 := (others => (others => '0'));
431 signal SFP_PhyEmacRxD_q : array3X32 := (others => (others => '0'));
432 signal SFP_PhyEmacRxC_q : array3X4 := (others => (others => '0'));
433 signal xgmii_rxd_i : array3X64 := (others => (others => '0'));
434 signal xgmii_rxc_i : array3X8 := (others => (others => '0'));
435 signal SFP_pd_q : array3X4 := (others => (others => '0'));
436 signal soft_reset : std_logic := '0';
437 signal reset_cntr20_q : std_logic := '0';
438 signal reset_cntr : std_logic_vector(20 downto 0) := (others => '0');
439 
440 COMPONENT chipscope1
441  PORT(
442  clk : IN std_logic;
443  Din : IN std_logic_vector(303 downto 0)
444  );
445 END COMPONENT;
446 signal cs : std_logic_vector(303 downto 0) := (others => '0');
447 
448 begin
449 --i_chipscope1: chipscope1 PORT MAP(
450 -- clk => ClientClk2X,
451 -- Din => cs
452 -- );
453 -- trigger starts at cs(288)
454 process(ClientClk)
455 begin
456  if(ClientClk'event and ClientClk = '1')then
457  if(xgmii_rxc_i(0)(0) = '1' and xgmii_rxd_i(0)(7 downto 0) = x"fb")then
458  cs(288) <= '1';
459  elsif(xgmii_rxc_i(0)(4) = '1' and xgmii_rxd_i(0)(39 downto 32) = x"fb")then
460  cs(288) <= '1';
461  else
462  cs(288) <= '0';
463  end if;
464  end if;
465 end process;
466 process(ClientClk2X)
467 begin
468  if(ClientClk2X'event and ClientClk2X = '1')then
469  if(SFP_EmacPhyTxc(0)(0) = '1' and SFP_EmacPhyTxd(0)(7 downto 0) = x"fb")then
470  cs(289) <= '1';
471  else
472  cs(289) <= '0';
473  end if;
474  if(SFP_EmacPhyTxc(0)(0) = '1' and SFP_EmacPhyTxd(0)(7 downto 0) = x"fe")then
475  cs(290) <= '1';
476  elsif(SFP_EmacPhyTxc(0)(1) = '1' and SFP_EmacPhyTxd(0)(15 downto 8) = x"fe")then
477  cs(290) <= '1';
478  elsif(SFP_EmacPhyTxc(0)(2) = '1' and SFP_EmacPhyTxd(0)(23 downto 16) = x"fe")then
479  cs(290) <= '1';
480  elsif(SFP_EmacPhyTxc(0)(3) = '1' and SFP_EmacPhyTxd(0)(31 downto 24) = x"fe")then
481  cs(290) <= '1';
482  else
483  cs(290) <= '0';
484  end if;
485  end if;
486 end process;
487 
488 
489 -- chipscope data
490 cs(63 downto 0) <= xgmii_rxd_i(0);
491 cs(71 downto 64) <= xgmii_rxc_i(0);
492 cs(135 downto 72) <= xgmii_txd(0);
493 cs(143 downto 136) <= xgmii_txc(0);
494 cs(175 downto 144) <= SFP_EmacPhyTxd(0);
495 cs(179 downto 176) <= SFP_EmacPhyTxc(0);
496 cs(211 downto 180) <= SFP_PhyEmacRxd(0);
497 cs(215 downto 212) <= SFP_PhyEmacRxc(0);
498 
499 
500 
501 
502 
503 xgmii_rxd <= xgmii_rxd_i;
504 xgmii_rxc <= xgmii_rxc_i;
505 clk156 <= ClientClk;
506 gtx_rxresetdone <= SFP_RXRESETDONE;
507 process(ClientClk,gtx_reset,ClientClk_lock)
508 begin
509  if(gtx_reset = '1' or ClientClk_lock = '0')then
510  gtx_resetSyncRegs <= (others => '1');
511  elsif(ClientClk'event and ClientClk = '1')then
512  gtx_resetSyncRegs <= gtx_resetSyncRegs(1 downto 0) & '0';
513  end if;
514 end process;
515 process(txusrclk)
516 begin
517  if(txusrclk'event and txusrclk = '1')then
518  if(TXSEQ_cntr = "1000001")then
519  TXSEQ_cntr <= (others => '0');
520  else
521  TXSEQ_cntr <= TXSEQ_cntr + 1;
522  end if;
523  if(TXSEQ_cntr(0) = '1')then
524  GTX_TX_PAUSE <= and_reduce(TXSEQ_cntr(5 downto 1));
525  end if;
526  if(inh_TX(0) = '1')then
527  SFP_TXSEQUENCE(0) <= (others => '0');
528  elsif(TXSEQ_cntr(0) = '1')then
529  SFP_TXSEQUENCE(0) <= '0' & TXSEQ_cntr(6 downto 1);
530  end if;
531  if(inh_TX(1) = '1')then
532  SFP_TXSEQUENCE(1) <= (others => '0');
533  elsif(TXSEQ_cntr(0) = '1')then
534  SFP_TXSEQUENCE(1) <= '0' & TXSEQ_cntr(6 downto 1);
535  end if;
536  if(inh_TX(2) = '1')then
537  SFP_TXSEQUENCE(2) <= (others => '0');
538  elsif(TXSEQ_cntr(0) = '1')then
539  SFP_TXSEQUENCE(2) <= '0' & TXSEQ_cntr(6 downto 1);
540  end if;
541  end if;
542 end process;
543 process(TXUSRCLK,gtx_reset)
544 begin
545  if(gtx_reset = '1')then
546  reset_TXSyncRegs <= (others => '1');
547  elsif(TXUSRCLK'event and TXUSRCLK = '1')then
548  reset_TXSyncRegs <= reset_TXSyncRegs(1 downto 0) & '0';
549  end if;
550 end process;
551 process(TXUSRCLK,SFP_TX_FSM_RESET_DONE(0))
552 begin
553  if(SFP_TX_FSM_RESET_DONE(0) = '0')then
554  inh_TX(0) <= '1';
555  inh_TX_q(0) <= '1';
556  elsif(TXUSRCLK'event and TXUSRCLK = '1')then
557  if(TXSEQ_cntr(0) = '1' and TXSEQ_cntr(6) = '1')then
558  inh_TX(0) <= '0';
559  end if;
560  inh_TX_q(0) <= inh_TX(0);
561  end if;
562 end process;
563 process(TXUSRCLK,SFP_TX_FSM_RESET_DONE(1))
564 begin
565  if(SFP_TX_FSM_RESET_DONE(1) = '0')then
566  inh_TX(1) <= '1';
567  inh_TX_q(1) <= '1';
568  elsif(TXUSRCLK'event and TXUSRCLK = '1')then
569  if(TXSEQ_cntr(0) = '1' and TXSEQ_cntr(6) = '1')then
570  inh_TX(1) <= '0';
571  end if;
572  inh_TX_q(1) <= inh_TX(1);
573  end if;
574 end process;
575 process(TXUSRCLK,SFP_TX_FSM_RESET_DONE(2))
576 begin
577  if(SFP_TX_FSM_RESET_DONE(2) = '0')then
578  inh_TX(2) <= '1';
579  inh_TX_q(2) <= '1';
580  elsif(TXUSRCLK'event and TXUSRCLK = '1')then
581  if(TXSEQ_cntr(0) = '1' and TXSEQ_cntr(6) = '1')then
582  inh_TX(2) <= '0';
583  end if;
584  inh_TX_q(2) <= inh_TX(2);
585  end if;
586 end process;
587 g_XGbEPCS : for i in 0 to 2 generate
588  i_XGbEPCS: XGbEPCS32 PORT MAP (
589  reset => gtx_resetSyncRegs(2),
590  clk2x => ClientClk2X,
591  clk => ClientClk,
592  TXUSRCLK => txusrclk,
593  TX_high => TX_high,
594  RXUSRCLK => SFP_RXUSRCLK(i),
595  RXRESETDONE => SFP_RXRESETDONE(i),
596  inh_TX => inh_TX(i),
597  RESET_TXSync => reset_TXSyncRegs(2),
598  GTX_RXGEARBOXSLIP_OUT => SFP_RXGEARBOXSLIP(i),
599  GTX_TXD => SFP_TXD(i),
600  GTX_TXHEADER => SFP_TXHEADER(i),
601  GTX_TX_PAUSE => GTX_TX_PAUSE,
602  GTX_RXD => SFP_RXD(i),
603  GTX_RXDVLD => SFP_RXDVLD(i),
604  GTX_RXHEADER => SFP_RXHEADER(i),
605  GTX_RXHEADERVLD => SFP_RXHEADERVLD(i),
606  GTX_RXGOOD => SFP_RXGOOD(i),
607  EmacPhyTxC => SFP_EmacPhyTxc(i),
608  EmacPhyTxD => SFP_EmacPhyTxd(i),
609  PhyEmacRxC => SFP_PhyEmacRxC(i),
610  PhyEmacRxD => SFP_PhyEmacRxD(i)
611  );
612 end generate;
613 process(ClientClk)
614 begin
615  if(ClientClk'event and ClientClk = '1')then
616  ClientClkToggle <= not ClientClkToggle;
617  for i in 0 to 2 loop
618  xgmii_rxd_i(i) <= SFP_PhyEmacRxd(i) & SFP_PhyEmacRxd_q(i);
619  xgmii_rxc_i(i) <= SFP_PhyEmacRxc(i) & SFP_PhyEmacRxc_q(i);
620  end loop;
621  end if;
622 end process;
623 process(ClientClk2X)
624 begin
625  if(ClientClk2X'event and ClientClk2X = '1')then
626  ClientClkToggle_q <= ClientClkToggle;
627  SFP_PhyEmacRxd_q <= SFP_PhyEmacRxd;
628  SFP_PhyEmacRxc_q <= SFP_PhyEmacRxc;
629  TX_high <= ClientClkToggle_q xnor ClientClkToggle;
630  for i in 0 to 2 loop
631  if(TX_high = '1')then
632  SFP_EmacPhyTxd(i) <= xgmii_txd(i)(31 downto 0);
633  SFP_EmacPhyTxc(i) <= xgmii_txc(i)(3 downto 0);
634  else
635  SFP_EmacPhyTxd(i) <= xgmii_txd(i)(63 downto 32);
636  SFP_EmacPhyTxc(i) <= xgmii_txc(i)(7 downto 4);
637  end if;
638  end loop;
639  end if;
640 end process;
641 process(DRPclk)
642 begin
643  if(DRPclk'event and DRPclk = '1')then
644  for i in 0 to 2 loop
645  SFP_pd_q(i) <= SFP_pd_q(i)(2 downto 0) & SFP_pd(i)(0);
646  end loop;
647  if(SFP_pd_q(0)(3 downto 2) = "10" or SFP_pd_q(1)(3 downto 2) = "10" or SFP_pd_q(2)(3 downto 2) = "10")then
648  reset_cntr <= (others => '0');
649  elsif(reset_cntr(20) = '0')then
650  reset_cntr <= reset_cntr + 1;
651  end if;
652  reset_cntr20_q <= reset_cntr(20);
653  soft_reset <= not reset_cntr20_q and reset_cntr(20);
654  end if;
655 end process;
656 i_SFP3_init : SFP3_v2_7_init
657  generic map(N_SFP => N_SFP)
658  port map
659  (
660  SYSCLK_IN => DRPclk,
661  SOFT_RESET_IN => soft_reset,
662  DONT_RESET_ON_DATA_ERROR_IN => '0',
663  GT0_TX_FSM_RESET_DONE_OUT => SFP_TX_FSM_RESET_DONE(0),
664  GT0_RX_FSM_RESET_DONE_OUT => PCS_lock(0),
665  GT0_DATA_VALID_IN => SFP_RXGOOD(0),
666  GT1_TX_FSM_RESET_DONE_OUT => SFP_TX_FSM_RESET_DONE (1),
667  GT1_RX_FSM_RESET_DONE_OUT => PCS_lock(1),
668  GT1_DATA_VALID_IN => SFP_RXGOOD(1),
669  GT2_TX_FSM_RESET_DONE_OUT => SFP_TX_FSM_RESET_DONE(2),
670  GT2_RX_FSM_RESET_DONE_OUT => PCS_lock(2),
671  GT2_DATA_VALID_IN => SFP_RXGOOD(2),
672 
673 
674 
675 
676 
677  --_____________________________________________________________________
678  --_____________________________________________________________________
679  --GT0 (X1Y12)
680 
681  ---------------------------- Channel - DRP Ports --------------------------
682  GT0_DRPADDR_IN => SFP_drpaddr(0),
683  GT0_DRPCLK_IN => DRPclk,
684  GT0_DRPDI_IN => SFP_drpdi(0),
685  GT0_DRPDO_OUT => SFP_drpdo(0),
686  GT0_DRPEN_IN => SFP_drpen(0),
687  GT0_DRPRDY_OUT => SFP_drprdy(0),
688  GT0_DRPWE_IN => SFP_drpwe(0),
689  ------------------------------- Loopback Ports -----------------------------
690  GT0_LOOPBACK_IN => SFP_LOOPBACK_IN(0),
691  ------------------------------ Power-Down Ports ----------------------------
692  GT0_RXPD_IN => SFP_pd(0),
693  GT0_TXPD_IN => SFP_pd(0),
694  --------------------- RX Initialization and Reset Ports --------------------
695  GT0_RXUSERRDY_IN => SFP_rxuserrdy(0),
696  -------------------------- RX Margin Analysis Ports ------------------------
697  GT0_EYESCANDATAERROR_OUT => SFP_EYESCANDATAERROR_OUT(0),
698  ------------------------- Receive Ports - CDR Ports ------------------------
699  GT0_RXCDRLOCK_OUT => open,
700  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
701  GT0_RXUSRCLK_IN => SFP_RXUSRCLK(0),
702  GT0_RXUSRCLK2_IN => SFP_RXUSRCLK(0),
703  ------------------ Receive Ports - FPGA RX interface Ports -----------------
704  GT0_RXDATA_OUT => SFP_RXD_inv(0),
705  ------------------- Receive Ports - Pattern Checker Ports ------------------
706  GT0_RXPRBSERR_OUT => SFP_RXPRBSERR_OUT(0),
707  GT0_RXPRBSSEL_IN => SFP_RXPRBSSEL_IN(0),
708  ------------------- Receive Ports - Pattern Checker ports ------------------
709  GT0_RXPRBSCNTRESET_IN => '0',
710  --------------------------- Receive Ports - RX AFE -------------------------
711  GT0_GTXRXP_IN => SFP0_RXP,
712  ------------------------ Receive Ports - RX AFE Ports ----------------------
713  GT0_GTXRXN_IN => SFP0_RXN,
714  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
715  GT0_RXBUFRESET_IN => '0',
716  GT0_RXBUFSTATUS_OUT => open,
717  --------------- Receive Ports - RX Fabric Output Control Ports -------------
718  GT0_RXOUTCLK_OUT => SFP_rxoutclk(0),
719  ---------------------- Receive Ports - RX Gearbox Ports --------------------
720  GT0_RXDATAVALID_OUT => SFP_RXDVLD(0),
721  GT0_RXHEADER_OUT => SFP_RXHEADER(0),
722  GT0_RXHEADERVALID_OUT => SFP_RXHEADERVLD(0),
723  --------------------- Receive Ports - RX Gearbox Ports --------------------
724  GT0_RXGEARBOXSLIP_IN => SFP_RXGEARBOXSLIP(0),
725  ------------- Receive Ports - RX Initialization and Reset Ports ------------
726  GT0_GTRXRESET_IN => '0',
727  GT0_RXPMARESET_IN => '0',
728  ------------------ Receive Ports - RX Margin Analysis ports ----------------
729  GT0_RXLPMEN_IN => '0',
730  -------------- Receive Ports -RX Initialization and Reset Ports ------------
731  GT0_RXRESETDONE_OUT => SFP_rxresetdone(0),
732  --------------------- TX Initialization and Reset Ports --------------------
733  GT0_GTTXRESET_IN => '0',
734  GT0_TXUSERRDY_IN => SFP_txuserrdy(0),
735  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
736  GT0_TXUSRCLK_IN => txusrclk,
737  GT0_TXUSRCLK2_IN => txusrclk,
738  --------------- Transmit Ports - TX Configurable Driver Ports --------------
739  GT0_TXDIFFCTRL_IN => "1110",
740  GT0_TXINHIBIT_IN => '0',
741  GT0_TXMAINCURSOR_IN => (others => '0'),
742  ------------------ Transmit Ports - TX Data Path interface -----------------
743  GT0_TXDATA_IN => SFP_TXD_inv(0),
744  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
745  GT0_GTXTXN_OUT => SFP0_TXN,
746  GT0_GTXTXP_OUT => SFP0_TXP,
747  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
748  GT0_TXOUTCLK_OUT => SFP_TXOUTCLK(0),
749  GT0_TXOUTCLKFABRIC_OUT => open,
750  GT0_TXOUTCLKPCS_OUT => open,
751  --------------------- Transmit Ports - TX Gearbox Ports --------------------
752  GT0_TXHEADER_IN => SFP_TXHEADER(0),
753  GT0_TXSEQUENCE_IN => SFP_TXSEQUENCE(0),
754  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
755  GT0_TXRESETDONE_OUT => SFP_txresetdone(0),
756  ------------------ Transmit Ports - pattern Generator Ports ----------------
757  GT0_TXPRBSSEL_IN => SFP_TXPRBSSEL_IN(0),
758 
759 
760 
761 
762 
763 
764  --_____________________________________________________________________
765  --_____________________________________________________________________
766  --GT1 (X1Y13)
767 
768  ---------------------------- Channel - DRP Ports --------------------------
769  GT1_DRPADDR_IN => SFP_drpaddr(1),
770  GT1_DRPCLK_IN => DRPclk,
771  GT1_DRPDI_IN => SFP_drpdi(1),
772  GT1_DRPDO_OUT => SFP_drpdo(1),
773  GT1_DRPEN_IN => SFP_drpen(1),
774  GT1_DRPRDY_OUT => SFP_drprdy(1),
775  GT1_DRPWE_IN => SFP_drpwe(1),
776  ------------------------------- Loopback Ports -----------------------------
777  GT1_LOOPBACK_IN => SFP_LOOPBACK_IN(1),
778  ------------------------------ Power-Down Ports ----------------------------
779  GT1_RXPD_IN => SFP_pd(1),
780  GT1_TXPD_IN => SFP_pd(1),
781  --------------------- RX Initialization and Reset Ports --------------------
782  GT1_RXUSERRDY_IN => SFP_rxuserrdy(1),
783  -------------------------- RX Margin Analysis Ports ------------------------
784  GT1_EYESCANDATAERROR_OUT => SFP_EYESCANDATAERROR_OUT(1),
785  ------------------------- Receive Ports - CDR Ports ------------------------
786  GT1_RXCDRLOCK_OUT => open,
787  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
788  GT1_RXUSRCLK_IN => SFP_RXUSRCLK(1),
789  GT1_RXUSRCLK2_IN => SFP_RXUSRCLK(1),
790  ------------------ Receive Ports - FPGA RX interface Ports -----------------
791  GT1_RXDATA_OUT => SFP_RXD_inv(1),
792  ------------------- Receive Ports - Pattern Checker Ports ------------------
793  GT1_RXPRBSERR_OUT => SFP_RXPRBSERR_OUT(1),
794  GT1_RXPRBSSEL_IN => SFP_RXPRBSSEL_IN(1),
795  ------------------- Receive Ports - Pattern Checker ports ------------------
796  GT1_RXPRBSCNTRESET_IN => '0',
797  --------------------------- Receive Ports - RX AFE -------------------------
798  GT1_GTXRXP_IN => SFP1_RXP,
799  ------------------------ Receive Ports - RX AFE Ports ----------------------
800  GT1_GTXRXN_IN => SFP1_RXN,
801  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
802  GT1_RXBUFRESET_IN => '0',
803  GT1_RXBUFSTATUS_OUT => open,
804  --------------- Receive Ports - RX Fabric Output Control Ports -------------
805  GT1_RXOUTCLK_OUT => SFP_rxoutclk(1),
806  ---------------------- Receive Ports - RX Gearbox Ports --------------------
807  GT1_RXDATAVALID_OUT => SFP_RXDVLD(1),
808  GT1_RXHEADER_OUT => SFP_RXHEADER(1),
809  GT1_RXHEADERVALID_OUT => SFP_RXHEADERVLD(1),
810  --------------------- Receive Ports - RX Gearbox Ports --------------------
811  GT1_RXGEARBOXSLIP_IN => SFP_RXGEARBOXSLIP(1),
812  ------------- Receive Ports - RX Initialization and Reset Ports ------------
813  GT1_GTRXRESET_IN => '0',
814  GT1_RXPMARESET_IN => '0',
815  ------------------ Receive Ports - RX Margin Analysis ports ----------------
816  GT1_RXLPMEN_IN => '0',
817  -------------- Receive Ports -RX Initialization and Reset Ports ------------
818  GT1_RXRESETDONE_OUT => SFP_rxresetdone(1),
819  --------------------- TX Initialization and Reset Ports --------------------
820  GT1_GTTXRESET_IN => '0',
821  GT1_TXUSERRDY_IN => SFP_txuserrdy(1),
822  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
823  GT1_TXUSRCLK_IN => txusrclk,
824  GT1_TXUSRCLK2_IN => txusrclk,
825  --------------- Transmit Ports - TX Configurable Driver Ports --------------
826  GT1_TXDIFFCTRL_IN => "1110",
827  GT1_TXINHIBIT_IN => '0',
828  GT1_TXMAINCURSOR_IN => (others => '0'),
829  ------------------ Transmit Ports - TX Data Path interface -----------------
830  GT1_TXDATA_IN => SFP_TXD_inv(1),
831  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
832  GT1_GTXTXN_OUT => SFP1_TXN,
833  GT1_GTXTXP_OUT => SFP1_TXP,
834  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
835  GT1_TXOUTCLK_OUT => open,
836  GT1_TXOUTCLKFABRIC_OUT => open,
837  GT1_TXOUTCLKPCS_OUT => open,
838  --------------------- Transmit Ports - TX Gearbox Ports --------------------
839  GT1_TXHEADER_IN => SFP_TXHEADER(1),
840  GT1_TXSEQUENCE_IN => SFP_TXSEQUENCE(1),
841  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
842  GT1_TXRESETDONE_OUT => SFP_txresetdone(1),
843  ------------------ Transmit Ports - pattern Generator Ports ----------------
844  GT1_TXPRBSSEL_IN => SFP_TXPRBSSEL_IN(1),
845 
846 
847  --_____________________________________________________________________
848  --_____________________________________________________________________
849  --GT2 (X1Y14)
850 
851  ---------------------------- Channel - DRP Ports --------------------------
852  GT2_DRPADDR_IN => SFP_drpaddr(2),
853  GT2_DRPCLK_IN => DRPclk,
854  GT2_DRPDI_IN => SFP_drpdi(2),
855  GT2_DRPDO_OUT => SFP_drpdo(2),
856  GT2_DRPEN_IN => SFP_drpen(2),
857  GT2_DRPRDY_OUT => SFP_drprdy(2),
858  GT2_DRPWE_IN => SFP_drpwe(2),
859  ------------------------------- Loopback Ports -----------------------------
860  GT2_LOOPBACK_IN => SFP_LOOPBACK_IN(2),
861  ------------------------------ Power-Down Ports ----------------------------
862  GT2_RXPD_IN => SFP_pd(2),
863  GT2_TXPD_IN => SFP_pd(2),
864  --------------------- RX Initialization and Reset Ports --------------------
865  GT2_RXUSERRDY_IN => SFP_rxuserrdy(2),
866  -------------------------- RX Margin Analysis Ports ------------------------
867  GT2_EYESCANDATAERROR_OUT => SFP_EYESCANDATAERROR_OUT(2),
868  ------------------------- Receive Ports - CDR Ports ------------------------
869  GT2_RXCDRLOCK_OUT => open,
870  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
871  GT2_RXUSRCLK_IN => SFP_RXUSRCLK(2),
872  GT2_RXUSRCLK2_IN => SFP_RXUSRCLK(2),
873  ------------------ Receive Ports - FPGA RX interface Ports -----------------
874  GT2_RXDATA_OUT => SFP_RXD_inv(2),
875  ------------------- Receive Ports - Pattern Checker Ports ------------------
876  GT2_RXPRBSERR_OUT => SFP_RXPRBSERR_OUT(2),
877  GT2_RXPRBSSEL_IN => SFP_RXPRBSSEL_IN(2),
878  ------------------- Receive Ports - Pattern Checker ports ------------------
879  GT2_RXPRBSCNTRESET_IN => '0',
880  --------------------------- Receive Ports - RX AFE -------------------------
881  GT2_GTXRXP_IN => SFP2_RXP,
882  ------------------------ Receive Ports - RX AFE Ports ----------------------
883  GT2_GTXRXN_IN => SFP2_RXN,
884  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
885  GT2_RXBUFRESET_IN => '0',
886  GT2_RXBUFSTATUS_OUT => open,
887  --------------- Receive Ports - RX Fabric Output Control Ports -------------
888  GT2_RXOUTCLK_OUT => SFP_rxoutclk(2),
889  ---------------------- Receive Ports - RX Gearbox Ports --------------------
890  GT2_RXDATAVALID_OUT => SFP_RXDVLD(2),
891  GT2_RXHEADER_OUT => SFP_RXHEADER(2),
892  GT2_RXHEADERVALID_OUT => SFP_RXHEADERVLD(2),
893  --------------------- Receive Ports - RX Gearbox Ports --------------------
894  GT2_RXGEARBOXSLIP_IN => SFP_RXGEARBOXSLIP(2),
895  ------------- Receive Ports - RX Initialization and Reset Ports ------------
896  GT2_GTRXRESET_IN => '0',
897  GT2_RXPMARESET_IN => '0',
898  ------------------ Receive Ports - RX Margin Analysis ports ----------------
899  GT2_RXLPMEN_IN => '0',
900  -------------- Receive Ports -RX Initialization and Reset Ports ------------
901  GT2_RXRESETDONE_OUT => SFP_rxresetdone(2),
902  --------------------- TX Initialization and Reset Ports --------------------
903  GT2_GTTXRESET_IN => '0',
904  GT2_TXUSERRDY_IN => SFP_txuserrdy(2),
905  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
906  GT2_TXUSRCLK_IN => txusrclk,
907  GT2_TXUSRCLK2_IN => txusrclk,
908  --------------- Transmit Ports - TX Configurable Driver Ports --------------
909  GT2_TXDIFFCTRL_IN => "1110",
910  GT2_TXINHIBIT_IN => '0',
911  GT2_TXMAINCURSOR_IN => (others => '0'),
912  ------------------ Transmit Ports - TX Data Path interface -----------------
913  GT2_TXDATA_IN => SFP_TXD_inv(2),
914  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
915  GT2_GTXTXN_OUT => SFP2_TXN,
916  GT2_GTXTXP_OUT => SFP2_TXP,
917  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
918  GT2_TXOUTCLK_OUT => open,
919  GT2_TXOUTCLKFABRIC_OUT => open,
920  GT2_TXOUTCLKPCS_OUT => open,
921  --------------------- Transmit Ports - TX Gearbox Ports --------------------
922  GT2_TXHEADER_IN => SFP_TXHEADER(2),
923  GT2_TXSEQUENCE_IN => SFP_TXSEQUENCE(2),
924  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
925  GT2_TXRESETDONE_OUT => SFP_txresetdone(2),
926  ------------------ Transmit Ports - pattern Generator Ports ----------------
927  GT2_TXPRBSSEL_IN => SFP_TXPRBSSEL_IN(2),
928 
929 
930  --____________________________COMMON PORTS________________________________
931  ---------------------- Common Block - Ref Clock Ports ---------------------
932  GT0_GTREFCLK0_COMMON_IN => SFP_REFCLK,
933  ------------------------- Common Block - QPLL Ports ------------------------
934  GT0_QPLLLOCK_OUT => qplllock,
935  GT0_QPLLLOCKDETCLK_IN => DRPclk,
936  GT0_QPLLRESET_IN => qpllreset
937 
938  );
939 process(SFP_TXD,SFP_RXD,SFP_RXD_inv)
940  begin
941  for j in 0 to 2 loop
942  for i in 0 to 31 loop
943  SFP_TXD_inv(j)(i) <= SFP_TXD(j)(31-i);
944  SFP_RXD(j)(i) <= SFP_RXD_inv(j)(31-i);
945  end loop;
946  end loop;
947 end process;
948 i_REFCLK : IBUFDS_GTE2 port map(O => SFP_REFCLK, ODIV2 => open, CEB => '0', I => SFP_REFCLK_P, IB => SFP_REFCLK_N);
949 i_txusrclk : BUFG port map (I => SFP_TXOUTCLK(0), O => txusrclk);
950 g_SFP_rxusrclk : for i in 0 to 2 generate
951  i_SFP_rxusrclk : BUFG port map (I => SFP_RXOUTCLK(i), O => SFP_rxusrclk(i));
952 end generate;
953 i_REFCLK2X_in: bufg port map(i => SFP_REFCLK, o => REFCLK2X_in);
954 i_ClientClk2X : BUFG port map (I => ClientClk2X_dcm, O => ClientClk2X);
955 i_ClientClk : BUFG port map (I => ClientClk_dcm, O => ClientClk);
956 i_REFCLK2XPLLRST : SRL16 generic map(INIT => x"ffff")
957  port map (
958  Q => REFCLK2XPLLRST , -- SRL data output
959  A0 => '1', -- Select[0] input
960  A1 => '1', -- Select[1] input
961  A2 => '1', -- Select[2] input
962  A3 => '1', -- Select[3] input
963  CLK => REFCLK2X_in, -- Clock input
964  D => '0' -- SRL data input
965  );
966 i_REFCLK2XPLL : PLLE2_BASE
967  generic map (
968  BANDWIDTH => "OPTIMIZED", -- OPTIMIZED, HIGH, LOW
969  CLKFBOUT_MULT => 8, -- Multiply value for all CLKOUT, (2-64)
970  CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB, (-360.000-360.000).
971  CLKIN1_PERIOD => 6.4, -- Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
972  -- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for each CLKOUT (1-128)
973  CLKOUT0_DIVIDE => 4,
974  DIVCLK_DIVIDE => 1, -- Master division value, (1-56)
975  REF_JITTER1 => 0.0, -- Reference input jitter in UI, (0.000-0.999).
976  STARTUP_WAIT => "FALSE" -- Delay DONE until PLL Locks, ("TRUE"/"FALSE")
977  )
978  port map (
979  -- Clock Outputs: 1-bit (each) output: User configurable clock outputs
980  CLKOUT0 => ClientClk2X_dcm,
981  -- Feedback Clocks: 1-bit (each) output: Clock feedback ports
982  CLKFBOUT => ClientClk_dcm, -- 1-bit output: Feedback clock
983  -- Status Port: 1-bit (each) output: PLL status ports
984  LOCKED => ClientClk_lock , -- 1-bit output: LOCK
985  -- Clock Input: 1-bit (each) input: Clock input
986  CLKIN1 => REFCLK2X_in, -- 1-bit input: Input clock
987  -- Control Ports: 1-bit (each) input: PLL control ports
988  PWRDWN => '0', -- 1-bit input: Power-down
989  RST => REFCLK2XPLLRST , -- 1-bit input: Reset
990  -- Feedback Clocks: 1-bit (each) input: Clock feedback ports
991  CLKFBIN => ClientClk -- 1-bit input: Feedback clock
992  );
993 
994 
995 end Behavioral;
996 
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