3 use IEEE.STD_LOGIC_1164.
ALL;
4 use ieee.std_logic_unsigned.
all;
10 use UNISIM.VComponents.
all;
13 Port ( sys_reset : in ;
-- active high reset of all logic but GTX
17 LinkWe : in (2 downto 0);
18 LinkCtrl : in (2 downto 0);
19 LinkData : in array3x64;
21 LinkDown : out (2 downto 0);
22 LinkFull : out (2 downto 0);
24 -- ack_cnt : out (2 downto 0); --
1 ck pulse (txusrclk) indicating a received acknowledge
25 -- pckt_cnt : out (2 downto 0); --
1 ck pulse (txusrclk) indicating a transmit packet
26 -- retransmit_cnt : out (2 downto 0); --
1 ck pulse (txusrclk) indicating a retransmit packet
27 -- event_cnt : out (2 downto 0); --
1 ck pulse (sys_clk) indicating a sent event
28 sync_loss : out (2 downto 0);
-- goes to '1' (rxusrclk) when SERDES is out of synch
29 status_ce : in (2 downto 0);
-- not implemented yet
30 status_addr : in (15 downto 0);
-- not implemented yet
31 status_port : out array3x64;
-- first 32 bits are hard-wired
33 txusrclk_o : out ;
-- reconstructed tx clock, to be used to clock sending circuitry
34 rxusrclk_o : out ;
-- reconstructed rx clock, to be used to clock receiving circuitry
36 gtx_reset : in ;
-- full reset of GTX only
37 gtx_refclk_p : in ;
-- iob for refclk neg
38 gtx_refclk_n : in ;
-- iob for refclk neg
39 sfp_rxn : in (2 downto 0);
-- sfp iobs
40 sfp_rxp : in (2 downto 0);
41 sfp_txn : out (2 downto 0);
42 sfp_txp : out (2 downto 0)
54 LINKData :
in (
63 downto 0);
55 src_ID :
in (
15 downto 0);
56 inject_err :
in (
17 downto 0);
58 Addr :
in (
15 downto 0);
59 status_data :
out (
63 downto 0);
66 SD_Data_o :
out (
63 downto 0);
67 SD_Kb_o :
out (
7 downto 0);
69 SD_Data_i :
in (
63 downto 0);
70 SD_Kb_i :
in (
7 downto 0);
72 Serdes_status :
in (
31 downto 0)
77 generic(N_SFP : :=
3);
91 xgmii_txd :
IN array3x64;
92 xgmii_txc :
IN array3x8;
100 PCS_lock :
OUT (
2 downto 0);
101 gtx_rxresetdone :
OUT (
2 downto 0);
102 xgmii_rxd :
OUT array3x64;
103 xgmii_rxc :
OUT array3x8
109 signal sys_reset_bar : ;
110 signal serdes_core_clk156_out : ;
111 signal txdata, rxdata : array3x64;
112 signal rxcharisk, txcharisk, rxchariscomma, gtx_rxnotintable : array3x8;
113 signal gtx_rxresetdone : (2 downto 0);
114 signal PCS_lock : (2 downto 0);
115 signal serdes_status : array3x32 := (others => (others => '0'));
117 txusrclk_o <= serdes_core_clk156_out;
118 rxusrclk_o <= serdes_core_clk156_out;
119 sync_loss <= not PCS_lock;
120 g_SLINK_opt : for i in 0 to 2 generate
124 reset => sys_reset_bar,
-- needs an active low reset
126 -- DATA interface from FED
127 LINKWe =>
not LinkWe
(i
),
128 LINKCtrl => LinkCtrl
(i
),
129 LINKData => LinkData
(i
),
131 inject_err =>
(others =>'0'
),
134 status_data => status_port
(i
),
135 serdes_status => serdes_status
(i
),
136 LINKDown => LinkDown
(i
),
137 LINK_LFF => LinkFull
(i
),
139 clock => serdes_core_clk156_out,
--clk_156_service, -- clk tx from SERDES
140 serdes_init => serdes_status
(i
)(0),
-- status that comes back from GTX
141 SD_Data_o => TXDATA
(i
),
-- data sent to serdes (64 )
142 SD_Kb_o => TXCHARISK
(i
),
-- control K associated to SD_Data_o (8 bits)
143 clock_r => serdes_core_clk156_out,
-- reconstructed clock from SERDES
144 SD_Data_i => RXDATA
(i
),
-- return data from SERDES 64
145 SD_Kb_i => RXCHARISK
(i
) -- return control K associated to SD_Data_i (8 bits)
147 serdes_status(i)(0) <= PCS_lock(i);
148 serdes_status(i)(1) <= gtx_rxresetdone(i);
150 sys_reset_bar <= not(sys_reset);
154 gtx_reset => gtx_reset,
156 SFP0_RXN => sfp_rxn
(0),
157 SFP0_RXP => sfp_rxp
(0),
158 SFP1_RXN => sfp_rxn
(1),
159 SFP1_RXP => sfp_rxp
(1),
160 SFP2_RXN => sfp_rxn
(2),
161 SFP2_RXP => sfp_rxp
(2),
162 SFP0_TXN => sfp_txn
(0),
163 SFP0_TXP => sfp_txp
(0),
164 SFP1_TXN => sfp_txn
(1),
165 SFP1_TXP => sfp_txp
(1),
166 SFP2_TXN => sfp_txn
(2),
167 SFP2_TXP => sfp_txp
(2),
168 SFP_REFCLK_P => gtx_refclk_p,
169 SFP_REFCLK_N => gtx_refclk_n,
170 clk156 => serdes_core_clk156_out,
171 PCS_lock => PCS_lock,
172 gtx_rxresetdone => gtx_rxresetdone,
174 xgmii_txc => TXCHARISK,
176 xgmii_rxc => RXCHARISK