AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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AMC_wrapper.vhd
1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 11:15:28 03/21/2013
6 -- Design Name:
7 -- Module Name: AMC_wrapper - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 library IEEE;
21 use IEEE.STD_LOGIC_1164.ALL;
22 use IEEE.STD_LOGIC_ARITH.ALL;
23 use IEEE.STD_LOGIC_UNSIGNED.ALL;
24 use IEEE.std_logic_misc.all;
25 use work.amc13_pack.all;
26 
27 -- Uncomment the following library declaration if using
28 -- arithmetic functions with Signed or Unsigned values
29 --use IEEE.NUMERIC_STD.ALL;
30 
31 -- Uncomment the following library declaration if instantiating
32 -- any Xilinx primitives in this code.
33 library UNISIM;
34 use UNISIM.VComponents.all;
35 
36 entity AMC_wrapper is
37  Port ( DRPclk : in STD_LOGIC;
38  SOFT_RESET : in STD_LOGIC;
39  UsrClk : in STD_LOGIC;
40  test : in STD_LOGIC;
41  Dis_pd : in STD_LOGIC;
42  AMC_en : in STD_LOGIC_VECTOR(11 downto 0);
43  RXDATA : out array12X16;
44  RxBufOvf : out STD_LOGIC_VECTOR(11 downto 0);
45  RxBufUdf : out STD_LOGIC_VECTOR(11 downto 0);
46  sampleRatio : in STD_LOGIC;
47  updateRatio : in STD_LOGIC;
48  RxClkRatio : out array12x21;
49  rxprbserr : out STD_LOGIC_VECTOR(11 downto 0);
50  rxprbssel : in array12X3;
51  RXNOTINTABLE : out array12X2;
52  rxcommaalignen : in STD_LOGIC_VECTOR(11 downto 0);
53  rxchariscomma : out array12X2;
54  rxcharisk : out array12X2;
55  rxresetdone : out STD_LOGIC_VECTOR(11 downto 0);
56  txdiffctrl : in array12X4;
57  TXDATA : in array12X16;
58  txoutclk : out STD_LOGIC_VECTOR(11 downto 0);
59  txcharisk : in array12X2;
60  txresetdone : out STD_LOGIC_VECTOR(11 downto 0);
61  txprbssel : in array12X3;
62  qpll_lock : out STD_LOGIC_VECTOR(2 downto 0);
63  txfsmresetdone : out STD_LOGIC_VECTOR(11 downto 0);
64  rxfsmresetdone : out STD_LOGIC_VECTOR(11 downto 0);
65  data_valid : in STD_LOGIC_VECTOR(11 downto 0);
66  AMC_REFCLK : in STD_LOGIC;
67  RXN : in STD_LOGIC_VECTOR(11 downto 0);
68  RXP : in STD_LOGIC_VECTOR(11 downto 0);
69  TXN : out STD_LOGIC_VECTOR(11 downto 0);
70  TXP : out STD_LOGIC_VECTOR(11 downto 0)
71  );
72 end AMC_wrapper;
73 architecture Behavioral of AMC_wrapper is
74 component amc_gtx5Gpd_init
75 generic
76 (
77  EXAMPLE_SIM_GTRESET_SPEEDUP : string := "TRUE"; -- simulation setting for GT SecureIP model
78  EXAMPLE_SIMULATION : integer := 0; -- Set to 1 for simulation
79 
80  STABLE_CLOCK_PERIOD : integer := 20;
81  -- Set to 1 for simulation
82  EXAMPLE_USE_CHIPSCOPE : integer := 0 -- Set to 1 to use Chipscope to drive resets
83 
84 );
85 port
86 (
87  SYSCLK_IN : IN std_logic;
88  SOFT_RESET_IN : IN std_logic;
89  DONT_RESET_ON_DATA_ERROR_IN : IN std_logic;
90  GT0_DATA_VALID_IN : IN std_logic;
91  GT1_DATA_VALID_IN : IN std_logic;
92  GT2_DATA_VALID_IN : IN std_logic;
93  GT3_DATA_VALID_IN : IN std_logic;
94  GT4_DATA_VALID_IN : IN std_logic;
95  GT5_DATA_VALID_IN : IN std_logic;
96  GT6_DATA_VALID_IN : IN std_logic;
97  GT7_DATA_VALID_IN : IN std_logic;
98  GT8_DATA_VALID_IN : IN std_logic;
99  GT9_DATA_VALID_IN : IN std_logic;
100  GT10_DATA_VALID_IN : IN std_logic;
101  GT11_DATA_VALID_IN : IN std_logic;
102  gt0_drpaddr_in : IN std_logic_vector(8 downto 0);
103  gt0_drpclk_in : IN std_logic;
104  gt0_drpdi_in : IN std_logic_vector(15 downto 0);
105  gt0_drpen_in : IN std_logic;
106  gt0_drpwe_in : IN std_logic;
107  gt0_loopback_in : IN std_logic_vector(2 downto 0);
108  gt0_rxpd_in : IN std_logic_vector(1 downto 0);
109  gt0_txpd_in : IN std_logic_vector(1 downto 0);
110  gt0_eyescanreset_in : IN std_logic;
111  gt0_rxuserrdy_in : IN std_logic;
112  gt0_eyescantrigger_in : IN std_logic;
113  gt0_rxusrclk_in : IN std_logic;
114  gt0_rxusrclk2_in : IN std_logic;
115  gt0_rxprbssel_in : IN std_logic_vector(2 downto 0);
116  gt0_rxprbscntreset_in : IN std_logic;
117  gt0_gtxrxp_in : IN std_logic;
118  gt0_gtxrxn_in : IN std_logic;
119  gt0_rxmcommaalignen_in : IN std_logic;
120  gt0_rxpcommaalignen_in : IN std_logic;
121  gt0_rxdfelpmreset_in : IN std_logic;
122  gt0_rxmonitorsel_in : IN std_logic_vector(1 downto 0);
123  gt0_gtrxreset_in : IN std_logic;
124  gt0_rxpmareset_in : IN std_logic;
125  gt0_gttxreset_in : IN std_logic;
126  gt0_txuserrdy_in : IN std_logic;
127  gt0_txusrclk_in : IN std_logic;
128  gt0_txusrclk2_in : IN std_logic;
129  gt0_txdiffctrl_in : IN std_logic_vector(3 downto 0);
130  gt0_txdata_in : IN std_logic_vector(15 downto 0);
131  gt0_txcharisk_in : IN std_logic_vector(1 downto 0);
132  gt0_txprbssel_in : IN std_logic_vector(2 downto 0);
133  gt1_drpaddr_in : IN std_logic_vector(8 downto 0);
134  gt1_drpclk_in : IN std_logic;
135  gt1_drpdi_in : IN std_logic_vector(15 downto 0);
136  gt1_drpen_in : IN std_logic;
137  gt1_drpwe_in : IN std_logic;
138  gt1_loopback_in : IN std_logic_vector(2 downto 0);
139  gt1_rxpd_in : IN std_logic_vector(1 downto 0);
140  gt1_txpd_in : IN std_logic_vector(1 downto 0);
141  gt1_eyescanreset_in : IN std_logic;
142  gt1_rxuserrdy_in : IN std_logic;
143  gt1_eyescantrigger_in : IN std_logic;
144  gt1_rxusrclk_in : IN std_logic;
145  gt1_rxusrclk2_in : IN std_logic;
146  gt1_rxprbssel_in : IN std_logic_vector(2 downto 0);
147  gt1_rxprbscntreset_in : IN std_logic;
148  gt1_gtxrxp_in : IN std_logic;
149  gt1_gtxrxn_in : IN std_logic;
150  gt1_rxmcommaalignen_in : IN std_logic;
151  gt1_rxpcommaalignen_in : IN std_logic;
152  gt1_rxdfelpmreset_in : IN std_logic;
153  gt1_rxmonitorsel_in : IN std_logic_vector(1 downto 0);
154  gt1_gtrxreset_in : IN std_logic;
155  gt1_rxpmareset_in : IN std_logic;
156  gt1_gttxreset_in : IN std_logic;
157  gt1_txuserrdy_in : IN std_logic;
158  gt1_txusrclk_in : IN std_logic;
159  gt1_txusrclk2_in : IN std_logic;
160  gt1_txdiffctrl_in : IN std_logic_vector(3 downto 0);
161  gt1_txdata_in : IN std_logic_vector(15 downto 0);
162  gt1_txcharisk_in : IN std_logic_vector(1 downto 0);
163  gt1_txprbssel_in : IN std_logic_vector(2 downto 0);
164  gt2_drpaddr_in : IN std_logic_vector(8 downto 0);
165  gt2_drpclk_in : IN std_logic;
166  gt2_drpdi_in : IN std_logic_vector(15 downto 0);
167  gt2_drpen_in : IN std_logic;
168  gt2_drpwe_in : IN std_logic;
169  gt2_loopback_in : IN std_logic_vector(2 downto 0);
170  gt2_rxpd_in : IN std_logic_vector(1 downto 0);
171  gt2_txpd_in : IN std_logic_vector(1 downto 0);
172  gt2_eyescanreset_in : IN std_logic;
173  gt2_rxuserrdy_in : IN std_logic;
174  gt2_eyescantrigger_in : IN std_logic;
175  gt2_rxusrclk_in : IN std_logic;
176  gt2_rxusrclk2_in : IN std_logic;
177  gt2_rxprbssel_in : IN std_logic_vector(2 downto 0);
178  gt2_rxprbscntreset_in : IN std_logic;
179  gt2_gtxrxp_in : IN std_logic;
180  gt2_gtxrxn_in : IN std_logic;
181  gt2_rxmcommaalignen_in : IN std_logic;
182  gt2_rxpcommaalignen_in : IN std_logic;
183  gt2_rxdfelpmreset_in : IN std_logic;
184  gt2_rxmonitorsel_in : IN std_logic_vector(1 downto 0);
185  gt2_gtrxreset_in : IN std_logic;
186  gt2_rxpmareset_in : IN std_logic;
187  gt2_gttxreset_in : IN std_logic;
188  gt2_txuserrdy_in : IN std_logic;
189  gt2_txusrclk_in : IN std_logic;
190  gt2_txusrclk2_in : IN std_logic;
191  gt2_txdiffctrl_in : IN std_logic_vector(3 downto 0);
192  gt2_txdata_in : IN std_logic_vector(15 downto 0);
193  gt2_txcharisk_in : IN std_logic_vector(1 downto 0);
194  gt2_txprbssel_in : IN std_logic_vector(2 downto 0);
195  gt3_drpaddr_in : IN std_logic_vector(8 downto 0);
196  gt3_drpclk_in : IN std_logic;
197  gt3_drpdi_in : IN std_logic_vector(15 downto 0);
198  gt3_drpen_in : IN std_logic;
199  gt3_drpwe_in : IN std_logic;
200  gt3_loopback_in : IN std_logic_vector(2 downto 0);
201  gt3_rxpd_in : IN std_logic_vector(1 downto 0);
202  gt3_txpd_in : IN std_logic_vector(1 downto 0);
203  gt3_eyescanreset_in : IN std_logic;
204  gt3_rxuserrdy_in : IN std_logic;
205  gt3_eyescantrigger_in : IN std_logic;
206  gt3_rxusrclk_in : IN std_logic;
207  gt3_rxusrclk2_in : IN std_logic;
208  gt3_rxprbssel_in : IN std_logic_vector(2 downto 0);
209  gt3_rxprbscntreset_in : IN std_logic;
210  gt3_gtxrxp_in : IN std_logic;
211  gt3_gtxrxn_in : IN std_logic;
212  gt3_rxmcommaalignen_in : IN std_logic;
213  gt3_rxpcommaalignen_in : IN std_logic;
214  gt3_rxdfelpmreset_in : IN std_logic;
215  gt3_rxmonitorsel_in : IN std_logic_vector(1 downto 0);
216  gt3_gtrxreset_in : IN std_logic;
217  gt3_rxpmareset_in : IN std_logic;
218  gt3_gttxreset_in : IN std_logic;
219  gt3_txuserrdy_in : IN std_logic;
220  gt3_txusrclk_in : IN std_logic;
221  gt3_txusrclk2_in : IN std_logic;
222  gt3_txdiffctrl_in : IN std_logic_vector(3 downto 0);
223  gt3_txdata_in : IN std_logic_vector(15 downto 0);
224  gt3_txcharisk_in : IN std_logic_vector(1 downto 0);
225  gt3_txprbssel_in : IN std_logic_vector(2 downto 0);
226  gt4_drpaddr_in : IN std_logic_vector(8 downto 0);
227  gt4_drpclk_in : IN std_logic;
228  gt4_drpdi_in : IN std_logic_vector(15 downto 0);
229  gt4_drpen_in : IN std_logic;
230  gt4_drpwe_in : IN std_logic;
231  gt4_loopback_in : IN std_logic_vector(2 downto 0);
232  gt4_rxpd_in : IN std_logic_vector(1 downto 0);
233  gt4_txpd_in : IN std_logic_vector(1 downto 0);
234  gt4_eyescanreset_in : IN std_logic;
235  gt4_rxuserrdy_in : IN std_logic;
236  gt4_eyescantrigger_in : IN std_logic;
237  gt4_rxusrclk_in : IN std_logic;
238  gt4_rxusrclk2_in : IN std_logic;
239  gt4_rxprbssel_in : IN std_logic_vector(2 downto 0);
240  gt4_rxprbscntreset_in : IN std_logic;
241  gt4_gtxrxp_in : IN std_logic;
242  gt4_gtxrxn_in : IN std_logic;
243  gt4_rxmcommaalignen_in : IN std_logic;
244  gt4_rxpcommaalignen_in : IN std_logic;
245  gt4_rxdfelpmreset_in : IN std_logic;
246  gt4_rxmonitorsel_in : IN std_logic_vector(1 downto 0);
247  gt4_gtrxreset_in : IN std_logic;
248  gt4_rxpmareset_in : IN std_logic;
249  gt4_gttxreset_in : IN std_logic;
250  gt4_txuserrdy_in : IN std_logic;
251  gt4_txusrclk_in : IN std_logic;
252  gt4_txusrclk2_in : IN std_logic;
253  gt4_txdiffctrl_in : IN std_logic_vector(3 downto 0);
254  gt4_txdata_in : IN std_logic_vector(15 downto 0);
255  gt4_txcharisk_in : IN std_logic_vector(1 downto 0);
256  gt4_txprbssel_in : IN std_logic_vector(2 downto 0);
257  gt5_drpaddr_in : IN std_logic_vector(8 downto 0);
258  gt5_drpclk_in : IN std_logic;
259  gt5_drpdi_in : IN std_logic_vector(15 downto 0);
260  gt5_drpen_in : IN std_logic;
261  gt5_drpwe_in : IN std_logic;
262  gt5_loopback_in : IN std_logic_vector(2 downto 0);
263  gt5_rxpd_in : IN std_logic_vector(1 downto 0);
264  gt5_txpd_in : IN std_logic_vector(1 downto 0);
265  gt5_eyescanreset_in : IN std_logic;
266  gt5_rxuserrdy_in : IN std_logic;
267  gt5_eyescantrigger_in : IN std_logic;
268  gt5_rxusrclk_in : IN std_logic;
269  gt5_rxusrclk2_in : IN std_logic;
270  gt5_rxprbssel_in : IN std_logic_vector(2 downto 0);
271  gt5_rxprbscntreset_in : IN std_logic;
272  gt5_gtxrxp_in : IN std_logic;
273  gt5_gtxrxn_in : IN std_logic;
274  gt5_rxmcommaalignen_in : IN std_logic;
275  gt5_rxpcommaalignen_in : IN std_logic;
276  gt5_rxdfelpmreset_in : IN std_logic;
277  gt5_rxmonitorsel_in : IN std_logic_vector(1 downto 0);
278  gt5_gtrxreset_in : IN std_logic;
279  gt5_rxpmareset_in : IN std_logic;
280  gt5_gttxreset_in : IN std_logic;
281  gt5_txuserrdy_in : IN std_logic;
282  gt5_txusrclk_in : IN std_logic;
283  gt5_txusrclk2_in : IN std_logic;
284  gt5_txdiffctrl_in : IN std_logic_vector(3 downto 0);
285  gt5_txdata_in : IN std_logic_vector(15 downto 0);
286  gt5_txcharisk_in : IN std_logic_vector(1 downto 0);
287  gt5_txprbssel_in : IN std_logic_vector(2 downto 0);
288  gt6_drpaddr_in : IN std_logic_vector(8 downto 0);
289  gt6_drpclk_in : IN std_logic;
290  gt6_drpdi_in : IN std_logic_vector(15 downto 0);
291  gt6_drpen_in : IN std_logic;
292  gt6_drpwe_in : IN std_logic;
293  gt6_loopback_in : IN std_logic_vector(2 downto 0);
294  gt6_rxpd_in : IN std_logic_vector(1 downto 0);
295  gt6_txpd_in : IN std_logic_vector(1 downto 0);
296  gt6_eyescanreset_in : IN std_logic;
297  gt6_rxuserrdy_in : IN std_logic;
298  gt6_eyescantrigger_in : IN std_logic;
299  gt6_rxusrclk_in : IN std_logic;
300  gt6_rxusrclk2_in : IN std_logic;
301  gt6_rxprbssel_in : IN std_logic_vector(2 downto 0);
302  gt6_rxprbscntreset_in : IN std_logic;
303  gt6_gtxrxp_in : IN std_logic;
304  gt6_gtxrxn_in : IN std_logic;
305  gt6_rxmcommaalignen_in : IN std_logic;
306  gt6_rxpcommaalignen_in : IN std_logic;
307  gt6_rxdfelpmreset_in : IN std_logic;
308  gt6_rxmonitorsel_in : IN std_logic_vector(1 downto 0);
309  gt6_gtrxreset_in : IN std_logic;
310  gt6_rxpmareset_in : IN std_logic;
311  gt6_gttxreset_in : IN std_logic;
312  gt6_txuserrdy_in : IN std_logic;
313  gt6_txusrclk_in : IN std_logic;
314  gt6_txusrclk2_in : IN std_logic;
315  gt6_txdiffctrl_in : IN std_logic_vector(3 downto 0);
316  gt6_txdata_in : IN std_logic_vector(15 downto 0);
317  gt6_txcharisk_in : IN std_logic_vector(1 downto 0);
318  gt6_txprbssel_in : IN std_logic_vector(2 downto 0);
319  gt7_drpaddr_in : IN std_logic_vector(8 downto 0);
320  gt7_drpclk_in : IN std_logic;
321  gt7_drpdi_in : IN std_logic_vector(15 downto 0);
322  gt7_drpen_in : IN std_logic;
323  gt7_drpwe_in : IN std_logic;
324  gt7_loopback_in : IN std_logic_vector(2 downto 0);
325  gt7_rxpd_in : IN std_logic_vector(1 downto 0);
326  gt7_txpd_in : IN std_logic_vector(1 downto 0);
327  gt7_eyescanreset_in : IN std_logic;
328  gt7_rxuserrdy_in : IN std_logic;
329  gt7_eyescantrigger_in : IN std_logic;
330  gt7_rxusrclk_in : IN std_logic;
331  gt7_rxusrclk2_in : IN std_logic;
332  gt7_rxprbssel_in : IN std_logic_vector(2 downto 0);
333  gt7_rxprbscntreset_in : IN std_logic;
334  gt7_gtxrxp_in : IN std_logic;
335  gt7_gtxrxn_in : IN std_logic;
336  gt7_rxmcommaalignen_in : IN std_logic;
337  gt7_rxpcommaalignen_in : IN std_logic;
338  gt7_rxdfelpmreset_in : IN std_logic;
339  gt7_rxmonitorsel_in : IN std_logic_vector(1 downto 0);
340  gt7_gtrxreset_in : IN std_logic;
341  gt7_rxpmareset_in : IN std_logic;
342  gt7_gttxreset_in : IN std_logic;
343  gt7_txuserrdy_in : IN std_logic;
344  gt7_txusrclk_in : IN std_logic;
345  gt7_txusrclk2_in : IN std_logic;
346  gt7_txdiffctrl_in : IN std_logic_vector(3 downto 0);
347  gt7_txdata_in : IN std_logic_vector(15 downto 0);
348  gt7_txcharisk_in : IN std_logic_vector(1 downto 0);
349  gt7_txprbssel_in : IN std_logic_vector(2 downto 0);
350  gt8_drpaddr_in : IN std_logic_vector(8 downto 0);
351  gt8_drpclk_in : IN std_logic;
352  gt8_drpdi_in : IN std_logic_vector(15 downto 0);
353  gt8_drpen_in : IN std_logic;
354  gt8_drpwe_in : IN std_logic;
355  gt8_loopback_in : IN std_logic_vector(2 downto 0);
356  gt8_rxpd_in : IN std_logic_vector(1 downto 0);
357  gt8_txpd_in : IN std_logic_vector(1 downto 0);
358  gt8_eyescanreset_in : IN std_logic;
359  gt8_rxuserrdy_in : IN std_logic;
360  gt8_eyescantrigger_in : IN std_logic;
361  gt8_rxusrclk_in : IN std_logic;
362  gt8_rxusrclk2_in : IN std_logic;
363  gt8_rxprbssel_in : IN std_logic_vector(2 downto 0);
364  gt8_rxprbscntreset_in : IN std_logic;
365  gt8_gtxrxp_in : IN std_logic;
366  gt8_gtxrxn_in : IN std_logic;
367  gt8_rxmcommaalignen_in : IN std_logic;
368  gt8_rxpcommaalignen_in : IN std_logic;
369  gt8_rxdfelpmreset_in : IN std_logic;
370  gt8_rxmonitorsel_in : IN std_logic_vector(1 downto 0);
371  gt8_gtrxreset_in : IN std_logic;
372  gt8_rxpmareset_in : IN std_logic;
373  gt8_gttxreset_in : IN std_logic;
374  gt8_txuserrdy_in : IN std_logic;
375  gt8_txusrclk_in : IN std_logic;
376  gt8_txusrclk2_in : IN std_logic;
377  gt8_txdiffctrl_in : IN std_logic_vector(3 downto 0);
378  gt8_txdata_in : IN std_logic_vector(15 downto 0);
379  gt8_txcharisk_in : IN std_logic_vector(1 downto 0);
380  gt8_txprbssel_in : IN std_logic_vector(2 downto 0);
381  gt9_drpaddr_in : IN std_logic_vector(8 downto 0);
382  gt9_drpclk_in : IN std_logic;
383  gt9_drpdi_in : IN std_logic_vector(15 downto 0);
384  gt9_drpen_in : IN std_logic;
385  gt9_drpwe_in : IN std_logic;
386  gt9_loopback_in : IN std_logic_vector(2 downto 0);
387  gt9_rxpd_in : IN std_logic_vector(1 downto 0);
388  gt9_txpd_in : IN std_logic_vector(1 downto 0);
389  gt9_eyescanreset_in : IN std_logic;
390  gt9_rxuserrdy_in : IN std_logic;
391  gt9_eyescantrigger_in : IN std_logic;
392  gt9_rxusrclk_in : IN std_logic;
393  gt9_rxusrclk2_in : IN std_logic;
394  gt9_rxprbssel_in : IN std_logic_vector(2 downto 0);
395  gt9_rxprbscntreset_in : IN std_logic;
396  gt9_gtxrxp_in : IN std_logic;
397  gt9_gtxrxn_in : IN std_logic;
398  gt9_rxmcommaalignen_in : IN std_logic;
399  gt9_rxpcommaalignen_in : IN std_logic;
400  gt9_rxdfelpmreset_in : IN std_logic;
401  gt9_rxmonitorsel_in : IN std_logic_vector(1 downto 0);
402  gt9_gtrxreset_in : IN std_logic;
403  gt9_rxpmareset_in : IN std_logic;
404  gt9_gttxreset_in : IN std_logic;
405  gt9_txuserrdy_in : IN std_logic;
406  gt9_txusrclk_in : IN std_logic;
407  gt9_txusrclk2_in : IN std_logic;
408  gt9_txdiffctrl_in : IN std_logic_vector(3 downto 0);
409  gt9_txdata_in : IN std_logic_vector(15 downto 0);
410  gt9_txcharisk_in : IN std_logic_vector(1 downto 0);
411  gt9_txprbssel_in : IN std_logic_vector(2 downto 0);
412  gt10_drpaddr_in : IN std_logic_vector(8 downto 0);
413  gt10_drpclk_in : IN std_logic;
414  gt10_drpdi_in : IN std_logic_vector(15 downto 0);
415  gt10_drpen_in : IN std_logic;
416  gt10_drpwe_in : IN std_logic;
417  gt10_loopback_in : IN std_logic_vector(2 downto 0);
418  gt10_rxpd_in : IN std_logic_vector(1 downto 0);
419  gt10_txpd_in : IN std_logic_vector(1 downto 0);
420  gt10_eyescanreset_in : IN std_logic;
421  gt10_rxuserrdy_in : IN std_logic;
422  gt10_eyescantrigger_in : IN std_logic;
423  gt10_rxusrclk_in : IN std_logic;
424  gt10_rxusrclk2_in : IN std_logic;
425  gt10_rxprbssel_in : IN std_logic_vector(2 downto 0);
426  gt10_rxprbscntreset_in : IN std_logic;
427  gt10_gtxrxp_in : IN std_logic;
428  gt10_gtxrxn_in : IN std_logic;
429  gt10_rxmcommaalignen_in : IN std_logic;
430  gt10_rxpcommaalignen_in : IN std_logic;
431  gt10_rxdfelpmreset_in : IN std_logic;
432  gt10_rxmonitorsel_in : IN std_logic_vector(1 downto 0);
433  gt10_gtrxreset_in : IN std_logic;
434  gt10_rxpmareset_in : IN std_logic;
435  gt10_gttxreset_in : IN std_logic;
436  gt10_txuserrdy_in : IN std_logic;
437  gt10_txusrclk_in : IN std_logic;
438  gt10_txusrclk2_in : IN std_logic;
439  gt10_txdiffctrl_in : IN std_logic_vector(3 downto 0);
440  gt10_txdata_in : IN std_logic_vector(15 downto 0);
441  gt10_txcharisk_in : IN std_logic_vector(1 downto 0);
442  gt10_txprbssel_in : IN std_logic_vector(2 downto 0);
443  gt11_drpaddr_in : IN std_logic_vector(8 downto 0);
444  gt11_drpclk_in : IN std_logic;
445  gt11_drpdi_in : IN std_logic_vector(15 downto 0);
446  gt11_drpen_in : IN std_logic;
447  gt11_drpwe_in : IN std_logic;
448  gt11_loopback_in : IN std_logic_vector(2 downto 0);
449  gt11_rxpd_in : IN std_logic_vector(1 downto 0);
450  gt11_txpd_in : IN std_logic_vector(1 downto 0);
451  gt11_eyescanreset_in : IN std_logic;
452  gt11_rxuserrdy_in : IN std_logic;
453  gt11_eyescantrigger_in : IN std_logic;
454  gt11_rxusrclk_in : IN std_logic;
455  gt11_rxusrclk2_in : IN std_logic;
456  gt11_rxprbssel_in : IN std_logic_vector(2 downto 0);
457  gt11_rxprbscntreset_in : IN std_logic;
458  gt11_gtxrxp_in : IN std_logic;
459  gt11_gtxrxn_in : IN std_logic;
460  gt11_rxmcommaalignen_in : IN std_logic;
461  gt11_rxpcommaalignen_in : IN std_logic;
462  gt11_rxdfelpmreset_in : IN std_logic;
463  gt11_rxmonitorsel_in : IN std_logic_vector(1 downto 0);
464  gt11_gtrxreset_in : IN std_logic;
465  gt11_rxpmareset_in : IN std_logic;
466  gt11_gttxreset_in : IN std_logic;
467  gt11_txuserrdy_in : IN std_logic;
468  gt11_txusrclk_in : IN std_logic;
469  gt11_txusrclk2_in : IN std_logic;
470  gt11_txdiffctrl_in : IN std_logic_vector(3 downto 0);
471  gt11_txdata_in : IN std_logic_vector(15 downto 0);
472  gt11_txcharisk_in : IN std_logic_vector(1 downto 0);
473  gt11_txprbssel_in : IN std_logic_vector(2 downto 0);
474  GT0_QPLLLOCK_IN : IN std_logic;
475  GT0_QPLLREFCLKLOST_IN : IN std_logic;
476  GT0_QPLLOUTCLK_IN : IN std_logic;
477  GT0_QPLLOUTREFCLK_IN : IN std_logic;
478  GT1_QPLLLOCK_IN : IN std_logic;
479  GT1_QPLLREFCLKLOST_IN : IN std_logic;
480  GT1_QPLLOUTCLK_IN : IN std_logic;
481  GT1_QPLLOUTREFCLK_IN : IN std_logic;
482  GT2_QPLLLOCK_IN : IN std_logic;
483  GT2_QPLLREFCLKLOST_IN : IN std_logic;
484  GT2_QPLLOUTCLK_IN : IN std_logic;
485  GT2_QPLLOUTREFCLK_IN : IN std_logic;
486  GT0_TX_FSM_RESET_DONE_OUT : OUT std_logic;
487  GT0_RX_FSM_RESET_DONE_OUT : OUT std_logic;
488  GT1_TX_FSM_RESET_DONE_OUT : OUT std_logic;
489  GT1_RX_FSM_RESET_DONE_OUT : OUT std_logic;
490  GT2_TX_FSM_RESET_DONE_OUT : OUT std_logic;
491  GT2_RX_FSM_RESET_DONE_OUT : OUT std_logic;
492  GT3_TX_FSM_RESET_DONE_OUT : OUT std_logic;
493  GT3_RX_FSM_RESET_DONE_OUT : OUT std_logic;
494  GT4_TX_FSM_RESET_DONE_OUT : OUT std_logic;
495  GT4_RX_FSM_RESET_DONE_OUT : OUT std_logic;
496  GT5_TX_FSM_RESET_DONE_OUT : OUT std_logic;
497  GT5_RX_FSM_RESET_DONE_OUT : OUT std_logic;
498  GT6_TX_FSM_RESET_DONE_OUT : OUT std_logic;
499  GT6_RX_FSM_RESET_DONE_OUT : OUT std_logic;
500  GT7_TX_FSM_RESET_DONE_OUT : OUT std_logic;
501  GT7_RX_FSM_RESET_DONE_OUT : OUT std_logic;
502  GT8_TX_FSM_RESET_DONE_OUT : OUT std_logic;
503  GT8_RX_FSM_RESET_DONE_OUT : OUT std_logic;
504  GT9_TX_FSM_RESET_DONE_OUT : OUT std_logic;
505  GT9_RX_FSM_RESET_DONE_OUT : OUT std_logic;
506  GT10_TX_FSM_RESET_DONE_OUT : OUT std_logic;
507  GT10_RX_FSM_RESET_DONE_OUT : OUT std_logic;
508  GT11_TX_FSM_RESET_DONE_OUT : OUT std_logic;
509  GT11_RX_FSM_RESET_DONE_OUT : OUT std_logic;
510  gt0_drpdo_out : OUT std_logic_vector(15 downto 0);
511  gt0_drprdy_out : OUT std_logic;
512  gt0_dmonitorout_out : OUT std_logic_vector(7 downto 0);
513  gt0_eyescandataerror_out : OUT std_logic;
514  gt0_rxclkcorcnt_out : OUT std_logic_vector(1 downto 0);
515  gt0_rxdata_out : OUT std_logic_vector(15 downto 0);
516  gt0_rxprbserr_out : OUT std_logic;
517  gt0_rxdisperr_out : OUT std_logic_vector(1 downto 0);
518  gt0_rxnotintable_out : OUT std_logic_vector(1 downto 0);
519  gt0_rxbufstatus_out : OUT std_logic_vector(2 downto 0);
520  gt0_rxmonitorout_out : OUT std_logic_vector(6 downto 0);
521  gt0_rxoutclk_out : OUT std_logic;
522  gt0_rxchariscomma_out : OUT std_logic_vector(1 downto 0);
523  gt0_rxcharisk_out : OUT std_logic_vector(1 downto 0);
524  gt0_rxresetdone_out : OUT std_logic;
525  gt0_gtxtxn_out : OUT std_logic;
526  gt0_gtxtxp_out : OUT std_logic;
527  gt0_txoutclk_out : OUT std_logic;
528  gt0_txoutclkfabric_out : OUT std_logic;
529  gt0_txoutclkpcs_out : OUT std_logic;
530  gt0_txresetdone_out : OUT std_logic;
531  gt1_drpdo_out : OUT std_logic_vector(15 downto 0);
532  gt1_drprdy_out : OUT std_logic;
533  gt1_dmonitorout_out : OUT std_logic_vector(7 downto 0);
534  gt1_eyescandataerror_out : OUT std_logic;
535  gt1_rxclkcorcnt_out : OUT std_logic_vector(1 downto 0);
536  gt1_rxdata_out : OUT std_logic_vector(15 downto 0);
537  gt1_rxprbserr_out : OUT std_logic;
538  gt1_rxdisperr_out : OUT std_logic_vector(1 downto 0);
539  gt1_rxnotintable_out : OUT std_logic_vector(1 downto 0);
540  gt1_rxbufstatus_out : OUT std_logic_vector(2 downto 0);
541  gt1_rxmonitorout_out : OUT std_logic_vector(6 downto 0);
542  gt1_rxoutclk_out : OUT std_logic;
543  gt1_rxchariscomma_out : OUT std_logic_vector(1 downto 0);
544  gt1_rxcharisk_out : OUT std_logic_vector(1 downto 0);
545  gt1_rxresetdone_out : OUT std_logic;
546  gt1_gtxtxn_out : OUT std_logic;
547  gt1_gtxtxp_out : OUT std_logic;
548  gt1_txoutclk_out : OUT std_logic;
549  gt1_txoutclkfabric_out : OUT std_logic;
550  gt1_txoutclkpcs_out : OUT std_logic;
551  gt1_txresetdone_out : OUT std_logic;
552  gt2_drpdo_out : OUT std_logic_vector(15 downto 0);
553  gt2_drprdy_out : OUT std_logic;
554  gt2_dmonitorout_out : OUT std_logic_vector(7 downto 0);
555  gt2_eyescandataerror_out : OUT std_logic;
556  gt2_rxclkcorcnt_out : OUT std_logic_vector(1 downto 0);
557  gt2_rxdata_out : OUT std_logic_vector(15 downto 0);
558  gt2_rxprbserr_out : OUT std_logic;
559  gt2_rxdisperr_out : OUT std_logic_vector(1 downto 0);
560  gt2_rxnotintable_out : OUT std_logic_vector(1 downto 0);
561  gt2_rxbufstatus_out : OUT std_logic_vector(2 downto 0);
562  gt2_rxmonitorout_out : OUT std_logic_vector(6 downto 0);
563  gt2_rxoutclk_out : OUT std_logic;
564  gt2_rxchariscomma_out : OUT std_logic_vector(1 downto 0);
565  gt2_rxcharisk_out : OUT std_logic_vector(1 downto 0);
566  gt2_rxresetdone_out : OUT std_logic;
567  gt2_gtxtxn_out : OUT std_logic;
568  gt2_gtxtxp_out : OUT std_logic;
569  gt2_txoutclk_out : OUT std_logic;
570  gt2_txoutclkfabric_out : OUT std_logic;
571  gt2_txoutclkpcs_out : OUT std_logic;
572  gt2_txresetdone_out : OUT std_logic;
573  gt3_drpdo_out : OUT std_logic_vector(15 downto 0);
574  gt3_drprdy_out : OUT std_logic;
575  gt3_dmonitorout_out : OUT std_logic_vector(7 downto 0);
576  gt3_eyescandataerror_out : OUT std_logic;
577  gt3_rxclkcorcnt_out : OUT std_logic_vector(1 downto 0);
578  gt3_rxdata_out : OUT std_logic_vector(15 downto 0);
579  gt3_rxprbserr_out : OUT std_logic;
580  gt3_rxdisperr_out : OUT std_logic_vector(1 downto 0);
581  gt3_rxnotintable_out : OUT std_logic_vector(1 downto 0);
582  gt3_rxbufstatus_out : OUT std_logic_vector(2 downto 0);
583  gt3_rxmonitorout_out : OUT std_logic_vector(6 downto 0);
584  gt3_rxoutclk_out : OUT std_logic;
585  gt3_rxchariscomma_out : OUT std_logic_vector(1 downto 0);
586  gt3_rxcharisk_out : OUT std_logic_vector(1 downto 0);
587  gt3_rxresetdone_out : OUT std_logic;
588  gt3_gtxtxn_out : OUT std_logic;
589  gt3_gtxtxp_out : OUT std_logic;
590  gt3_txoutclk_out : OUT std_logic;
591  gt3_txoutclkfabric_out : OUT std_logic;
592  gt3_txoutclkpcs_out : OUT std_logic;
593  gt3_txresetdone_out : OUT std_logic;
594  gt4_drpdo_out : OUT std_logic_vector(15 downto 0);
595  gt4_drprdy_out : OUT std_logic;
596  gt4_dmonitorout_out : OUT std_logic_vector(7 downto 0);
597  gt4_eyescandataerror_out : OUT std_logic;
598  gt4_rxclkcorcnt_out : OUT std_logic_vector(1 downto 0);
599  gt4_rxdata_out : OUT std_logic_vector(15 downto 0);
600  gt4_rxprbserr_out : OUT std_logic;
601  gt4_rxdisperr_out : OUT std_logic_vector(1 downto 0);
602  gt4_rxnotintable_out : OUT std_logic_vector(1 downto 0);
603  gt4_rxbufstatus_out : OUT std_logic_vector(2 downto 0);
604  gt4_rxmonitorout_out : OUT std_logic_vector(6 downto 0);
605  gt4_rxoutclk_out : OUT std_logic;
606  gt4_rxchariscomma_out : OUT std_logic_vector(1 downto 0);
607  gt4_rxcharisk_out : OUT std_logic_vector(1 downto 0);
608  gt4_rxresetdone_out : OUT std_logic;
609  gt4_gtxtxn_out : OUT std_logic;
610  gt4_gtxtxp_out : OUT std_logic;
611  gt4_txoutclk_out : OUT std_logic;
612  gt4_txoutclkfabric_out : OUT std_logic;
613  gt4_txoutclkpcs_out : OUT std_logic;
614  gt4_txresetdone_out : OUT std_logic;
615  gt5_drpdo_out : OUT std_logic_vector(15 downto 0);
616  gt5_drprdy_out : OUT std_logic;
617  gt5_dmonitorout_out : OUT std_logic_vector(7 downto 0);
618  gt5_eyescandataerror_out : OUT std_logic;
619  gt5_rxclkcorcnt_out : OUT std_logic_vector(1 downto 0);
620  gt5_rxdata_out : OUT std_logic_vector(15 downto 0);
621  gt5_rxprbserr_out : OUT std_logic;
622  gt5_rxdisperr_out : OUT std_logic_vector(1 downto 0);
623  gt5_rxnotintable_out : OUT std_logic_vector(1 downto 0);
624  gt5_rxbufstatus_out : OUT std_logic_vector(2 downto 0);
625  gt5_rxmonitorout_out : OUT std_logic_vector(6 downto 0);
626  gt5_rxoutclk_out : OUT std_logic;
627  gt5_rxchariscomma_out : OUT std_logic_vector(1 downto 0);
628  gt5_rxcharisk_out : OUT std_logic_vector(1 downto 0);
629  gt5_rxresetdone_out : OUT std_logic;
630  gt5_gtxtxn_out : OUT std_logic;
631  gt5_gtxtxp_out : OUT std_logic;
632  gt5_txoutclk_out : OUT std_logic;
633  gt5_txoutclkfabric_out : OUT std_logic;
634  gt5_txoutclkpcs_out : OUT std_logic;
635  gt5_txresetdone_out : OUT std_logic;
636  gt6_drpdo_out : OUT std_logic_vector(15 downto 0);
637  gt6_drprdy_out : OUT std_logic;
638  gt6_dmonitorout_out : OUT std_logic_vector(7 downto 0);
639  gt6_eyescandataerror_out : OUT std_logic;
640  gt6_rxclkcorcnt_out : OUT std_logic_vector(1 downto 0);
641  gt6_rxdata_out : OUT std_logic_vector(15 downto 0);
642  gt6_rxprbserr_out : OUT std_logic;
643  gt6_rxdisperr_out : OUT std_logic_vector(1 downto 0);
644  gt6_rxnotintable_out : OUT std_logic_vector(1 downto 0);
645  gt6_rxbufstatus_out : OUT std_logic_vector(2 downto 0);
646  gt6_rxmonitorout_out : OUT std_logic_vector(6 downto 0);
647  gt6_rxoutclk_out : OUT std_logic;
648  gt6_rxchariscomma_out : OUT std_logic_vector(1 downto 0);
649  gt6_rxcharisk_out : OUT std_logic_vector(1 downto 0);
650  gt6_rxresetdone_out : OUT std_logic;
651  gt6_gtxtxn_out : OUT std_logic;
652  gt6_gtxtxp_out : OUT std_logic;
653  gt6_txoutclk_out : OUT std_logic;
654  gt6_txoutclkfabric_out : OUT std_logic;
655  gt6_txoutclkpcs_out : OUT std_logic;
656  gt6_txresetdone_out : OUT std_logic;
657  gt7_drpdo_out : OUT std_logic_vector(15 downto 0);
658  gt7_drprdy_out : OUT std_logic;
659  gt7_dmonitorout_out : OUT std_logic_vector(7 downto 0);
660  gt7_eyescandataerror_out : OUT std_logic;
661  gt7_rxclkcorcnt_out : OUT std_logic_vector(1 downto 0);
662  gt7_rxdata_out : OUT std_logic_vector(15 downto 0);
663  gt7_rxprbserr_out : OUT std_logic;
664  gt7_rxdisperr_out : OUT std_logic_vector(1 downto 0);
665  gt7_rxnotintable_out : OUT std_logic_vector(1 downto 0);
666  gt7_rxbufstatus_out : OUT std_logic_vector(2 downto 0);
667  gt7_rxmonitorout_out : OUT std_logic_vector(6 downto 0);
668  gt7_rxoutclk_out : OUT std_logic;
669  gt7_rxchariscomma_out : OUT std_logic_vector(1 downto 0);
670  gt7_rxcharisk_out : OUT std_logic_vector(1 downto 0);
671  gt7_rxresetdone_out : OUT std_logic;
672  gt7_gtxtxn_out : OUT std_logic;
673  gt7_gtxtxp_out : OUT std_logic;
674  gt7_txoutclk_out : OUT std_logic;
675  gt7_txoutclkfabric_out : OUT std_logic;
676  gt7_txoutclkpcs_out : OUT std_logic;
677  gt7_txresetdone_out : OUT std_logic;
678  gt8_drpdo_out : OUT std_logic_vector(15 downto 0);
679  gt8_drprdy_out : OUT std_logic;
680  gt8_dmonitorout_out : OUT std_logic_vector(7 downto 0);
681  gt8_eyescandataerror_out : OUT std_logic;
682  gt8_rxclkcorcnt_out : OUT std_logic_vector(1 downto 0);
683  gt8_rxdata_out : OUT std_logic_vector(15 downto 0);
684  gt8_rxprbserr_out : OUT std_logic;
685  gt8_rxdisperr_out : OUT std_logic_vector(1 downto 0);
686  gt8_rxnotintable_out : OUT std_logic_vector(1 downto 0);
687  gt8_rxbufstatus_out : OUT std_logic_vector(2 downto 0);
688  gt8_rxmonitorout_out : OUT std_logic_vector(6 downto 0);
689  gt8_rxoutclk_out : OUT std_logic;
690  gt8_rxchariscomma_out : OUT std_logic_vector(1 downto 0);
691  gt8_rxcharisk_out : OUT std_logic_vector(1 downto 0);
692  gt8_rxresetdone_out : OUT std_logic;
693  gt8_gtxtxn_out : OUT std_logic;
694  gt8_gtxtxp_out : OUT std_logic;
695  gt8_txoutclk_out : OUT std_logic;
696  gt8_txoutclkfabric_out : OUT std_logic;
697  gt8_txoutclkpcs_out : OUT std_logic;
698  gt8_txresetdone_out : OUT std_logic;
699  gt9_drpdo_out : OUT std_logic_vector(15 downto 0);
700  gt9_drprdy_out : OUT std_logic;
701  gt9_dmonitorout_out : OUT std_logic_vector(7 downto 0);
702  gt9_eyescandataerror_out : OUT std_logic;
703  gt9_rxclkcorcnt_out : OUT std_logic_vector(1 downto 0);
704  gt9_rxdata_out : OUT std_logic_vector(15 downto 0);
705  gt9_rxprbserr_out : OUT std_logic;
706  gt9_rxdisperr_out : OUT std_logic_vector(1 downto 0);
707  gt9_rxnotintable_out : OUT std_logic_vector(1 downto 0);
708  gt9_rxbufstatus_out : OUT std_logic_vector(2 downto 0);
709  gt9_rxmonitorout_out : OUT std_logic_vector(6 downto 0);
710  gt9_rxoutclk_out : OUT std_logic;
711  gt9_rxchariscomma_out : OUT std_logic_vector(1 downto 0);
712  gt9_rxcharisk_out : OUT std_logic_vector(1 downto 0);
713  gt9_rxresetdone_out : OUT std_logic;
714  gt9_gtxtxn_out : OUT std_logic;
715  gt9_gtxtxp_out : OUT std_logic;
716  gt9_txoutclk_out : OUT std_logic;
717  gt9_txoutclkfabric_out : OUT std_logic;
718  gt9_txoutclkpcs_out : OUT std_logic;
719  gt9_txresetdone_out : OUT std_logic;
720  gt10_drpdo_out : OUT std_logic_vector(15 downto 0);
721  gt10_drprdy_out : OUT std_logic;
722  gt10_dmonitorout_out : OUT std_logic_vector(7 downto 0);
723  gt10_eyescandataerror_out : OUT std_logic;
724  gt10_rxclkcorcnt_out : OUT std_logic_vector(1 downto 0);
725  gt10_rxdata_out : OUT std_logic_vector(15 downto 0);
726  gt10_rxprbserr_out : OUT std_logic;
727  gt10_rxdisperr_out : OUT std_logic_vector(1 downto 0);
728  gt10_rxnotintable_out : OUT std_logic_vector(1 downto 0);
729  gt10_rxbufstatus_out : OUT std_logic_vector(2 downto 0);
730  gt10_rxmonitorout_out : OUT std_logic_vector(6 downto 0);
731  gt10_rxoutclk_out : OUT std_logic;
732  gt10_rxchariscomma_out : OUT std_logic_vector(1 downto 0);
733  gt10_rxcharisk_out : OUT std_logic_vector(1 downto 0);
734  gt10_rxresetdone_out : OUT std_logic;
735  gt10_gtxtxn_out : OUT std_logic;
736  gt10_gtxtxp_out : OUT std_logic;
737  gt10_txoutclk_out : OUT std_logic;
738  gt10_txoutclkfabric_out : OUT std_logic;
739  gt10_txoutclkpcs_out : OUT std_logic;
740  gt10_txresetdone_out : OUT std_logic;
741  gt11_drpdo_out : OUT std_logic_vector(15 downto 0);
742  gt11_drprdy_out : OUT std_logic;
743  gt11_dmonitorout_out : OUT std_logic_vector(7 downto 0);
744  gt11_eyescandataerror_out : OUT std_logic;
745  gt11_rxclkcorcnt_out : OUT std_logic_vector(1 downto 0);
746  gt11_rxdata_out : OUT std_logic_vector(15 downto 0);
747  gt11_rxprbserr_out : OUT std_logic;
748  gt11_rxdisperr_out : OUT std_logic_vector(1 downto 0);
749  gt11_rxnotintable_out : OUT std_logic_vector(1 downto 0);
750  gt11_rxbufstatus_out : OUT std_logic_vector(2 downto 0);
751  gt11_rxmonitorout_out : OUT std_logic_vector(6 downto 0);
752  gt11_rxoutclk_out : OUT std_logic;
753  gt11_rxchariscomma_out : OUT std_logic_vector(1 downto 0);
754  gt11_rxcharisk_out : OUT std_logic_vector(1 downto 0);
755  gt11_rxresetdone_out : OUT std_logic;
756  gt11_gtxtxn_out : OUT std_logic;
757  gt11_gtxtxp_out : OUT std_logic;
758  gt11_txoutclk_out : OUT std_logic;
759  gt11_txoutclkfabric_out : OUT std_logic;
760  gt11_txoutclkpcs_out : OUT std_logic;
761  gt11_txresetdone_out : OUT std_logic;
762  GT0_QPLLRESET_OUT : OUT std_logic;
763  GT1_QPLLRESET_OUT : OUT std_logic;
764  GT2_QPLLRESET_OUT : OUT std_logic
765  );
766 end component;
767 component amc_gtx5Gpd_common_reset
768 generic
769 (
770  STABLE_CLOCK_PERIOD : integer := 8 -- Period of the stable clock driving this state-machine, unit is [ns]
771  );
772 port
773  (
774  STABLE_CLOCK : in std_logic; --Stable Clock, either a stable clock from the PCB
775  SOFT_RESET : in std_logic; --User Reset, can be pulled any time
776  COMMON_RESET : out std_logic --Reset QPLL
777  );
778 end component;
779 
780 component amc_gtx5Gpd_common
781 generic
782 (
783  -- Simulation attributes
784  WRAPPER_SIM_GTRESET_SPEEDUP : string := "TRUE" -- Set to "TRUE" to speed up sim reset
785 );
786 port
787 (
788  GTREFCLK0_IN : in std_logic;
789  QPLLLOCK_OUT : out std_logic;
790  QPLLLOCKDETCLK_IN : in std_logic;
791  QPLLOUTCLK_OUT : out std_logic;
792  QPLLOUTREFCLK_OUT : out std_logic;
793  QPLLREFCLKLOST_OUT : out std_logic;
794  QPLLRESET_IN : in std_logic
795 
796 );
797 
798 end component;
799 signal qpll_lock_i : std_logic_vector(2 downto 0) := (others =>'0');
800 signal qpll_lock_n : std_logic_vector(2 downto 0) := (others =>'0');
801 signal COMMON_RESET : std_logic := '0';
802 signal GT0_QPLLRESET_OUT : std_logic := '0';
803 signal GT1_QPLLRESET_OUT : std_logic := '0';
804 signal GT2_QPLLRESET_OUT : std_logic := '0';
805 signal GT0_QPLLRESET_IN : std_logic := '0';
806 signal GT1_QPLLRESET_IN : std_logic := '0';
807 signal GT2_QPLLRESET_IN : std_logic := '0';
808 signal GT0_QPLLOUTCLK : std_logic := '0';
809 signal GT1_QPLLOUTCLK : std_logic := '0';
810 signal GT2_QPLLOUTCLK : std_logic := '0';
811 signal GT0_QPLLOUTREFCLK : std_logic := '0';
812 signal GT1_QPLLOUTREFCLK : std_logic := '0';
813 signal GT2_QPLLOUTREFCLK : std_logic := '0';
814 signal GT0_QPLLREFCLKLOST : std_logic := '0';
815 signal GT1_QPLLREFCLKLOST : std_logic := '0';
816 signal GT2_QPLLREFCLKLOST : std_logic := '0';
817 signal loopback : array12x3 := (others => (others => '0'));
818 signal AMC_pd : array12x2 := (others => (others => '0'));
819 signal gt0_rxbufstatus : std_logic_vector(2 downto 0) := (others =>'0');
820 signal gt1_rxbufstatus : std_logic_vector(2 downto 0) := (others =>'0');
821 signal gt2_rxbufstatus : std_logic_vector(2 downto 0) := (others =>'0');
822 signal gt3_rxbufstatus : std_logic_vector(2 downto 0) := (others =>'0');
823 signal gt4_rxbufstatus : std_logic_vector(2 downto 0) := (others =>'0');
824 signal gt5_rxbufstatus : std_logic_vector(2 downto 0) := (others =>'0');
825 signal gt6_rxbufstatus : std_logic_vector(2 downto 0) := (others =>'0');
826 signal gt7_rxbufstatus : std_logic_vector(2 downto 0) := (others =>'0');
827 signal gt8_rxbufstatus : std_logic_vector(2 downto 0) := (others =>'0');
828 signal gt9_rxbufstatus : std_logic_vector(2 downto 0) := (others =>'0');
829 signal gt10_rxbufstatus : std_logic_vector(2 downto 0) := (others =>'0');
830 signal gt11_rxbufstatus : std_logic_vector(2 downto 0) := (others =>'0');
831 signal gt0_rxoutclk : std_logic := '0';
832 signal gt1_rxoutclk : std_logic := '0';
833 signal gt2_rxoutclk : std_logic := '0';
834 signal gt3_rxoutclk : std_logic := '0';
835 signal gt4_rxoutclk : std_logic := '0';
836 signal gt5_rxoutclk : std_logic := '0';
837 signal gt6_rxoutclk : std_logic := '0';
838 signal gt7_rxoutclk : std_logic := '0';
839 signal gt8_rxoutclk : std_logic := '0';
840 signal gt9_rxoutclk : std_logic := '0';
841 signal gt10_rxoutclk : std_logic := '0';
842 signal gt11_rxoutclk : std_logic := '0';
843 signal gt0_rxoutclk_buf : std_logic := '0';
844 signal gt1_rxoutclk_buf : std_logic := '0';
845 signal gt2_rxoutclk_buf : std_logic := '0';
846 signal gt3_rxoutclk_buf : std_logic := '0';
847 signal gt4_rxoutclk_buf : std_logic := '0';
848 signal gt5_rxoutclk_buf : std_logic := '0';
849 signal gt6_rxoutclk_buf : std_logic := '0';
850 signal gt7_rxoutclk_buf : std_logic := '0';
851 signal gt8_rxoutclk_buf : std_logic := '0';
852 signal gt9_rxoutclk_buf : std_logic := '0';
853 signal gt10_rxoutclk_buf : std_logic := '0';
854 signal gt11_rxoutclk_buf : std_logic := '0';
855 signal RxCntr : array12x21 := (others => (others => '0'));
856 signal sampleRatioSync : array12x4 := (others => (others => '0'));
857 signal RXDATA_i : array12x16 := (others => (others => '0'));
858 signal RXNOTINTABLE_i : array12x2 := (others => (others => '0'));
859 signal rxchariscomma_i : array12x2 := (others => (others => '0'));
860 signal rxcharisk_i : array12x2 := (others => (others => '0'));
861 signal rxresetdone_i : STD_LOGIC_VECTOR(11 downto 0) := (others => '0');
862 begin
863 qpll_lock <= qpll_lock_i;
864 process(test, AMC_en)
865 begin
866  for i in 0 to 11 loop
867  if(test = '1' or AMC_en(i) = '0')then
868  loopback(i) <= "001";
869  else
870  loopback(i) <= "000";
871  end if;
872  if(Dis_pd = '0' and (test = '1' or AMC_en(i) = '0'))then
873  AMC_pd(i) <= "11";
874  else
875  AMC_pd(i) <= "00";
876  end if;
877  end loop;
878 end process;
879 process(UsrClk)
880 begin
881  if(UsrClk'event and UsrClk = '1')then
882  if(test = '1')then
883  RXDATA <= (others => x"bcbc");
884  RXNOTINTABLE <= (others => "00");
885  rxchariscomma <= (others => "11");
886  rxcharisk <= (others => "11");
887  rxresetdone <= (others => '1');
888  else
889  RXDATA <= RXDATA_i;
890  RXNOTINTABLE <= RXNOTINTABLE_i;
891  rxchariscomma <= rxchariscomma_i;
892  rxcharisk <= rxcharisk_i;
893  rxresetdone <= rxresetdone_i;
894  end if;
895  if(gt0_rxbufstatus = "110")then
896  RxBufOvf(0) <= '1';
897  else
898  RxBufOvf(0) <= '0';
899  end if;
900  if(gt0_rxbufstatus = "101")then
901  RxBufUdf(0) <= '1';
902  else
903  RxBufUdf(0) <= '0';
904  end if;
905  if(gt1_rxbufstatus = "110")then
906  RxBufOvf(1) <= '1';
907  else
908  RxBufOvf(1) <= '0';
909  end if;
910  if(gt1_rxbufstatus = "101")then
911  RxBufUdf(1) <= '1';
912  else
913  RxBufUdf(1) <= '0';
914  end if;
915  if(gt2_rxbufstatus = "110")then
916  RxBufOvf(2) <= '1';
917  else
918  RxBufOvf(2) <= '0';
919  end if;
920  if(gt2_rxbufstatus = "101")then
921  RxBufUdf(2) <= '1';
922  else
923  RxBufUdf(2) <= '0';
924  end if;
925  if(gt3_rxbufstatus = "110")then
926  RxBufOvf(3) <= '1';
927  else
928  RxBufOvf(3) <= '0';
929  end if;
930  if(gt3_rxbufstatus = "101")then
931  RxBufUdf(3) <= '1';
932  else
933  RxBufUdf(3) <= '0';
934  end if;
935  if(gt4_rxbufstatus = "110")then
936  RxBufOvf(4) <= '1';
937  else
938  RxBufOvf(4) <= '0';
939  end if;
940  if(gt4_rxbufstatus = "101")then
941  RxBufUdf(4) <= '1';
942  else
943  RxBufUdf(4) <= '0';
944  end if;
945  if(gt5_rxbufstatus = "110")then
946  RxBufOvf(5) <= '1';
947  else
948  RxBufOvf(5) <= '0';
949  end if;
950  if(gt5_rxbufstatus = "101")then
951  RxBufUdf(5) <= '1';
952  else
953  RxBufUdf(5) <= '0';
954  end if;
955  if(gt6_rxbufstatus = "110")then
956  RxBufOvf(6) <= '1';
957  else
958  RxBufOvf(6) <= '0';
959  end if;
960  if(gt6_rxbufstatus = "101")then
961  RxBufUdf(6) <= '1';
962  else
963  RxBufUdf(6) <= '0';
964  end if;
965  if(gt7_rxbufstatus = "110")then
966  RxBufOvf(7) <= '1';
967  else
968  RxBufOvf(7) <= '0';
969  end if;
970  if(gt7_rxbufstatus = "101")then
971  RxBufUdf(7) <= '1';
972  else
973  RxBufUdf(7) <= '0';
974  end if;
975  if(gt8_rxbufstatus = "110")then
976  RxBufOvf(8) <= '1';
977  else
978  RxBufOvf(8) <= '0';
979  end if;
980  if(gt8_rxbufstatus = "101")then
981  RxBufUdf(8) <= '1';
982  else
983  RxBufUdf(8) <= '0';
984  end if;
985  if(gt9_rxbufstatus = "110")then
986  RxBufOvf(9) <= '1';
987  else
988  RxBufOvf(9) <= '0';
989  end if;
990  if(gt9_rxbufstatus = "101")then
991  RxBufUdf(9) <= '1';
992  else
993  RxBufUdf(9) <= '0';
994  end if;
995  if(gt10_rxbufstatus = "110")then
996  RxBufOvf(10) <= '1';
997  else
998  RxBufOvf(10) <= '0';
999  end if;
1000  if(gt10_rxbufstatus = "101")then
1001  RxBufUdf(10) <= '1';
1002  else
1003  RxBufUdf(10) <= '0';
1004  end if;
1005  if(gt11_rxbufstatus = "110")then
1006  RxBufOvf(11) <= '1';
1007  else
1008  RxBufOvf(11) <= '0';
1009  end if;
1010  if(gt11_rxbufstatus = "101")then
1011  RxBufUdf(11) <= '1';
1012  else
1013  RxBufUdf(11) <= '0';
1014  end if;
1015  end if;
1016 end process;
1017 process(gt0_rxoutclk_buf)
1018 begin
1019  if(gt0_rxoutclk_buf'event and gt0_rxoutclk_buf = '1')then
1020  sampleRatioSync(0) <= sampleRatioSync(0)(2 downto 0) & sampleRatio;
1021  if(sampleRatioSync(0)(3 downto 2) = "10")then
1022  RxCntr(0) <= (others => '0');
1023  if(updateRatio = '1')then
1024  RxClkRatio(0) <= RxCntr(0);
1025  end if;
1026  else
1027  RxCntr(0) <= RxCntr(0) + 1;
1028  end if;
1029  end if;
1030 end process;
1031 process(gt1_rxoutclk_buf)
1032 begin
1033  if(gt1_rxoutclk_buf'event and gt1_rxoutclk_buf = '1')then
1034  sampleRatioSync(1) <= sampleRatioSync(1)(2 downto 0) & sampleRatio;
1035  if(sampleRatioSync(1)(3 downto 2) = "10")then
1036  RxCntr(1) <= (others => '0');
1037  if(updateRatio = '1')then
1038  RxClkRatio(1) <= RxCntr(1);
1039  end if;
1040  else
1041  RxCntr(1) <= RxCntr(1) + 1;
1042  end if;
1043  end if;
1044 end process;
1045 process(gt2_rxoutclk_buf)
1046 begin
1047  if(gt2_rxoutclk_buf'event and gt2_rxoutclk_buf = '1')then
1048  sampleRatioSync(2) <= sampleRatioSync(2)(2 downto 0) & sampleRatio;
1049  if(sampleRatioSync(2)(3 downto 2) = "10")then
1050  RxCntr(2) <= (others => '0');
1051  if(updateRatio = '1')then
1052  RxClkRatio(2) <= RxCntr(2);
1053  end if;
1054  else
1055  RxCntr(2) <= RxCntr(2) + 1;
1056  end if;
1057  end if;
1058 end process;
1059 process(gt3_rxoutclk_buf)
1060 begin
1061  if(gt3_rxoutclk_buf'event and gt3_rxoutclk_buf = '1')then
1062  sampleRatioSync(3) <= sampleRatioSync(3)(2 downto 0) & sampleRatio;
1063  if(sampleRatioSync(3)(3 downto 2) = "10")then
1064  RxCntr(3) <= (others => '0');
1065  if(updateRatio = '1')then
1066  RxClkRatio(3) <= RxCntr(3);
1067  end if;
1068  else
1069  RxCntr(3) <= RxCntr(3) + 1;
1070  end if;
1071  end if;
1072 end process;
1073 process(gt4_rxoutclk_buf)
1074 begin
1075  if(gt4_rxoutclk_buf'event and gt4_rxoutclk_buf = '1')then
1076  sampleRatioSync(4) <= sampleRatioSync(4)(2 downto 0) & sampleRatio;
1077  if(sampleRatioSync(4)(3 downto 2) = "10")then
1078  RxCntr(4) <= (others => '0');
1079  if(updateRatio = '1')then
1080  RxClkRatio(4) <= RxCntr(4);
1081  end if;
1082  else
1083  RxCntr(4) <= RxCntr(4) + 1;
1084  end if;
1085  end if;
1086 end process;
1087 process(gt5_rxoutclk_buf)
1088 begin
1089  if(gt5_rxoutclk_buf'event and gt5_rxoutclk_buf = '1')then
1090  sampleRatioSync(5) <= sampleRatioSync(5)(2 downto 0) & sampleRatio;
1091  if(sampleRatioSync(5)(3 downto 2) = "10")then
1092  RxCntr(5) <= (others => '0');
1093  if(updateRatio = '1')then
1094  RxClkRatio(5) <= RxCntr(5);
1095  end if;
1096  else
1097  RxCntr(5) <= RxCntr(5) + 1;
1098  end if;
1099  end if;
1100 end process;
1101 process(gt6_rxoutclk_buf)
1102 begin
1103  if(gt6_rxoutclk_buf'event and gt6_rxoutclk_buf = '1')then
1104  sampleRatioSync(6) <= sampleRatioSync(6)(2 downto 0) & sampleRatio;
1105  if(sampleRatioSync(6)(3 downto 2) = "10")then
1106  RxCntr(6) <= (others => '0');
1107  if(updateRatio = '1')then
1108  RxClkRatio(6) <= RxCntr(6);
1109  end if;
1110  else
1111  RxCntr(6) <= RxCntr(6) + 1;
1112  end if;
1113  end if;
1114 end process;
1115 process(gt7_rxoutclk_buf)
1116 begin
1117  if(gt7_rxoutclk_buf'event and gt7_rxoutclk_buf = '1')then
1118  sampleRatioSync(7) <= sampleRatioSync(7)(2 downto 0) & sampleRatio;
1119  if(sampleRatioSync(7)(3 downto 2) = "10")then
1120  RxCntr(7) <= (others => '0');
1121  if(updateRatio = '1')then
1122  RxClkRatio(7) <= RxCntr(7);
1123  end if;
1124  else
1125  RxCntr(7) <= RxCntr(7) + 1;
1126  end if;
1127  end if;
1128 end process;
1129 process(gt8_rxoutclk_buf)
1130 begin
1131  if(gt8_rxoutclk_buf'event and gt8_rxoutclk_buf = '1')then
1132  sampleRatioSync(8) <= sampleRatioSync(8)(2 downto 0) & sampleRatio;
1133  if(sampleRatioSync(8)(3 downto 2) = "10")then
1134  RxCntr(8) <= (others => '0');
1135  if(updateRatio = '1')then
1136  RxClkRatio(8) <= RxCntr(8);
1137  end if;
1138  else
1139  RxCntr(8) <= RxCntr(8) + 1;
1140  end if;
1141  end if;
1142 end process;
1143 process(gt9_rxoutclk_buf)
1144 begin
1145  if(gt9_rxoutclk_buf'event and gt9_rxoutclk_buf = '1')then
1146  sampleRatioSync(9) <= sampleRatioSync(9)(2 downto 0) & sampleRatio;
1147  if(sampleRatioSync(9)(3 downto 2) = "10")then
1148  RxCntr(9) <= (others => '0');
1149  if(updateRatio = '1')then
1150  RxClkRatio(9) <= RxCntr(9);
1151  end if;
1152  else
1153  RxCntr(9) <= RxCntr(9) + 1;
1154  end if;
1155  end if;
1156 end process;
1157 process(gt10_rxoutclk_buf)
1158 begin
1159  if(gt10_rxoutclk_buf'event and gt10_rxoutclk_buf = '1')then
1160  sampleRatioSync(10) <= sampleRatioSync(10)(2 downto 0) & sampleRatio;
1161  if(sampleRatioSync(10)(3 downto 2) = "10")then
1162  RxCntr(10) <= (others => '0');
1163  if(updateRatio = '1')then
1164  RxClkRatio(10) <= RxCntr(10);
1165  end if;
1166  else
1167  RxCntr(10) <= RxCntr(10) + 1;
1168  end if;
1169  end if;
1170 end process;
1171 process(gt11_rxoutclk_buf)
1172 begin
1173  if(gt11_rxoutclk_buf'event and gt11_rxoutclk_buf = '1')then
1174  sampleRatioSync(11) <= sampleRatioSync(11)(2 downto 0) & sampleRatio;
1175  if(sampleRatioSync(11)(3 downto 2) = "10")then
1176  RxCntr(11) <= (others => '0');
1177  if(updateRatio = '1')then
1178  RxClkRatio(11) <= RxCntr(11);
1179  end if;
1180  else
1181  RxCntr(11) <= RxCntr(11) + 1;
1182  end if;
1183  end if;
1184 end process;
1185 --qpll_lock_n <= not qpll_lock_i;
1186 qpll_lock_n <= "000";
1187 i_gt0_rxoutclk_buf : BUFH port map (O => gt0_rxoutclk_buf, I => gt0_rxoutclk);
1188 i_gt1_rxoutclk_buf : BUFH port map (O => gt1_rxoutclk_buf, I => gt1_rxoutclk);
1189 i_gt2_rxoutclk_buf : BUFH port map (O => gt2_rxoutclk_buf, I => gt2_rxoutclk);
1190 i_gt3_rxoutclk_buf : BUFH port map (O => gt3_rxoutclk_buf, I => gt3_rxoutclk);
1191 i_gt4_rxoutclk_buf : BUFH port map (O => gt4_rxoutclk_buf, I => gt4_rxoutclk);
1192 i_gt5_rxoutclk_buf : BUFH port map (O => gt5_rxoutclk_buf, I => gt5_rxoutclk);
1193 i_gt6_rxoutclk_buf : BUFH port map (O => gt6_rxoutclk_buf, I => gt6_rxoutclk);
1194 i_gt7_rxoutclk_buf : BUFH port map (O => gt7_rxoutclk_buf, I => gt7_rxoutclk);
1195 i_gt8_rxoutclk_buf : BUFH port map (O => gt8_rxoutclk_buf, I => gt8_rxoutclk);
1196 i_gt9_rxoutclk_buf : BUFH port map (O => gt9_rxoutclk_buf, I => gt9_rxoutclk);
1197 i_gt10_rxoutclk_buf : BUFH port map (O => gt10_rxoutclk_buf, I => gt10_rxoutclk);
1198 i_gt11_rxoutclk_buf : BUFH port map (O => gt11_rxoutclk_buf, I => gt11_rxoutclk);
1199 i_AMC_GTX5Gpd_init : amc_gtx5Gpd_init
1200 port map
1201 (
1202  SYSCLK_IN => DRPclk,
1203  SOFT_RESET_IN => SOFT_RESET,
1204  DONT_RESET_ON_DATA_ERROR_IN => '0',
1205  GT0_TX_FSM_RESET_DONE_OUT => txfsmresetdone(0),
1206  GT0_RX_FSM_RESET_DONE_OUT => rxfsmresetdone(0),
1207  GT0_DATA_VALID_IN => data_valid(0),
1208  GT1_TX_FSM_RESET_DONE_OUT => txfsmresetdone(1),
1209  GT1_RX_FSM_RESET_DONE_OUT => rxfsmresetdone(1),
1210  GT1_DATA_VALID_IN => data_valid(1),
1211  GT2_TX_FSM_RESET_DONE_OUT => txfsmresetdone(2),
1212  GT2_RX_FSM_RESET_DONE_OUT => rxfsmresetdone(2),
1213  GT2_DATA_VALID_IN => data_valid(2),
1214  GT3_TX_FSM_RESET_DONE_OUT => txfsmresetdone(3),
1215  GT3_RX_FSM_RESET_DONE_OUT => rxfsmresetdone(3),
1216  GT3_DATA_VALID_IN => data_valid(3),
1217  GT4_TX_FSM_RESET_DONE_OUT => txfsmresetdone(4),
1218  GT4_RX_FSM_RESET_DONE_OUT => rxfsmresetdone(4),
1219  GT4_DATA_VALID_IN => data_valid(4),
1220  GT5_TX_FSM_RESET_DONE_OUT => txfsmresetdone(5),
1221  GT5_RX_FSM_RESET_DONE_OUT => rxfsmresetdone(5),
1222  GT5_DATA_VALID_IN => data_valid(5),
1223  GT6_TX_FSM_RESET_DONE_OUT => txfsmresetdone(6),
1224  GT6_RX_FSM_RESET_DONE_OUT => rxfsmresetdone(6),
1225  GT6_DATA_VALID_IN => data_valid(6),
1226  GT7_TX_FSM_RESET_DONE_OUT => txfsmresetdone(7),
1227  GT7_RX_FSM_RESET_DONE_OUT => rxfsmresetdone(7),
1228  GT7_DATA_VALID_IN => data_valid(7),
1229  GT8_TX_FSM_RESET_DONE_OUT => txfsmresetdone(8),
1230  GT8_RX_FSM_RESET_DONE_OUT => rxfsmresetdone(8),
1231  GT8_DATA_VALID_IN => data_valid(8),
1232  GT9_TX_FSM_RESET_DONE_OUT => txfsmresetdone(9),
1233  GT9_RX_FSM_RESET_DONE_OUT => rxfsmresetdone(9),
1234  GT9_DATA_VALID_IN => data_valid(9),
1235  GT10_TX_FSM_RESET_DONE_OUT => txfsmresetdone(10),
1236  GT10_RX_FSM_RESET_DONE_OUT => rxfsmresetdone(10),
1237  GT10_DATA_VALID_IN => data_valid(10),
1238  GT11_TX_FSM_RESET_DONE_OUT => txfsmresetdone(11),
1239  GT11_RX_FSM_RESET_DONE_OUT => rxfsmresetdone(11),
1240  GT11_DATA_VALID_IN => data_valid(11),
1241 
1242  gt0_rxoutclk_out => gt0_rxoutclk,
1243  gt0_rxbufstatus_out => gt0_rxbufstatus,
1244  gt1_rxoutclk_out => gt1_rxoutclk,
1245  gt1_rxbufstatus_out => gt1_rxbufstatus,
1246  gt2_rxoutclk_out => gt2_rxoutclk,
1247  gt2_rxbufstatus_out => gt2_rxbufstatus,
1248  gt3_rxoutclk_out => gt3_rxoutclk,
1249  gt3_rxbufstatus_out => gt3_rxbufstatus,
1250  gt4_rxoutclk_out => gt4_rxoutclk,
1251  gt4_rxbufstatus_out => gt4_rxbufstatus,
1252  gt5_rxoutclk_out => gt5_rxoutclk,
1253  gt5_rxbufstatus_out => gt5_rxbufstatus,
1254  gt6_rxoutclk_out => gt6_rxoutclk,
1255  gt6_rxbufstatus_out => gt6_rxbufstatus,
1256  gt7_rxoutclk_out => gt7_rxoutclk,
1257  gt7_rxbufstatus_out => gt7_rxbufstatus,
1258  gt8_rxoutclk_out => gt8_rxoutclk,
1259  gt8_rxbufstatus_out => gt8_rxbufstatus,
1260  gt9_rxoutclk_out => gt9_rxoutclk,
1261  gt9_rxbufstatus_out => gt9_rxbufstatus,
1262  gt10_rxoutclk_out => gt10_rxoutclk,
1263  gt10_rxbufstatus_out => gt10_rxbufstatus,
1264  gt11_rxoutclk_out => gt11_rxoutclk,
1265  gt11_rxbufstatus_out => gt11_rxbufstatus,
1266 
1267  --_________________________________________________________________________
1268  --GT0 (X0Y0)
1269  --____________________________CHANNEL PORTS________________________________
1270  ---------------------------- Channel - DRP Ports --------------------------
1271  GT0_DRPADDR_IN => (others => '0'),
1272  GT0_DRPCLK_IN => DRPclk,
1273  GT0_DRPDI_IN => (others => '0'),
1274  GT0_DRPDO_OUT => open,
1275  GT0_DRPEN_IN => '0',
1276  GT0_DRPRDY_OUT => open,
1277  GT0_DRPWE_IN => '0',
1278  --------------------------- Digital Monitor Ports --------------------------
1279  GT0_DMONITOROUT_OUT => open,
1280  ------------------------------- Loopback Ports -----------------------------
1281  GT0_LOOPBACK_IN => loopback(0),
1282  ------------------------------ Power-Down Ports ----------------------------
1283  GT0_RXPD_IN => AMC_pd(0),
1284  GT0_TXPD_IN => AMC_pd(0),
1285  --------------------- RX Initialization and Reset Ports --------------------
1286  GT0_EYESCANRESET_IN => '0',
1287  GT0_RXUSERRDY_IN => '0',
1288  -------------------------- RX Margin Analysis Ports ------------------------
1289  GT0_EYESCANDATAERROR_OUT => open,
1290  GT0_EYESCANTRIGGER_IN => '0',
1291  ------------------- Receive Ports - Clock Correction Ports -----------------
1292  GT0_RXCLKCORCNT_OUT => open,
1293  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
1294  GT0_RXUSRCLK_IN => UsrClk,
1295  GT0_RXUSRCLK2_IN => UsrClk,
1296  ------------------ Receive Ports - FPGA RX interface Ports -----------------
1297  GT0_RXDATA_OUT => RXDATA_i(0),
1298  ------------------- Receive Ports - Pattern Checker Ports ------------------
1299  GT0_RXPRBSERR_OUT => rxprbserr(0),
1300  GT0_RXPRBSSEL_IN => rxprbssel(0),
1301  ------------------- Receive Ports - Pattern Checker ports ------------------
1302  GT0_RXPRBSCNTRESET_IN => '0',
1303  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
1304  GT0_RXDISPERR_OUT => open,
1305  GT0_RXNOTINTABLE_OUT => RXNOTINTABLE_i(0),
1306  --------------------------- Receive Ports - RX AFE -------------------------
1307  GT0_GTXRXP_IN => RXP(0),
1308  ------------------------ Receive Ports - RX AFE Ports ----------------------
1309  GT0_GTXRXN_IN => RXN(0),
1310  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
1311  GT0_RXMCOMMAALIGNEN_IN => rxcommaalignen(0),
1312  GT0_RXPCOMMAALIGNEN_IN => rxcommaalignen(0),
1313  --------------------- Receive Ports - RX Equalizer Ports -------------------
1314  GT0_RXDFELPMRESET_IN => '0',
1315  GT0_RXMONITOROUT_OUT => open,
1316  GT0_RXMONITORSEL_IN => "00",
1317  ------------- Receive Ports - RX Initialization and Reset Ports ------------
1318  GT0_GTRXRESET_IN => qpll_lock_n(0),
1319  GT0_RXPMARESET_IN => '0',
1320  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
1321  GT0_RXCHARISCOMMA_OUT => rxchariscomma_i(0),
1322  GT0_RXCHARISK_OUT => rxcharisk_i(0),
1323  -------------- Receive Ports -RX Initialization and Reset Ports ------------
1324  GT0_RXRESETDONE_OUT => rxresetdone_i(0),
1325  --------------------- TX Initialization and Reset Ports --------------------
1326  GT0_GTTXRESET_IN => qpll_lock_n(0),
1327  GT0_TXUSERRDY_IN => '0',
1328  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
1329  GT0_TXUSRCLK_IN => UsrClk,
1330  GT0_TXUSRCLK2_IN => UsrClk,
1331  --------------- Transmit Ports - TX Configurable Driver Ports --------------
1332  GT0_TXDIFFCTRL_IN => txdiffctrl(0),
1333  ------------------ Transmit Ports - TX Data Path interface -----------------
1334  GT0_TXDATA_IN => TXDATA(0),
1335  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
1336  GT0_GTXTXN_OUT => TXN(0),
1337  GT0_GTXTXP_OUT => TXP(0),
1338  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
1339  GT0_TXOUTCLK_OUT => txoutclk(0),
1340  GT0_TXOUTCLKFABRIC_OUT => open,
1341  GT0_TXOUTCLKPCS_OUT => open,
1342  --------------------- Transmit Ports - TX Gearbox Ports --------------------
1343  GT0_TXCHARISK_IN => txcharisk(0),
1344  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
1345  GT0_TXRESETDONE_OUT => txresetdone(0),
1346  ------------------ Transmit Ports - pattern Generator Ports ----------------
1347  GT0_TXPRBSSEL_IN => txprbssel(0),
1348 
1349  --GT1 (X0Y1)
1350  --____________________________CHANNEL PORTS________________________________
1351  ---------------------------- Channel - DRP Ports --------------------------
1352  GT1_DRPADDR_IN => (others => '0'),
1353  GT1_DRPCLK_IN => DRPclk,
1354  GT1_DRPDI_IN => (others => '0'),
1355  GT1_DRPDO_OUT => open,
1356  GT1_DRPEN_IN => '0',
1357  GT1_DRPRDY_OUT => open,
1358  GT1_DRPWE_IN => '0',
1359  --------------------------- Digital Monitor Ports --------------------------
1360  GT1_DMONITOROUT_OUT => open,
1361  ------------------------------- Loopback Ports -----------------------------
1362  GT1_LOOPBACK_IN => loopback(1),
1363  ------------------------------ Power-Down Ports ----------------------------
1364  GT1_RXPD_IN => AMC_pd(1),
1365  GT1_TXPD_IN => AMC_pd(1),
1366  --------------------- RX Initialization and Reset Ports --------------------
1367  GT1_EYESCANRESET_IN => '0',
1368  GT1_RXUSERRDY_IN => '0',
1369  -------------------------- RX Margin Analysis Ports ------------------------
1370  GT1_EYESCANDATAERROR_OUT => open,
1371  GT1_EYESCANTRIGGER_IN => '0',
1372  ------------------- Receive Ports - Clock Correction Ports -----------------
1373  GT1_RXCLKCORCNT_OUT => open,
1374  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
1375  GT1_RXUSRCLK_IN => UsrClk,
1376  GT1_RXUSRCLK2_IN => UsrClk,
1377  ------------------ Receive Ports - FPGA RX interface Ports -----------------
1378  GT1_RXDATA_OUT => RXDATA_i(1),
1379  ------------------- Receive Ports - Pattern Checker Ports ------------------
1380  GT1_RXPRBSERR_OUT => rxprbserr(1),
1381  GT1_RXPRBSSEL_IN => rxprbssel(1),
1382  ------------------- Receive Ports - Pattern Checker ports ------------------
1383  GT1_RXPRBSCNTRESET_IN => '0',
1384  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
1385  GT1_RXDISPERR_OUT => open,
1386  GT1_RXNOTINTABLE_OUT => RXNOTINTABLE_i(1),
1387  --------------------------- Receive Ports - RX AFE -------------------------
1388  GT1_GTXRXP_IN => RXP(1),
1389  ------------------------ Receive Ports - RX AFE Ports ----------------------
1390  GT1_GTXRXN_IN => RXN(1),
1391  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
1392  GT1_RXMCOMMAALIGNEN_IN => rxcommaalignen(1),
1393  GT1_RXPCOMMAALIGNEN_IN => rxcommaalignen(1),
1394  --------------------- Receive Ports - RX Equalizer Ports -------------------
1395  GT1_RXDFELPMRESET_IN => '0',
1396  GT1_RXMONITOROUT_OUT => open,
1397  GT1_RXMONITORSEL_IN => "00",
1398  ------------- Receive Ports - RX Initialization and Reset Ports ------------
1399  GT1_GTRXRESET_IN => qpll_lock_n(1),
1400  GT1_RXPMARESET_IN => '0',
1401  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
1402  GT1_RXCHARISCOMMA_OUT => rxchariscomma_i(1),
1403  GT1_RXCHARISK_OUT => rxcharisk_i(1),
1404  -------------- Receive Ports -RX Initialization and Reset Ports ------------
1405  GT1_RXRESETDONE_OUT => rxresetdone_i(1),
1406  --------------------- TX Initialization and Reset Ports --------------------
1407  GT1_GTTXRESET_IN => qpll_lock_n(0),
1408  GT1_TXUSERRDY_IN => '0',
1409  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
1410  GT1_TXUSRCLK_IN => UsrClk,
1411  GT1_TXUSRCLK2_IN => UsrClk,
1412  --------------- Transmit Ports - TX Configurable Driver Ports --------------
1413  GT1_TXDIFFCTRL_IN => txdiffctrl(1),
1414  ------------------ Transmit Ports - TX Data Path interface -----------------
1415  GT1_TXDATA_IN => TXDATA(1),
1416  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
1417  GT1_GTXTXN_OUT => TXN(1),
1418  GT1_GTXTXP_OUT => TXP(1),
1419  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
1420  GT1_TXOUTCLK_OUT => txoutclk(1),
1421  GT1_TXOUTCLKFABRIC_OUT => open,
1422  GT1_TXOUTCLKPCS_OUT => open,
1423  --------------------- Transmit Ports - TX Gearbox Ports --------------------
1424  GT1_TXCHARISK_IN => txcharisk(1),
1425  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
1426  GT1_TXRESETDONE_OUT => txresetdone(1),
1427  ------------------ Transmit Ports - pattern Generator Ports ----------------
1428  GT1_TXPRBSSEL_IN => txprbssel(1),
1429 
1430  --GT2 (X0Y2)
1431  --____________________________CHANNEL PORTS________________________________
1432  ---------------------------- Channel - DRP Ports --------------------------
1433  GT2_DRPADDR_IN => (others => '0'),
1434  GT2_DRPCLK_IN => DRPclk,
1435  GT2_DRPDI_IN => (others => '0'),
1436  GT2_DRPDO_OUT => open,
1437  GT2_DRPEN_IN => '0',
1438  GT2_DRPRDY_OUT => open,
1439  GT2_DRPWE_IN => '0',
1440  --------------------------- Digital Monitor Ports --------------------------
1441  GT2_DMONITOROUT_OUT => open,
1442  ------------------------------- Loopback Ports -----------------------------
1443  GT2_LOOPBACK_IN => loopback(2),
1444  ------------------------------ Power-Down Ports ----------------------------
1445  GT2_RXPD_IN => AMC_pd(2),
1446  GT2_TXPD_IN => AMC_pd(2),
1447  --------------------- RX Initialization and Reset Ports --------------------
1448  GT2_EYESCANRESET_IN => '0',
1449  GT2_RXUSERRDY_IN => '0',
1450  -------------------------- RX Margin Analysis Ports ------------------------
1451  GT2_EYESCANDATAERROR_OUT => open,
1452  GT2_EYESCANTRIGGER_IN => '0',
1453  ------------------- Receive Ports - Clock Correction Ports -----------------
1454  GT2_RXCLKCORCNT_OUT => open,
1455  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
1456  GT2_RXUSRCLK_IN => UsrClk,
1457  GT2_RXUSRCLK2_IN => UsrClk,
1458  ------------------ Receive Ports - FPGA RX interface Ports -----------------
1459  GT2_RXDATA_OUT => RXDATA_i(2),
1460  ------------------- Receive Ports - Pattern Checker Ports ------------------
1461  GT2_RXPRBSERR_OUT => rxprbserr(2),
1462  GT2_RXPRBSSEL_IN => rxprbssel(2),
1463  ------------------- Receive Ports - Pattern Checker ports ------------------
1464  GT2_RXPRBSCNTRESET_IN => '0',
1465  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
1466  GT2_RXDISPERR_OUT => open,
1467  GT2_RXNOTINTABLE_OUT => RXNOTINTABLE_i(2),
1468  --------------------------- Receive Ports - RX AFE -------------------------
1469  GT2_GTXRXP_IN => RXP(2),
1470  ------------------------ Receive Ports - RX AFE Ports ----------------------
1471  GT2_GTXRXN_IN => RXN(2),
1472  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
1473  GT2_RXMCOMMAALIGNEN_IN => rxcommaalignen(2),
1474  GT2_RXPCOMMAALIGNEN_IN => rxcommaalignen(2),
1475  --------------------- Receive Ports - RX Equalizer Ports -------------------
1476  GT2_RXDFELPMRESET_IN => '0',
1477  GT2_RXMONITOROUT_OUT => open,
1478  GT2_RXMONITORSEL_IN => "00",
1479  ------------- Receive Ports - RX Initialization and Reset Ports ------------
1480  GT2_GTRXRESET_IN => qpll_lock_n(0),
1481  GT2_RXPMARESET_IN => '0',
1482  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
1483  GT2_RXCHARISCOMMA_OUT => rxchariscomma_i(2),
1484  GT2_RXCHARISK_OUT => rxcharisk_i(2),
1485  -------------- Receive Ports -RX Initialization and Reset Ports ------------
1486  GT2_RXRESETDONE_OUT => rxresetdone_i(2),
1487  --------------------- TX Initialization and Reset Ports --------------------
1488  GT2_GTTXRESET_IN => qpll_lock_n(2),
1489  GT2_TXUSERRDY_IN => '0',
1490  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
1491  GT2_TXUSRCLK_IN => UsrClk,
1492  GT2_TXUSRCLK2_IN => UsrClk,
1493  --------------- Transmit Ports - TX Configurable Driver Ports --------------
1494  GT2_TXDIFFCTRL_IN => txdiffctrl(2),
1495  ------------------ Transmit Ports - TX Data Path interface -----------------
1496  GT2_TXDATA_IN => TXDATA(2),
1497  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
1498  GT2_GTXTXN_OUT => TXN(2),
1499  GT2_GTXTXP_OUT => TXP(2),
1500  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
1501  GT2_TXOUTCLK_OUT => txoutclk(2),
1502  GT2_TXOUTCLKFABRIC_OUT => open,
1503  GT2_TXOUTCLKPCS_OUT => open,
1504  --------------------- Transmit Ports - TX Gearbox Ports --------------------
1505  GT2_TXCHARISK_IN => txcharisk(2),
1506  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
1507  GT2_TXRESETDONE_OUT => txresetdone(2),
1508  ------------------ Transmit Ports - pattern Generator Ports ----------------
1509  GT2_TXPRBSSEL_IN => txprbssel(2),
1510 
1511  --GT3 (X0Y3)
1512  --____________________________CHANNEL PORTS________________________________
1513  ---------------------------- Channel - DRP Ports --------------------------
1514  GT3_DRPADDR_IN => (others => '0'),
1515  GT3_DRPCLK_IN => DRPclk,
1516  GT3_DRPDI_IN => (others => '0'),
1517  GT3_DRPDO_OUT => open,
1518  GT3_DRPEN_IN => '0',
1519  GT3_DRPRDY_OUT => open,
1520  GT3_DRPWE_IN => '0',
1521  --------------------------- Digital Monitor Ports --------------------------
1522  GT3_DMONITOROUT_OUT => open,
1523  ------------------------------- Loopback Ports -----------------------------
1524  GT3_LOOPBACK_IN => loopback(3),
1525  ------------------------------ Power-Down Ports ----------------------------
1526  GT3_RXPD_IN => AMC_pd(3),
1527  GT3_TXPD_IN => AMC_pd(3),
1528  --------------------- RX Initialization and Reset Ports --------------------
1529  GT3_EYESCANRESET_IN => '0',
1530  GT3_RXUSERRDY_IN => '0',
1531  -------------------------- RX Margin Analysis Ports ------------------------
1532  GT3_EYESCANDATAERROR_OUT => open,
1533  GT3_EYESCANTRIGGER_IN => '0',
1534  ------------------- Receive Ports - Clock Correction Ports -----------------
1535  GT3_RXCLKCORCNT_OUT => open,
1536  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
1537  GT3_RXUSRCLK_IN => UsrClk,
1538  GT3_RXUSRCLK2_IN => UsrClk,
1539  ------------------ Receive Ports - FPGA RX interface Ports -----------------
1540  GT3_RXDATA_OUT => RXDATA_i(3),
1541  ------------------- Receive Ports - Pattern Checker Ports ------------------
1542  GT3_RXPRBSERR_OUT => rxprbserr(3),
1543  GT3_RXPRBSSEL_IN => rxprbssel(3),
1544  ------------------- Receive Ports - Pattern Checker ports ------------------
1545  GT3_RXPRBSCNTRESET_IN => '0',
1546  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
1547  GT3_RXDISPERR_OUT => open,
1548  GT3_RXNOTINTABLE_OUT => RXNOTINTABLE_i(3),
1549  --------------------------- Receive Ports - RX AFE -------------------------
1550  GT3_GTXRXP_IN => RXP(3),
1551  ------------------------ Receive Ports - RX AFE Ports ----------------------
1552  GT3_GTXRXN_IN => RXN(3),
1553  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
1554  GT3_RXMCOMMAALIGNEN_IN => rxcommaalignen(3),
1555  GT3_RXPCOMMAALIGNEN_IN => rxcommaalignen(3),
1556  --------------------- Receive Ports - RX Equalizer Ports -------------------
1557  GT3_RXDFELPMRESET_IN => '0',
1558  GT3_RXMONITOROUT_OUT => open,
1559  GT3_RXMONITORSEL_IN => "00",
1560  ------------- Receive Ports - RX Initialization and Reset Ports ------------
1561  GT3_GTRXRESET_IN => qpll_lock_n(0),
1562  GT3_RXPMARESET_IN => '0',
1563  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
1564  GT3_RXCHARISCOMMA_OUT => rxchariscomma_i(3),
1565  GT3_RXCHARISK_OUT => rxcharisk_i(3),
1566  -------------- Receive Ports -RX Initialization and Reset Ports ------------
1567  GT3_RXRESETDONE_OUT => rxresetdone_i(3),
1568  --------------------- TX Initialization and Reset Ports --------------------
1569  GT3_GTTXRESET_IN => qpll_lock_n(0),
1570  GT3_TXUSERRDY_IN => '0',
1571  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
1572  GT3_TXUSRCLK_IN => UsrClk,
1573  GT3_TXUSRCLK2_IN => UsrClk,
1574  --------------- Transmit Ports - TX Configurable Driver Ports --------------
1575  GT3_TXDIFFCTRL_IN => txdiffctrl(3),
1576  ------------------ Transmit Ports - TX Data Path interface -----------------
1577  GT3_TXDATA_IN => TXDATA(3),
1578  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
1579  GT3_GTXTXN_OUT => TXN(3),
1580  GT3_GTXTXP_OUT => TXP(3),
1581  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
1582  GT3_TXOUTCLK_OUT => txoutclk(3),
1583  GT3_TXOUTCLKFABRIC_OUT => open,
1584  GT3_TXOUTCLKPCS_OUT => open,
1585  --------------------- Transmit Ports - TX Gearbox Ports --------------------
1586  GT3_TXCHARISK_IN => txcharisk(3),
1587  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
1588  GT3_TXRESETDONE_OUT => txresetdone(3),
1589  ------------------ Transmit Ports - pattern Generator Ports ----------------
1590  GT3_TXPRBSSEL_IN => txprbssel(3),
1591 
1592  --GT4 (X0Y4)
1593  --____________________________CHANNEL PORTS________________________________
1594  ---------------------------- Channel - DRP Ports --------------------------
1595  GT4_DRPADDR_IN => (others => '0'),
1596  GT4_DRPCLK_IN => DRPclk,
1597  GT4_DRPDI_IN => (others => '0'),
1598  GT4_DRPDO_OUT => open,
1599  GT4_DRPEN_IN => '0',
1600  GT4_DRPRDY_OUT => open,
1601  GT4_DRPWE_IN => '0',
1602  --------------------------- Digital Monitor Ports --------------------------
1603  GT4_DMONITOROUT_OUT => open,
1604  ------------------------------- Loopback Ports -----------------------------
1605  GT4_LOOPBACK_IN => loopback(4),
1606  ------------------------------ Power-Down Ports ----------------------------
1607  GT4_RXPD_IN => AMC_pd(4),
1608  GT4_TXPD_IN => AMC_pd(4),
1609  --------------------- RX Initialization and Reset Ports --------------------
1610  GT4_EYESCANRESET_IN => '0',
1611  GT4_RXUSERRDY_IN => '0',
1612  -------------------------- RX Margin Analysis Ports ------------------------
1613  GT4_EYESCANDATAERROR_OUT => open,
1614  GT4_EYESCANTRIGGER_IN => '0',
1615  ------------------- Receive Ports - Clock Correction Ports -----------------
1616  GT4_RXCLKCORCNT_OUT => open,
1617  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
1618  GT4_RXUSRCLK_IN => UsrClk,
1619  GT4_RXUSRCLK2_IN => UsrClk,
1620  ------------------ Receive Ports - FPGA RX interface Ports -----------------
1621  GT4_RXDATA_OUT => RXDATA_i(4),
1622  ------------------- Receive Ports - Pattern Checker Ports ------------------
1623  GT4_RXPRBSERR_OUT => rxprbserr(4),
1624  GT4_RXPRBSSEL_IN => rxprbssel(4),
1625  ------------------- Receive Ports - Pattern Checker ports ------------------
1626  GT4_RXPRBSCNTRESET_IN => '0',
1627  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
1628  GT4_RXDISPERR_OUT => open,
1629  GT4_RXNOTINTABLE_OUT => RXNOTINTABLE_i(4),
1630  --------------------------- Receive Ports - RX AFE -------------------------
1631  GT4_GTXRXP_IN => RXP(4),
1632  ------------------------ Receive Ports - RX AFE Ports ----------------------
1633  GT4_GTXRXN_IN => RXN(4),
1634  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
1635  GT4_RXMCOMMAALIGNEN_IN => rxcommaalignen(4),
1636  GT4_RXPCOMMAALIGNEN_IN => rxcommaalignen(4),
1637  --------------------- Receive Ports - RX Equalizer Ports -------------------
1638  GT4_RXDFELPMRESET_IN => '0',
1639  GT4_RXMONITOROUT_OUT => open,
1640  GT4_RXMONITORSEL_IN => "00",
1641  ------------- Receive Ports - RX Initialization and Reset Ports ------------
1642  GT4_GTRXRESET_IN => qpll_lock_n(1),
1643  GT4_RXPMARESET_IN => '0',
1644  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
1645  GT4_RXCHARISCOMMA_OUT => rxchariscomma_i(4),
1646  GT4_RXCHARISK_OUT => rxcharisk_i(4),
1647  -------------- Receive Ports -RX Initialization and Reset Ports ------------
1648  GT4_RXRESETDONE_OUT => rxresetdone_i(4),
1649  --------------------- TX Initialization and Reset Ports --------------------
1650  GT4_GTTXRESET_IN => qpll_lock_n(1),
1651  GT4_TXUSERRDY_IN => '0',
1652  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
1653  GT4_TXUSRCLK_IN => UsrClk,
1654  GT4_TXUSRCLK2_IN => UsrClk,
1655  --------------- Transmit Ports - TX Configurable Driver Ports --------------
1656  GT4_TXDIFFCTRL_IN => txdiffctrl(4),
1657  ------------------ Transmit Ports - TX Data Path interface -----------------
1658  GT4_TXDATA_IN => TXDATA(4),
1659  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
1660  GT4_GTXTXN_OUT => TXN(4),
1661  GT4_GTXTXP_OUT => TXP(4),
1662  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
1663  GT4_TXOUTCLK_OUT => txoutclk(4),
1664  GT4_TXOUTCLKFABRIC_OUT => open,
1665  GT4_TXOUTCLKPCS_OUT => open,
1666  --------------------- Transmit Ports - TX Gearbox Ports --------------------
1667  GT4_TXCHARISK_IN => txcharisk(4),
1668  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
1669  GT4_TXRESETDONE_OUT => txresetdone(4),
1670  ------------------ Transmit Ports - pattern Generator Ports ----------------
1671  GT4_TXPRBSSEL_IN => txprbssel(4),
1672 
1673  --GT5 (X0Y5)
1674  --____________________________CHANNEL PORTS________________________________
1675  ---------------------------- Channel - DRP Ports --------------------------
1676  GT5_DRPADDR_IN => (others => '0'),
1677  GT5_DRPCLK_IN => DRPclk,
1678  GT5_DRPDI_IN => (others => '0'),
1679  GT5_DRPDO_OUT => open,
1680  GT5_DRPEN_IN => '0',
1681  GT5_DRPRDY_OUT => open,
1682  GT5_DRPWE_IN => '0',
1683  --------------------------- Digital Monitor Ports --------------------------
1684  GT5_DMONITOROUT_OUT => open,
1685  ------------------------------- Loopback Ports -----------------------------
1686  GT5_LOOPBACK_IN => loopback(5),
1687  ------------------------------ Power-Down Ports ----------------------------
1688  GT5_RXPD_IN => AMC_pd(5),
1689  GT5_TXPD_IN => AMC_pd(5),
1690  --------------------- RX Initialization and Reset Ports --------------------
1691  GT5_EYESCANRESET_IN => '0',
1692  GT5_RXUSERRDY_IN => '0',
1693  -------------------------- RX Margin Analysis Ports ------------------------
1694  GT5_EYESCANDATAERROR_OUT => open,
1695  GT5_EYESCANTRIGGER_IN => '0',
1696  ------------------- Receive Ports - Clock Correction Ports -----------------
1697  GT5_RXCLKCORCNT_OUT => open,
1698  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
1699  GT5_RXUSRCLK_IN => UsrClk,
1700  GT5_RXUSRCLK2_IN => UsrClk,
1701  ------------------ Receive Ports - FPGA RX interface Ports -----------------
1702  GT5_RXDATA_OUT => RXDATA_i(5),
1703  ------------------- Receive Ports - Pattern Checker Ports ------------------
1704  GT5_RXPRBSERR_OUT => rxprbserr(5),
1705  GT5_RXPRBSSEL_IN => rxprbssel(5),
1706  ------------------- Receive Ports - Pattern Checker ports ------------------
1707  GT5_RXPRBSCNTRESET_IN => '0',
1708  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
1709  GT5_RXDISPERR_OUT => open,
1710  GT5_RXNOTINTABLE_OUT => RXNOTINTABLE_i(5),
1711  --------------------------- Receive Ports - RX AFE -------------------------
1712  GT5_GTXRXP_IN => RXP(5),
1713  ------------------------ Receive Ports - RX AFE Ports ----------------------
1714  GT5_GTXRXN_IN => RXN(5),
1715  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
1716  GT5_RXMCOMMAALIGNEN_IN => rxcommaalignen(5),
1717  GT5_RXPCOMMAALIGNEN_IN => rxcommaalignen(5),
1718  --------------------- Receive Ports - RX Equalizer Ports -------------------
1719  GT5_RXDFELPMRESET_IN => '0',
1720  GT5_RXMONITOROUT_OUT => open,
1721  GT5_RXMONITORSEL_IN => "00",
1722  ------------- Receive Ports - RX Initialization and Reset Ports ------------
1723  GT5_GTRXRESET_IN => qpll_lock_n(1),
1724  GT5_RXPMARESET_IN => '0',
1725  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
1726  GT5_RXCHARISCOMMA_OUT => rxchariscomma_i(5),
1727  GT5_RXCHARISK_OUT => rxcharisk_i(5),
1728  -------------- Receive Ports -RX Initialization and Reset Ports ------------
1729  GT5_RXRESETDONE_OUT => rxresetdone_i(5),
1730  --------------------- TX Initialization and Reset Ports --------------------
1731  GT5_GTTXRESET_IN => qpll_lock_n(1),
1732  GT5_TXUSERRDY_IN => '0',
1733  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
1734  GT5_TXUSRCLK_IN => UsrClk,
1735  GT5_TXUSRCLK2_IN => UsrClk,
1736  --------------- Transmit Ports - TX Configurable Driver Ports --------------
1737  GT5_TXDIFFCTRL_IN => txdiffctrl(5),
1738  ------------------ Transmit Ports - TX Data Path interface -----------------
1739  GT5_TXDATA_IN => TXDATA(5),
1740  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
1741  GT5_GTXTXN_OUT => TXN(5),
1742  GT5_GTXTXP_OUT => TXP(5),
1743  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
1744  GT5_TXOUTCLK_OUT => txoutclk(5),
1745  GT5_TXOUTCLKFABRIC_OUT => open,
1746  GT5_TXOUTCLKPCS_OUT => open,
1747  --------------------- Transmit Ports - TX Gearbox Ports --------------------
1748  GT5_TXCHARISK_IN => txcharisk(5),
1749  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
1750  GT5_TXRESETDONE_OUT => txresetdone(5),
1751  ------------------ Transmit Ports - pattern Generator Ports ----------------
1752  GT5_TXPRBSSEL_IN => txprbssel(5),
1753 
1754  --GT6 (X0Y6)
1755  --____________________________CHANNEL PORTS________________________________
1756  ---------------------------- Channel - DRP Ports --------------------------
1757  GT6_DRPADDR_IN => (others => '0'),
1758  GT6_DRPCLK_IN => DRPclk,
1759  GT6_DRPDI_IN => (others => '0'),
1760  GT6_DRPDO_OUT => open,
1761  GT6_DRPEN_IN => '0',
1762  GT6_DRPRDY_OUT => open,
1763  GT6_DRPWE_IN => '0',
1764  --------------------------- Digital Monitor Ports --------------------------
1765  GT6_DMONITOROUT_OUT => open,
1766  ------------------------------- Loopback Ports -----------------------------
1767  GT6_LOOPBACK_IN => loopback(6),
1768  ------------------------------ Power-Down Ports ----------------------------
1769  GT6_RXPD_IN => AMC_pd(6),
1770  GT6_TXPD_IN => AMC_pd(6),
1771  --------------------- RX Initialization and Reset Ports --------------------
1772  GT6_EYESCANRESET_IN => '0',
1773  GT6_RXUSERRDY_IN => '0',
1774  -------------------------- RX Margin Analysis Ports ------------------------
1775  GT6_EYESCANDATAERROR_OUT => open,
1776  GT6_EYESCANTRIGGER_IN => '0',
1777  ------------------- Receive Ports - Clock Correction Ports -----------------
1778  GT6_RXCLKCORCNT_OUT => open,
1779  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
1780  GT6_RXUSRCLK_IN => UsrClk,
1781  GT6_RXUSRCLK2_IN => UsrClk,
1782  ------------------ Receive Ports - FPGA RX interface Ports -----------------
1783  GT6_RXDATA_OUT => RXDATA_i(6),
1784  ------------------- Receive Ports - Pattern Checker Ports ------------------
1785  GT6_RXPRBSERR_OUT => rxprbserr(6),
1786  GT6_RXPRBSSEL_IN => rxprbssel(6),
1787  ------------------- Receive Ports - Pattern Checker ports ------------------
1788  GT6_RXPRBSCNTRESET_IN => '0',
1789  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
1790  GT6_RXDISPERR_OUT => open,
1791  GT6_RXNOTINTABLE_OUT => RXNOTINTABLE_i(6),
1792  --------------------------- Receive Ports - RX AFE -------------------------
1793  GT6_GTXRXP_IN => RXP(6),
1794  ------------------------ Receive Ports - RX AFE Ports ----------------------
1795  GT6_GTXRXN_IN => RXN(6),
1796  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
1797  GT6_RXMCOMMAALIGNEN_IN => rxcommaalignen(6),
1798  GT6_RXPCOMMAALIGNEN_IN => rxcommaalignen(6),
1799  --------------------- Receive Ports - RX Equalizer Ports -------------------
1800  GT6_RXDFELPMRESET_IN => '0',
1801  GT6_RXMONITOROUT_OUT => open,
1802  GT6_RXMONITORSEL_IN => "00",
1803  ------------- Receive Ports - RX Initialization and Reset Ports ------------
1804  GT6_GTRXRESET_IN => qpll_lock_n(1),
1805  GT6_RXPMARESET_IN => '0',
1806  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
1807  GT6_RXCHARISCOMMA_OUT => rxchariscomma_i(6),
1808  GT6_RXCHARISK_OUT => rxcharisk_i(6),
1809  -------------- Receive Ports -RX Initialization and Reset Ports ------------
1810  GT6_RXRESETDONE_OUT => rxresetdone_i(6),
1811  --------------------- TX Initialization and Reset Ports --------------------
1812  GT6_GTTXRESET_IN => qpll_lock_n(1),
1813  GT6_TXUSERRDY_IN => '0',
1814  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
1815  GT6_TXUSRCLK_IN => UsrClk,
1816  GT6_TXUSRCLK2_IN => UsrClk,
1817  --------------- Transmit Ports - TX Configurable Driver Ports --------------
1818  GT6_TXDIFFCTRL_IN => txdiffctrl(6),
1819  ------------------ Transmit Ports - TX Data Path interface -----------------
1820  GT6_TXDATA_IN => TXDATA(6),
1821  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
1822  GT6_GTXTXN_OUT => TXN(6),
1823  GT6_GTXTXP_OUT => TXP(6),
1824  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
1825  GT6_TXOUTCLK_OUT => txoutclk(6),
1826  GT6_TXOUTCLKFABRIC_OUT => open,
1827  GT6_TXOUTCLKPCS_OUT => open,
1828  --------------------- Transmit Ports - TX Gearbox Ports --------------------
1829  GT6_TXCHARISK_IN => txcharisk(6),
1830  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
1831  GT6_TXRESETDONE_OUT => txresetdone(6),
1832  ------------------ Transmit Ports - pattern Generator Ports ----------------
1833  GT6_TXPRBSSEL_IN => txprbssel(6),
1834 
1835  --GT7 (X0Y7)
1836  --____________________________CHANNEL PORTS________________________________
1837  ---------------------------- Channel - DRP Ports --------------------------
1838  GT7_DRPADDR_IN => (others => '0'),
1839  GT7_DRPCLK_IN => DRPclk,
1840  GT7_DRPDI_IN => (others => '0'),
1841  GT7_DRPDO_OUT => open,
1842  GT7_DRPEN_IN => '0',
1843  GT7_DRPRDY_OUT => open,
1844  GT7_DRPWE_IN => '0',
1845  --------------------------- Digital Monitor Ports --------------------------
1846  GT7_DMONITOROUT_OUT => open,
1847  ------------------------------- Loopback Ports -----------------------------
1848  GT7_LOOPBACK_IN => loopback(7),
1849  ------------------------------ Power-Down Ports ----------------------------
1850  GT7_RXPD_IN => AMC_pd(7),
1851  GT7_TXPD_IN => AMC_pd(7),
1852  --------------------- RX Initialization and Reset Ports --------------------
1853  GT7_EYESCANRESET_IN => '0',
1854  GT7_RXUSERRDY_IN => '0',
1855  -------------------------- RX Margin Analysis Ports ------------------------
1856  GT7_EYESCANDATAERROR_OUT => open,
1857  GT7_EYESCANTRIGGER_IN => '0',
1858  ------------------- Receive Ports - Clock Correction Ports -----------------
1859  GT7_RXCLKCORCNT_OUT => open,
1860  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
1861  GT7_RXUSRCLK_IN => UsrClk,
1862  GT7_RXUSRCLK2_IN => UsrClk,
1863  ------------------ Receive Ports - FPGA RX interface Ports -----------------
1864  GT7_RXDATA_OUT => RXDATA_i(7),
1865  ------------------- Receive Ports - Pattern Checker Ports ------------------
1866  GT7_RXPRBSERR_OUT => rxprbserr(7),
1867  GT7_RXPRBSSEL_IN => rxprbssel(7),
1868  ------------------- Receive Ports - Pattern Checker ports ------------------
1869  GT7_RXPRBSCNTRESET_IN => '0',
1870  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
1871  GT7_RXDISPERR_OUT => open,
1872  GT7_RXNOTINTABLE_OUT => RXNOTINTABLE_i(7),
1873  --------------------------- Receive Ports - RX AFE -------------------------
1874  GT7_GTXRXP_IN => RXP(7),
1875  ------------------------ Receive Ports - RX AFE Ports ----------------------
1876  GT7_GTXRXN_IN => RXN(7),
1877  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
1878  GT7_RXMCOMMAALIGNEN_IN => rxcommaalignen(7),
1879  GT7_RXPCOMMAALIGNEN_IN => rxcommaalignen(7),
1880  --------------------- Receive Ports - RX Equalizer Ports -------------------
1881  GT7_RXDFELPMRESET_IN => '0',
1882  GT7_RXMONITOROUT_OUT => open,
1883  GT7_RXMONITORSEL_IN => "00",
1884  ------------- Receive Ports - RX Initialization and Reset Ports ------------
1885  GT7_GTRXRESET_IN => qpll_lock_n(1),
1886  GT7_RXPMARESET_IN => '0',
1887  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
1888  GT7_RXCHARISCOMMA_OUT => rxchariscomma_i(7),
1889  GT7_RXCHARISK_OUT => rxcharisk_i(7),
1890  -------------- Receive Ports -RX Initialization and Reset Ports ------------
1891  GT7_RXRESETDONE_OUT => rxresetdone_i(7),
1892  --------------------- TX Initialization and Reset Ports --------------------
1893  GT7_GTTXRESET_IN => qpll_lock_n(1),
1894  GT7_TXUSERRDY_IN => '0',
1895  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
1896  GT7_TXUSRCLK_IN => UsrClk,
1897  GT7_TXUSRCLK2_IN => UsrClk,
1898  --------------- Transmit Ports - TX Configurable Driver Ports --------------
1899  GT7_TXDIFFCTRL_IN => txdiffctrl(7),
1900  ------------------ Transmit Ports - TX Data Path interface -----------------
1901  GT7_TXDATA_IN => TXDATA(7),
1902  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
1903  GT7_GTXTXN_OUT => TXN(7),
1904  GT7_GTXTXP_OUT => TXP(7),
1905  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
1906  GT7_TXOUTCLK_OUT => txoutclk(7),
1907  GT7_TXOUTCLKFABRIC_OUT => open,
1908  GT7_TXOUTCLKPCS_OUT => open,
1909  --------------------- Transmit Ports - TX Gearbox Ports --------------------
1910  GT7_TXCHARISK_IN => txcharisk(7),
1911  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
1912  GT7_TXRESETDONE_OUT => txresetdone(7),
1913  ------------------ Transmit Ports - pattern Generator Ports ----------------
1914  GT7_TXPRBSSEL_IN => txprbssel(7),
1915 
1916  --GT8 (X0Y8)
1917  --____________________________CHANNEL PORTS________________________________
1918  ---------------------------- Channel - DRP Ports --------------------------
1919  GT8_DRPADDR_IN => (others => '0'),
1920  GT8_DRPCLK_IN => DRPclk,
1921  GT8_DRPDI_IN => (others => '0'),
1922  GT8_DRPDO_OUT => open,
1923  GT8_DRPEN_IN => '0',
1924  GT8_DRPRDY_OUT => open,
1925  GT8_DRPWE_IN => '0',
1926  --------------------------- Digital Monitor Ports --------------------------
1927  GT8_DMONITOROUT_OUT => open,
1928  ------------------------------- Loopback Ports -----------------------------
1929  GT8_LOOPBACK_IN => loopback(8),
1930  ------------------------------ Power-Down Ports ----------------------------
1931  GT8_RXPD_IN => AMC_pd(8),
1932  GT8_TXPD_IN => AMC_pd(8),
1933  --------------------- RX Initialization and Reset Ports --------------------
1934  GT8_EYESCANRESET_IN => '0',
1935  GT8_RXUSERRDY_IN => '0',
1936  -------------------------- RX Margin Analysis Ports ------------------------
1937  GT8_EYESCANDATAERROR_OUT => open,
1938  GT8_EYESCANTRIGGER_IN => '0',
1939  ------------------- Receive Ports - Clock Correction Ports -----------------
1940  GT8_RXCLKCORCNT_OUT => open,
1941  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
1942  GT8_RXUSRCLK_IN => UsrClk,
1943  GT8_RXUSRCLK2_IN => UsrClk,
1944  ------------------ Receive Ports - FPGA RX interface Ports -----------------
1945  GT8_RXDATA_OUT => RXDATA_i(8),
1946  ------------------- Receive Ports - Pattern Checker Ports ------------------
1947  GT8_RXPRBSERR_OUT => rxprbserr(8),
1948  GT8_RXPRBSSEL_IN => rxprbssel(8),
1949  ------------------- Receive Ports - Pattern Checker ports ------------------
1950  GT8_RXPRBSCNTRESET_IN => '0',
1951  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
1952  GT8_RXDISPERR_OUT => open,
1953  GT8_RXNOTINTABLE_OUT => RXNOTINTABLE_i(8),
1954  --------------------------- Receive Ports - RX AFE -------------------------
1955  GT8_GTXRXP_IN => RXP(8),
1956  ------------------------ Receive Ports - RX AFE Ports ----------------------
1957  GT8_GTXRXN_IN => RXN(8),
1958  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
1959  GT8_RXMCOMMAALIGNEN_IN => rxcommaalignen(8),
1960  GT8_RXPCOMMAALIGNEN_IN => rxcommaalignen(8),
1961  --------------------- Receive Ports - RX Equalizer Ports -------------------
1962  GT8_RXDFELPMRESET_IN => '0',
1963  GT8_RXMONITOROUT_OUT => open,
1964  GT8_RXMONITORSEL_IN => "00",
1965  ------------- Receive Ports - RX Initialization and Reset Ports ------------
1966  GT8_GTRXRESET_IN => qpll_lock_n(2),
1967  GT8_RXPMARESET_IN => '0',
1968  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
1969  GT8_RXCHARISCOMMA_OUT => rxchariscomma_i(8),
1970  GT8_RXCHARISK_OUT => rxcharisk_i(8),
1971  -------------- Receive Ports -RX Initialization and Reset Ports ------------
1972  GT8_RXRESETDONE_OUT => rxresetdone_i(8),
1973  --------------------- TX Initialization and Reset Ports --------------------
1974  GT8_GTTXRESET_IN => qpll_lock_n(2),
1975  GT8_TXUSERRDY_IN => '0',
1976  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
1977  GT8_TXUSRCLK_IN => UsrClk,
1978  GT8_TXUSRCLK2_IN => UsrClk,
1979  --------------- Transmit Ports - TX Configurable Driver Ports --------------
1980  GT8_TXDIFFCTRL_IN => txdiffctrl(8),
1981  ------------------ Transmit Ports - TX Data Path interface -----------------
1982  GT8_TXDATA_IN => TXDATA(8),
1983  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
1984  GT8_GTXTXN_OUT => TXN(8),
1985  GT8_GTXTXP_OUT => TXP(8),
1986  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
1987  GT8_TXOUTCLK_OUT => txoutclk(8),
1988  GT8_TXOUTCLKFABRIC_OUT => open,
1989  GT8_TXOUTCLKPCS_OUT => open,
1990  --------------------- Transmit Ports - TX Gearbox Ports --------------------
1991  GT8_TXCHARISK_IN => txcharisk(8),
1992  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
1993  GT8_TXRESETDONE_OUT => txresetdone(8),
1994  ------------------ Transmit Ports - pattern Generator Ports ----------------
1995  GT8_TXPRBSSEL_IN => txprbssel(8),
1996 
1997  --GT9 (X0Y9)
1998  --____________________________CHANNEL PORTS________________________________
1999  ---------------------------- Channel - DRP Ports --------------------------
2000  GT9_DRPADDR_IN => (others => '0'),
2001  GT9_DRPCLK_IN => DRPclk,
2002  GT9_DRPDI_IN => (others => '0'),
2003  GT9_DRPDO_OUT => open,
2004  GT9_DRPEN_IN => '0',
2005  GT9_DRPRDY_OUT => open,
2006  GT9_DRPWE_IN => '0',
2007  --------------------------- Digital Monitor Ports --------------------------
2008  GT9_DMONITOROUT_OUT => open,
2009  ------------------------------- Loopback Ports -----------------------------
2010  GT9_LOOPBACK_IN => loopback(9),
2011  ------------------------------ Power-Down Ports ----------------------------
2012  GT9_RXPD_IN => AMC_pd(9),
2013  GT9_TXPD_IN => AMC_pd(9),
2014  --------------------- RX Initialization and Reset Ports --------------------
2015  GT9_EYESCANRESET_IN => '0',
2016  GT9_RXUSERRDY_IN => '0',
2017  -------------------------- RX Margin Analysis Ports ------------------------
2018  GT9_EYESCANDATAERROR_OUT => open,
2019  GT9_EYESCANTRIGGER_IN => '0',
2020  ------------------- Receive Ports - Clock Correction Ports -----------------
2021  GT9_RXCLKCORCNT_OUT => open,
2022  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
2023  GT9_RXUSRCLK_IN => UsrClk,
2024  GT9_RXUSRCLK2_IN => UsrClk,
2025  ------------------ Receive Ports - FPGA RX interface Ports -----------------
2026  GT9_RXDATA_OUT => RXDATA_i(9),
2027  ------------------- Receive Ports - Pattern Checker Ports ------------------
2028  GT9_RXPRBSERR_OUT => rxprbserr(9),
2029  GT9_RXPRBSSEL_IN => rxprbssel(9),
2030  ------------------- Receive Ports - Pattern Checker ports ------------------
2031  GT9_RXPRBSCNTRESET_IN => '0',
2032  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
2033  GT9_RXDISPERR_OUT => open,
2034  GT9_RXNOTINTABLE_OUT => RXNOTINTABLE_i(9),
2035  --------------------------- Receive Ports - RX AFE -------------------------
2036  GT9_GTXRXP_IN => RXP(9),
2037  ------------------------ Receive Ports - RX AFE Ports ----------------------
2038  GT9_GTXRXN_IN => RXN(9),
2039  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
2040  GT9_RXMCOMMAALIGNEN_IN => rxcommaalignen(9),
2041  GT9_RXPCOMMAALIGNEN_IN => rxcommaalignen(9),
2042  --------------------- Receive Ports - RX Equalizer Ports -------------------
2043  GT9_RXDFELPMRESET_IN => '0',
2044  GT9_RXMONITOROUT_OUT => open,
2045  GT9_RXMONITORSEL_IN => "00",
2046  ------------- Receive Ports - RX Initialization and Reset Ports ------------
2047  GT9_GTRXRESET_IN => qpll_lock_n(2),
2048  GT9_RXPMARESET_IN => '0',
2049  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
2050  GT9_RXCHARISCOMMA_OUT => rxchariscomma_i(9),
2051  GT9_RXCHARISK_OUT => rxcharisk_i(9),
2052  -------------- Receive Ports -RX Initialization and Reset Ports ------------
2053  GT9_RXRESETDONE_OUT => rxresetdone_i(9),
2054  --------------------- TX Initialization and Reset Ports --------------------
2055  GT9_GTTXRESET_IN => qpll_lock_n(2),
2056  GT9_TXUSERRDY_IN => '0',
2057  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
2058  GT9_TXUSRCLK_IN => UsrClk,
2059  GT9_TXUSRCLK2_IN => UsrClk,
2060  --------------- Transmit Ports - TX Configurable Driver Ports --------------
2061  GT9_TXDIFFCTRL_IN => txdiffctrl(9),
2062  ------------------ Transmit Ports - TX Data Path interface -----------------
2063  GT9_TXDATA_IN => TXDATA(9),
2064  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
2065  GT9_GTXTXN_OUT => TXN(9),
2066  GT9_GTXTXP_OUT => TXP(9),
2067  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
2068  GT9_TXOUTCLK_OUT => txoutclk(9),
2069  GT9_TXOUTCLKFABRIC_OUT => open,
2070  GT9_TXOUTCLKPCS_OUT => open,
2071  --------------------- Transmit Ports - TX Gearbox Ports --------------------
2072  GT9_TXCHARISK_IN => txcharisk(9),
2073  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
2074  GT9_TXRESETDONE_OUT => txresetdone(9),
2075  ------------------ Transmit Ports - pattern Generator Ports ----------------
2076  GT9_TXPRBSSEL_IN => txprbssel(9),
2077 
2078  --GT10 (X0Y10)
2079  --____________________________CHANNEL PORTS________________________________
2080  ---------------------------- Channel - DRP Ports --------------------------
2081  GT10_DRPADDR_IN => (others => '0'),
2082  GT10_DRPCLK_IN => DRPclk,
2083  GT10_DRPDI_IN => (others => '0'),
2084  GT10_DRPDO_OUT => open,
2085  GT10_DRPEN_IN => '0',
2086  GT10_DRPRDY_OUT => open,
2087  GT10_DRPWE_IN => '0',
2088  --------------------------- Digital Monitor Ports --------------------------
2089  GT10_DMONITOROUT_OUT => open,
2090  ------------------------------- Loopback Ports -----------------------------
2091  GT10_LOOPBACK_IN => loopback(10),
2092  ------------------------------ Power-Down Ports ----------------------------
2093  GT10_RXPD_IN => AMC_pd(10),
2094  GT10_TXPD_IN => AMC_pd(10),
2095  --------------------- RX Initialization and Reset Ports --------------------
2096  GT10_EYESCANRESET_IN => '0',
2097  GT10_RXUSERRDY_IN => '0',
2098  -------------------------- RX Margin Analysis Ports ------------------------
2099  GT10_EYESCANDATAERROR_OUT => open,
2100  GT10_EYESCANTRIGGER_IN => '0',
2101  ------------------- Receive Ports - Clock Correction Ports -----------------
2102  GT10_RXCLKCORCNT_OUT => open,
2103  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
2104  GT10_RXUSRCLK_IN => UsrClk,
2105  GT10_RXUSRCLK2_IN => UsrClk,
2106  ------------------ Receive Ports - FPGA RX interface Ports -----------------
2107  GT10_RXDATA_OUT => RXDATA_i(10),
2108  ------------------- Receive Ports - Pattern Checker Ports ------------------
2109  GT10_RXPRBSERR_OUT => rxprbserr(10),
2110  GT10_RXPRBSSEL_IN => rxprbssel(10),
2111  ------------------- Receive Ports - Pattern Checker ports ------------------
2112  GT10_RXPRBSCNTRESET_IN => '0',
2113  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
2114  GT10_RXDISPERR_OUT => open,
2115  GT10_RXNOTINTABLE_OUT => RXNOTINTABLE_i(10),
2116  --------------------------- Receive Ports - RX AFE -------------------------
2117  GT10_GTXRXP_IN => RXP(10),
2118  ------------------------ Receive Ports - RX AFE Ports ----------------------
2119  GT10_GTXRXN_IN => RXN(10),
2120  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
2121  GT10_RXMCOMMAALIGNEN_IN => rxcommaalignen(10),
2122  GT10_RXPCOMMAALIGNEN_IN => rxcommaalignen(10),
2123  --------------------- Receive Ports - RX Equalizer Ports -------------------
2124  GT10_RXDFELPMRESET_IN => '0',
2125  GT10_RXMONITOROUT_OUT => open,
2126  GT10_RXMONITORSEL_IN => "00",
2127  ------------- Receive Ports - RX Initialization and Reset Ports ------------
2128  GT10_GTRXRESET_IN => qpll_lock_n(2),
2129  GT10_RXPMARESET_IN => '0',
2130  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
2131  GT10_RXCHARISCOMMA_OUT => rxchariscomma_i(10),
2132  GT10_RXCHARISK_OUT => rxcharisk_i(10),
2133  -------------- Receive Ports -RX Initialization and Reset Ports ------------
2134  GT10_RXRESETDONE_OUT => rxresetdone_i(10),
2135  --------------------- TX Initialization and Reset Ports --------------------
2136  GT10_GTTXRESET_IN => qpll_lock_n(2),
2137  GT10_TXUSERRDY_IN => '0',
2138  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
2139  GT10_TXUSRCLK_IN => UsrClk,
2140  GT10_TXUSRCLK2_IN => UsrClk,
2141  --------------- Transmit Ports - TX Configurable Driver Ports --------------
2142  GT10_TXDIFFCTRL_IN => txdiffctrl(10),
2143  ------------------ Transmit Ports - TX Data Path interface -----------------
2144  GT10_TXDATA_IN => TXDATA(10),
2145  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
2146  GT10_GTXTXN_OUT => TXN(10),
2147  GT10_GTXTXP_OUT => TXP(10),
2148  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
2149  GT10_TXOUTCLK_OUT => txoutclk(10),
2150  GT10_TXOUTCLKFABRIC_OUT => open,
2151  GT10_TXOUTCLKPCS_OUT => open,
2152  --------------------- Transmit Ports - TX Gearbox Ports --------------------
2153  GT10_TXCHARISK_IN => txcharisk(10),
2154  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
2155  GT10_TXRESETDONE_OUT => txresetdone(10),
2156  ------------------ Transmit Ports - pattern Generator Ports ----------------
2157  GT10_TXPRBSSEL_IN => txprbssel(10),
2158 
2159  --GT11 (X0Y11)
2160  --____________________________CHANNEL PORTS________________________________
2161  ---------------------------- Channel - DRP Ports --------------------------
2162  GT11_DRPADDR_IN => (others => '0'),
2163  GT11_DRPCLK_IN => DRPclk,
2164  GT11_DRPDI_IN => (others => '0'),
2165  GT11_DRPDO_OUT => open,
2166  GT11_DRPEN_IN => '0',
2167  GT11_DRPRDY_OUT => open,
2168  GT11_DRPWE_IN => '0',
2169  --------------------------- Digital Monitor Ports --------------------------
2170  GT11_DMONITOROUT_OUT => open,
2171  ------------------------------- Loopback Ports -----------------------------
2172  GT11_LOOPBACK_IN => loopback(11),
2173  ------------------------------ Power-Down Ports ----------------------------
2174  GT11_RXPD_IN => AMC_pd(11),
2175  GT11_TXPD_IN => AMC_pd(11),
2176  --------------------- RX Initialization and Reset Ports --------------------
2177  GT11_EYESCANRESET_IN => '0',
2178  GT11_RXUSERRDY_IN => '0',
2179  -------------------------- RX Margin Analysis Ports ------------------------
2180  GT11_EYESCANDATAERROR_OUT => open,
2181  GT11_EYESCANTRIGGER_IN => '0',
2182  ------------------- Receive Ports - Clock Correction Ports -----------------
2183  GT11_RXCLKCORCNT_OUT => open,
2184  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
2185  GT11_RXUSRCLK_IN => UsrClk,
2186  GT11_RXUSRCLK2_IN => UsrClk,
2187  ------------------ Receive Ports - FPGA RX interface Ports -----------------
2188  GT11_RXDATA_OUT => RXDATA_i(11),
2189  ------------------- Receive Ports - Pattern Checker Ports ------------------
2190  GT11_RXPRBSERR_OUT => rxprbserr(11),
2191  GT11_RXPRBSSEL_IN => rxprbssel(11),
2192  ------------------- Receive Ports - Pattern Checker ports ------------------
2193  GT11_RXPRBSCNTRESET_IN => '0',
2194  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
2195  GT11_RXDISPERR_OUT => open,
2196  GT11_RXNOTINTABLE_OUT => RXNOTINTABLE_i(11),
2197  --------------------------- Receive Ports - RX AFE -------------------------
2198  GT11_GTXRXP_IN => RXP(11),
2199  ------------------------ Receive Ports - RX AFE Ports ----------------------
2200  GT11_GTXRXN_IN => RXN(11),
2201  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
2202  GT11_RXMCOMMAALIGNEN_IN => rxcommaalignen(11),
2203  GT11_RXPCOMMAALIGNEN_IN => rxcommaalignen(11),
2204  --------------------- Receive Ports - RX Equalizer Ports -------------------
2205  GT11_RXDFELPMRESET_IN => '0',
2206  GT11_RXMONITOROUT_OUT => open,
2207  GT11_RXMONITORSEL_IN => "00",
2208  ------------- Receive Ports - RX Initialization and Reset Ports ------------
2209  GT11_GTRXRESET_IN => qpll_lock_n(2),
2210  GT11_RXPMARESET_IN => '0',
2211  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
2212  GT11_RXCHARISCOMMA_OUT => rxchariscomma_i(11),
2213  GT11_RXCHARISK_OUT => rxcharisk_i(11),
2214  -------------- Receive Ports -RX Initialization and Reset Ports ------------
2215  GT11_RXRESETDONE_OUT => rxresetdone_i(11),
2216  --------------------- TX Initialization and Reset Ports --------------------
2217  GT11_GTTXRESET_IN => qpll_lock_n(2),
2218  GT11_TXUSERRDY_IN => '0',
2219  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
2220  GT11_TXUSRCLK_IN => UsrClk,
2221  GT11_TXUSRCLK2_IN => UsrClk,
2222  --------------- Transmit Ports - TX Configurable Driver Ports --------------
2223  GT11_TXDIFFCTRL_IN => txdiffctrl(11),
2224  ------------------ Transmit Ports - TX Data Path interface -----------------
2225  GT11_TXDATA_IN => TXDATA(11),
2226  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
2227  GT11_GTXTXN_OUT => TXN(11),
2228  GT11_GTXTXP_OUT => TXP(11),
2229  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
2230  GT11_TXOUTCLK_OUT => txoutclk(11),
2231  GT11_TXOUTCLKFABRIC_OUT => open,
2232  GT11_TXOUTCLKPCS_OUT => open,
2233  --------------------- Transmit Ports - TX Gearbox Ports --------------------
2234  GT11_TXCHARISK_IN => txcharisk(11),
2235  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
2236  GT11_TXRESETDONE_OUT => txresetdone(11),
2237  ------------------ Transmit Ports - pattern Generator Ports ----------------
2238  GT11_TXPRBSSEL_IN => txprbssel(11),
2239 
2240 
2241  --____________________________COMMON PORTS________________________________
2242  GT0_QPLLLOCK_IN => qpll_lock_i(0),
2243  GT0_QPLLREFCLKLOST_IN => GT0_QPLLREFCLKLOST,
2244  GT0_QPLLRESET_OUT => GT0_QPLLRESET_OUT,
2245  GT0_QPLLOUTCLK_IN => GT0_QPLLOUTCLK,
2246  GT0_QPLLOUTREFCLK_IN => GT0_QPLLOUTREFCLK,
2247  --____________________________COMMON PORTS________________________________
2248  GT1_QPLLLOCK_IN => qpll_lock_i(1),
2249  GT1_QPLLREFCLKLOST_IN => GT1_QPLLREFCLKLOST,
2250  GT1_QPLLRESET_OUT => GT1_QPLLRESET_OUT,
2251  GT1_QPLLOUTCLK_IN => GT1_QPLLOUTCLK,
2252  GT1_QPLLOUTREFCLK_IN => GT1_QPLLOUTREFCLK,
2253  --____________________________COMMON PORTS________________________________
2254  GT2_QPLLLOCK_IN => qpll_lock_i(2),
2255  GT2_QPLLREFCLKLOST_IN => GT2_QPLLREFCLKLOST,
2256  GT2_QPLLRESET_OUT => GT2_QPLLRESET_OUT,
2257  GT2_QPLLOUTCLK_IN => GT2_QPLLOUTCLK,
2258  GT2_QPLLOUTREFCLK_IN => GT2_QPLLOUTREFCLK
2259 
2260 );
2261 i_common0 : amc_gtx5Gpd_common
2262  port map
2263  (
2264  GTREFCLK0_IN => AMC_REFCLK,
2265  QPLLLOCK_OUT => qpll_lock_i(0),
2266  QPLLLOCKDETCLK_IN => DRPclk,
2267  QPLLOUTCLK_OUT => GT0_QPLLOUTCLK,
2268  QPLLOUTREFCLK_OUT => GT0_QPLLOUTREFCLK,
2269  QPLLREFCLKLOST_OUT => GT0_QPLLREFCLKLOST,
2270  QPLLRESET_IN => GT0_QPLLRESET_IN
2271 
2272 );
2273 GT0_QPLLRESET_IN <= GT0_QPLLRESET_OUT or COMMON_RESET;
2274 i_common1 : amc_gtx5Gpd_common
2275  port map
2276  (
2277  GTREFCLK0_IN => AMC_REFCLK,
2278  QPLLLOCK_OUT => qpll_lock_i(1),
2279  QPLLLOCKDETCLK_IN => DRPclk,
2280  QPLLOUTCLK_OUT => GT1_QPLLOUTCLK,
2281  QPLLOUTREFCLK_OUT => GT1_QPLLOUTREFCLK,
2282  QPLLREFCLKLOST_OUT => GT1_QPLLREFCLKLOST,
2283  QPLLRESET_IN => GT1_QPLLRESET_IN
2284 
2285 );
2286 GT1_QPLLRESET_IN <= GT1_QPLLRESET_OUT or COMMON_RESET;
2287 i_common2 : amc_gtx5Gpd_common
2288  port map
2289  (
2290  GTREFCLK0_IN => AMC_REFCLK,
2291  QPLLLOCK_OUT => qpll_lock_i(2),
2292  QPLLLOCKDETCLK_IN => DRPclk,
2293  QPLLOUTCLK_OUT => GT2_QPLLOUTCLK,
2294  QPLLOUTREFCLK_OUT => GT2_QPLLOUTREFCLK,
2295  QPLLREFCLKLOST_OUT => GT2_QPLLREFCLKLOST,
2296  QPLLRESET_IN => GT2_QPLLRESET_IN
2297 
2298 );
2299 GT2_QPLLRESET_IN <= GT2_QPLLRESET_OUT or COMMON_RESET;
2300 
2301 i_common_reset : amc_gtx5Gpd_common_reset
2302  port map
2303  (
2304  STABLE_CLOCK => DRPclk, --Stable Clock, either a stable clock from the PCB
2305  SOFT_RESET => SOFT_RESET, --User Reset, can be pulled any time
2306  COMMON_RESET => COMMON_RESET --Reset QPLL
2307  );
2308 end Behavioral;
2309 
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