AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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AMC_DATA_FIFO.vhd
1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 13:53:06 04/29/2014
6 -- Design Name:
7 -- Module Name: AMC_DATA_FIFO - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 library IEEE;
21 use IEEE.STD_LOGIC_1164.ALL;
22 use IEEE.STD_LOGIC_ARITH.ALL;
23 use IEEE.STD_LOGIC_UNSIGNED.ALL;
24 use IEEE.std_logic_misc.all;
25 
26 -- Uncomment the following library declaration if using
27 -- arithmetic functions with Signed or Unsigned values
28 --use IEEE.NUMERIC_STD.ALL;
29 
30 -- Uncomment the following library declaration if instantiating
31 -- any Xilinx primitives in this code.
32 library UNISIM;
33 use UNISIM.VComponents.all;
34 Library UNIMACRO;
35 use UNIMACRO.vcomponents.all;
36 
37 entity AMC_DATA_FIFO is
38  Port ( wclk : in STD_LOGIC;
39  rclk : in STD_LOGIC;
40  reset : in STD_LOGIC;
41  fifo_en : in STD_LOGIC;
42  we : in STD_LOGIC;
43  re : in STD_LOGIC;
44  Di : in STD_LOGIC_VECTOR (63 downto 0);
45  Do : out STD_LOGIC_VECTOR (63 downto 0);
46  WRERR_OUT : out STD_LOGIC_VECTOR (7 downto 0);
47  RDERR_OUT : out STD_LOGIC_VECTOR (7 downto 0);
48  full : out STD_LOGIC
49  );
50 end AMC_DATA_FIFO;
51 
52 architecture Behavioral of AMC_DATA_FIFO is
53 type array14x12 is array(0 to 13) of std_logic_vector(11 downto 0);
54 signal RDCOUNT : array14x12;
55 signal WRCOUNT : array14x12;
56 signal RDCOUNT14 : std_logic_vector(12 downto 0) := (others => '0');
57 signal WRCOUNT14 : std_logic_vector(12 downto 0) := (others => '0');
58 signal FIFO_full : std_logic_vector(13 downto 0) := (others => '0');
59 signal FIFO_empty : std_logic_vector(13 downto 0) := (others => '0');
60 signal FIFO_RdEn : std_logic_vector(6 downto 0) := (others => '0');
61 signal RDERR : std_logic_vector(7 downto 0) := (others => '0');
62 signal WRERR : std_logic_vector(7 downto 0) := (others => '0');
63 signal FIFO_Do : std_logic_vector(62 downto 0) := (others => '0');
64 begin
65 full <= FIFO_full(0);
66 process(wclk,reset)
67 begin
68  if(reset = '1')then
69  WRERR_OUT <= (others => '0');
70  elsif(wclk'event and wclk = '1')then
71  for i in 0 to 7 loop
72  if(WRERR(i) = '1')then
73  WRERR_OUT(i) <= '1';
74  end if;
75  end loop;
76  end if;
77 end process;
78 process(rclk,reset)
79 begin
80  if(reset = '1')then
81  RDERR_OUT <= (others => '0');
82  elsif(rclk'event and rclk = '1')then
83  for i in 0 to 6 loop
84  if(RDERR(i) = '1')then
85  RDERR_OUT(i) <= '1';
86  end if;
87  end loop;
88  end if;
89 end process;
90 g_FIFO: for i in 0 to 6 generate
91  i_FIFO_i : FIFO_DUALCLOCK_MACRO
92  generic map (
93  DEVICE => "7SERIES", -- Target Device: "VIRTEX5", "VIRTEX6", "7SERIES"
94  ALMOST_FULL_OFFSET => X"0008", -- Sets almost full threshold
95  ALMOST_EMPTY_OFFSET => X"0080", -- Sets the almost empty threshold
96  DATA_WIDTH => 9, -- Valid values are 1-72 (37-72 only valid when FIFO_SIZE="36Kb")
97  FIFO_SIZE => "36Kb", -- Target BRAM, "18Kb" or "36Kb"
98  FIRST_WORD_FALL_THROUGH => TRUE) -- Sets the FIFO FWFT to TRUE or FALSE
99  port map (
100  ALMOSTEMPTY => open, -- 1-bit output almost empty
101  ALMOSTFULL => FIFO_full(i), -- 1-bit output almost full
102  DO => FIFO_Do(i*9+8 downto i*9), -- Output data, width defined by DATA_WIDTH parameter
103  EMPTY => FIFO_empty(i), -- 1-bit output empty
104  FULL => open, -- 1-bit output full
105  RDCOUNT => RDCOUNT(i), -- Output read count, width determined by FIFO depth
106  RDERR => open, -- 1-bit output read error
107  WRCOUNT => WRCOUNT(i), -- Output write count, width determined by FIFO depth
108  WRERR => WRERR(i), -- 1-bit output write error
109  DI => Di(i*9+8 downto i*9), -- Input data, width defined by DATA_WIDTH parameter
110  RDCLK => wclk, -- 1-bit input read clock
111  RDEN => FIFO_Rden(i), -- 1-bit input read enable
112  RST => reset, -- 1-bit input reset
113  WRCLK => wclk, -- 1-bit input write clock
114  WREN => we -- 1-bit input write enable
115  );
116  i_FIFO_o : FIFO_DUALCLOCK_MACRO
117  generic map (
118  DEVICE => "7SERIES", -- Target Device: "VIRTEX5", "VIRTEX6", "7SERIES"
119  ALMOST_FULL_OFFSET => X"0004", -- Sets almost full threshold
120  ALMOST_EMPTY_OFFSET => X"0006", -- Sets the almost empty threshold
121  DATA_WIDTH => 9, -- Valid values are 1-72 (37-72 only valid when FIFO_SIZE="36Kb")
122  FIFO_SIZE => "36Kb", -- Target BRAM, "18Kb" or "36Kb"
123  FIRST_WORD_FALL_THROUGH => TRUE) -- Sets the FIFO FWFT to TRUE or FALSE
124  port map (
125  ALMOSTEMPTY => FIFO_empty(i+7), -- 1-bit output almost empty
126  ALMOSTFULL => open, -- 1-bit output almost full
127  DO => Do(i*9+8 downto i*9), -- Output data, width defined by DATA_WIDTH parameter
128  EMPTY => open, -- 1-bit output empty
129  FULL => FIFO_full(i+7), -- 1-bit output full
130  RDCOUNT => RDCOUNT(i+7), -- Output read count, width determined by FIFO depth
131  RDERR => RDERR(i), -- 1-bit output read error
132  WRCOUNT => WRCOUNT(i+7), -- Output write count, width determined by FIFO depth
133  WRERR => open, -- 1-bit output write error
134  DI => FIFO_Do(i*9+8 downto i*9), -- Input data, width defined by DATA_WIDTH parameter
135  RDCLK => rclk, -- 1-bit input read clock
136  RDEN => re, -- 1-bit input read enable
137  RST => reset, -- 1-bit input reset
138  WRCLK => wclk, -- 1-bit input write clock
139  WREN => FIFO_Rden(i) -- 1-bit input write enable
140  );
141  FIFO_Rden(i) <= fifo_en and not FIFO_full(i+7) and not FIFO_empty(i);
142 end generate;
143 i_FIFO63 : FIFO_DUALCLOCK_MACRO
144  generic map (
145  DEVICE => "7SERIES", -- Target Device: "VIRTEX5", "VIRTEX6", "7SERIES"
146  ALMOST_FULL_OFFSET => X"0004", -- Sets almost full threshold
147  ALMOST_EMPTY_OFFSET => X"0006", -- Sets the almost empty threshold
148  DATA_WIDTH => 1, -- Valid values are 1-72 (37-72 only valid when FIFO_SIZE="36Kb")
149  FIFO_SIZE => "36Kb", -- Target BRAM, "18Kb" or "36Kb" -- 18Kb max depth is 4K, need 36Kb to get 8K depth
150  FIRST_WORD_FALL_THROUGH => TRUE) -- Sets the FIFO FWFT to TRUE or FALSE
151  port map (
152  ALMOSTEMPTY => open, -- 1-bit output almost empty
153  ALMOSTFULL => open, -- 1-bit output almost full
154  DO => Do(63 downto 63), -- Output data, width defined by DATA_WIDTH parameter
155  EMPTY => open, -- 1-bit output empty
156  FULL => open, -- 1-bit output full
157  RDCOUNT => RDCOUNT14, -- Output read count, width determined by FIFO depth
158  RDERR => RDERR(7), -- 1-bit output read error
159  WRCOUNT => WRCOUNT14, -- Output write count, width determined by FIFO depth
160  WRERR => WRERR(7), -- 1-bit output write error
161  DI => Di(63 downto 63), -- Input data, width defined by DATA_WIDTH parameter
162  RDCLK => rclk, -- 1-bit input read clock
163  RDEN => re, -- 1-bit input read enable
164  RST => reset, -- 1-bit input reset
165  WRCLK => wclk, -- 1-bit input write clock
166  WREN => we -- 1-bit input write enable
167  );
168 end Behavioral;
169 
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