AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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AMC13_T1.vhd
1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 14:49:29 05/12/2010
6 -- Design Name:
7 -- Module Name: DTC_T2 - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 library IEEE;
21 use IEEE.STD_LOGIC_1164.ALL;
22 use IEEE.STD_LOGIC_ARITH.ALL;
23 use IEEE.STD_LOGIC_UNSIGNED.ALL;
24 use IEEE.std_logic_misc.all;
25 use work.ipbus.ALL;
26 use work.amc13_pack.all;
27 
28 -- Uncomment the following library declaration if using
29 -- arithmetic functions with Signed or Unsigned values
30 -- use IEEE.NUMERIC_STD.ALL;
31 
32 -- Uncomment the following library declaration if instantiating
33 -- any Xilinx primitives in this code.
34 library UNISIM;
35 use UNISIM.VComponents.all;
36 Library UNIMACRO;
37 use UNIMACRO.vcomponents.all;
38 
39 entity AMC13_T1 is
40  Port (
41  VAUXP : in STD_LOGIC_VECTOR(12 downto 0);
42  VAUXN : in STD_LOGIC_VECTOR(12 downto 0);
43 -- I2C interface
44  CLK_SCL : out STD_LOGIC;
45  CLK_SDA : inout STD_LOGIC;
46  SFP_SCL : out STD_LOGIC_VECTOR(3 downto 0);
47  SFP_SDA : inout STD_LOGIC_VECTOR(3 downto 0);
48 -- SFP slow control
49  SFP_LOS : in STD_LOGIC_VECTOR(2 downto 0);
50  SFP_ABS : in STD_LOGIC_VECTOR(3 downto 0);
51  TxFault : in STD_LOGIC_VECTOR(3 downto 0);
52  TxDisable : out STD_LOGIC_VECTOR(3 downto 0);
53 -- RATE : out STD_LOGIC_VECTOR(3 downto 0);
54 -- CDR signals
55  DIV4 : out STD_LOGIC;
56  DIV_nRST : out STD_LOGIC;
57  CDRclk_p : in STD_LOGIC;
58  CDRclk_n : in STD_LOGIC;
59  CDRdata_p : in STD_LOGIC;
60  CDRdata_n : in STD_LOGIC;
61  TTCdata_p : out STD_LOGIC;
62  TTCdata_n : out STD_LOGIC;
63  TTCclk_p : in STD_LOGIC;
64  TTCclk_n : in STD_LOGIC;
65  TTC_LOS : in STD_LOGIC;
66  TTC_LOL : in STD_LOGIC;
67  TTS_out_p : out STD_LOGIC;
68  TTS_out_n : out STD_LOGIC;
69 -- SPI interface
70  SPI_SCK : in STD_LOGIC;
71  SPI_CS_b : in STD_LOGIC;
72  SPI_MOSI : in STD_LOGIC;
73  SPI_MISO : out STD_LOGIC;
74 -- DDR3 pins
75  sys_clk_p : in STD_LOGIC;
76  sys_clk_n : in STD_LOGIC;
77  ddr3_dq : inout STD_LOGIC_VECTOR(31 downto 0);
78  ddr3_addr : out STD_LOGIC_VECTOR(13 downto 0);
79  ddr3_ba : out STD_LOGIC_VECTOR (2 downto 0);
80  ddr3_dm : out STD_LOGIC_VECTOR (3 downto 0);
81  ddr3_dqs_p : inout STD_LOGIC_VECTOR(3 downto 0);
82  ddr3_dqs_n : inout STD_LOGIC_VECTOR(3 downto 0);
83  ddr3_ras_n : out STD_LOGIC;
84  ddr3_cas_n : out STD_LOGIC;
85  ddr3_we_n : out STD_LOGIC;
86  ddr3_reset_n : out STD_LOGIC;
87  ddr3_cke : out STD_LOGIC_vector(0 to 0);
88  ddr3_odt : out STD_LOGIC_vector(0 to 0);
89  ddr3_ck_p : out STD_LOGIC_vector(0 to 0);
90  ddr3_ck_n : out STD_LOGIC_vector(0 to 0);
91  SFP0_RXN : in STD_LOGIC;
92  SFP0_RXP : in STD_LOGIC;
93  SFP1_RXN : in STD_LOGIC;
94  SFP1_RXP : in STD_LOGIC;
95  SFP2_RXN : in STD_LOGIC;
96  SFP2_RXP : in STD_LOGIC;
97  SFP0_TXN : out STD_LOGIC;
98  SFP0_TXP : out STD_LOGIC;
99  SFP1_TXN : out STD_LOGIC;
100  SFP1_TXP : out STD_LOGIC;
101  SFP2_TXN : out STD_LOGIC;
102  SFP2_TXP : out STD_LOGIC;
103  CDR_REFCLK_N : in STD_LOGIC;
104  CDR_REFCLK_P : in STD_LOGIC;
105  SFP_REFCLK_N : in STD_LOGIC;
106  SFP_REFCLK_P : in STD_LOGIC;
107  AMC_REFCLK_N : in STD_LOGIC;
108  AMC_REFCLK_P : in STD_LOGIC;
109  AMC_RXN : in STD_LOGIC_VECTOR(12 downto 1);
110  AMC_RXP : in STD_LOGIC_VECTOR(12 downto 1);
111  AMC_TXN : out STD_LOGIC_VECTOR(12 downto 1);
112  AMC_TXP : out STD_LOGIC_VECTOR(12 downto 1);
113 -- signal to/from DTC_T2
114  S6LINK_RXN : in STD_LOGIC;
115  S6LINK_RXP : in STD_LOGIC;
116  S6LINK_TXN : out STD_LOGIC;
117  S6LINK_TXP : out STD_LOGIC;
118  S2V_p : in STD_LOGIC;
119  S2V_n : in STD_LOGIC;
120 -- V2S_p : out STD_LOGIC;
121 -- V2S_n : out STD_LOGIC;
122  GbE_REFCLK_N : in STD_LOGIC;
123  GbE_REFCLK_P : in STD_LOGIC);
124 end AMC13_T1;
125 
126 architecture Behavioral of AMC13_T1 is
127 COMPONENT HCAL_trig
128 PORT(
129  TTC_clk : IN std_logic;
130  DRPCLK : IN std_logic;
131  reset : IN std_logic;
132  SFP_ABS : in STD_LOGIC;
133  BC0 : in STD_LOGIC;
134  BC0_dl : out STD_LOGIC;
135  triggerOut : out STD_LOGIC;
136  Trigdata : in array12x8;
137  TTC_lock : in STD_LOGIC;
138  AMC_en : in STD_LOGIC_VECTOR(11 downto 0);
139  BC0_lock : in STD_LOGIC_VECTOR(11 downto 0);
140  BX_offset2SC : out STD_LOGIC_VECTOR(11 downto 0);
141  ipb_clk : IN std_logic;
142  ipb_write : IN std_logic;
143  ipb_strobe : IN std_logic;
144  ipb_addr : IN std_logic_vector(31 downto 0);
145  ipb_wdata : IN std_logic_vector(31 downto 0);
146  GTX_REFCLKp : IN std_logic;
147  GTX_REFCLKn : IN std_logic;
148  GTX_RXp : IN std_logic;
149  GTX_RXn : IN std_logic;
150  ipb_rdata : OUT std_logic_vector(31 downto 0);
151  GTX_TXp : OUT std_logic;
152  GTX_TXn : OUT std_logic
153  );
154 END COMPONENT;
155 COMPONENT TTS_if
156  PORT(
157  sysclk : IN std_logic;
158  TTS_clk : IN std_logic;
159  reset : IN std_logic;
160  local_TTC : in STD_LOGIC;
161  TTS : IN std_logic_vector(3 downto 0);
162  TTS_out_p : OUT std_logic;
163  TTS_out_n : OUT std_logic
164  );
165 END COMPONENT;
166 COMPONENT ttc_if
167  PORT(
168  clk : IN std_logic;
169  refclk : IN std_logic;
170  reset : IN std_logic;
171  rst_PLL : IN std_logic;
172  run : IN std_logic;
173  IgnoreDAQ : IN std_logic;
174  DB_cmd_in : IN std_logic;
175  DB_cmd_Out : OUT std_logic;
176  sys_lock : IN std_logic;
177  local_TTC : IN std_logic;
178  local_TTCcmd : IN std_logic;
179  single_TTCcmd : in STD_LOGIC;
180  CDRclk_p : IN std_logic;
181  CDRclk_n : IN std_logic;
182  CDRdata_p : IN std_logic;
183  CDRdata_n : IN std_logic;
184  TTC_LOS : IN std_logic;
185  TTC_LOL : IN std_logic;
186  BCN_off : IN std_logic_vector(12 downto 0);
187  OC_off : IN std_logic_vector(3 downto 0);
188  en_cal_win : IN std_logic;
189  trig_BX : IN std_logic_vector(12 downto 0);
190  cal_win_high : IN std_logic_vector(11 downto 0);
191  cal_win_low : IN std_logic_vector(11 downto 0);
192  en_localL1A : IN std_logic;
193  LocalL1A_cfg : IN std_logic_vector(31 downto 0);
194  localL1A_s : IN std_logic;
195  localL1A_r : IN std_logic;
196  T3_trigger : IN std_logic;
197  HCAL_trigger : IN std_logic;
198  EvnRSt_l : IN std_logic;
199  OcnRSt_l : IN std_logic;
200  ovfl_warning : IN std_logic;
201  ipb_clk : IN std_logic;
202  ipb_write : IN std_logic;
203  ipb_strobe : IN std_logic;
204  ipb_addr : IN std_logic_vector(31 downto 0);
205  ipb_wdata : IN std_logic_vector(31 downto 0);
206  en_brcst : IN std_logic;
207  state : IN std_logic_vector(3 downto 0);
208  evn_fifo_full : IN std_logic;
209  BC0 : OUT std_logic;
210  TTC_strobe : OUT std_logic;
211  TTS_clk : OUT std_logic;
212  DIV4 : OUT std_logic;
213  DIV_nRST : OUT std_logic;
214  CDRclk_out : OUT std_logic;
215  TTCdata_p : OUT std_logic;
216  TTCdata_n : OUT std_logic;
217  CalType : OUT std_logic_vector(3 downto 0);
218  TTC_Brcst : OUT std_logic_vector(3 downto 0);
219  localL1A_periodic : OUT std_logic;
220  ipb_rdata : OUT std_logic_vector(31 downto 0);
221  ttc_start : OUT std_logic;
222  ttc_stop : OUT std_logic;
223  ttc_soft_reset : OUT std_logic;
224  ttc_ready : OUT std_logic;
225  ttc_serr : OUT std_logic;
226  ttc_derr : OUT std_logic;
227  ttc_bcnt_err : OUT std_logic;
228  rate_OFW : OUT std_logic;
229  sync_lost : OUT std_logic;
230  inc_oc : OUT std_logic;
231  inc_l1ac : OUT std_logic;
232  inc_bcnterr : OUT std_logic;
233  inc_serr : OUT std_logic;
234  inc_derr : OUT std_logic;
235  ttc_evcnt_reset : OUT std_logic;
236  event_number_avl : OUT std_logic;
237  event_number : OUT std_logic_vector(59 downto 0)
238  );
239 END COMPONENT;
240 COMPONENT AMC_if
241  Generic (simulation : boolean := false);
242  PORT(
243  sysclk : IN std_logic;
244  ipb_clk : IN std_logic;
245  clk125 : IN std_logic;
246  DRPclk : IN std_logic;
247  GTXreset : IN std_logic;
248  reset : IN std_logic;
249  DB_cmd : IN std_logic;
250  resetCntr : IN std_logic;
251  ReSync : IN std_logic;
252  AllEventBuilt : OUT std_logic;
253  run : IN std_logic;
254  en_inject_err : in STD_LOGIC;
255  Dis_pd : in STD_LOGIC;
256  enSFP : IN std_logic_vector(3 downto 0);
257  en_localL1A : IN std_logic;
258  test : IN std_logic;
259  NoReSyncFake : IN std_logic;
260  WaitMonBuf : IN std_logic;
261  fake_length : IN std_logic_vector(19 downto 0);
262  T1_version : IN std_logic_vector(7 downto 0);
263  Source_ID : IN array3x12;
264  AMC_en : IN std_logic_vector(11 downto 0);
265  TTS_disable : IN std_logic_vector(11 downto 0);
266  AMC_REFCLK_P : IN std_logic;
267  AMC_REFCLK_N : IN std_logic;
268  AMC_RXN : IN std_logic_vector(12 downto 1);
269  AMC_RXP : IN std_logic_vector(12 downto 1);
270  evt_data_re : IN std_logic_vector(2 downto 0);
271  evt_buf_full : IN std_logic_vector(2 downto 0);
272  ddr_pa : IN std_logic_vector(9 downto 0);
273  MonBuf_empty : IN std_logic;
274  mon_buf_avl : IN std_logic;
275  TCPbuf_avl : IN std_logic;
276  ipb_write : IN std_logic;
277  ipb_strobe : IN std_logic;
278  ipb_addr : IN std_logic_vector(31 downto 0);
279  ipb_wdata : IN std_logic_vector(31 downto 0);
280  TTC_clk : IN std_logic;
281  TTC_LOS : IN std_logic;
282  BC0 : IN std_logic;
283  ttc_evcnt_reset : IN std_logic;
284  event_number_avl : IN std_logic;
285  event_number : IN std_logic_vector(59 downto 0);
286  AMC_Ready : OUT std_logic_vector(11 downto 0);
287  TTC_lock : OUT std_logic;
288  BC0_lock : OUT std_logic_vector(11 downto 0);
289  AMC_TXN : OUT std_logic_vector(12 downto 1);
290  AMC_TXP : OUT std_logic_vector(12 downto 1);
291  AMC_status : OUT std_logic_vector(31 downto 0);
292  evt_data : OUT array3x67;
293  evt_data_we : OUT std_logic_vector(2 downto 0);
294  evt_data_rdy : OUT std_logic_vector(2 downto 0);
295  mon_evt_wc : OUT std_logic_vector(47 downto 0);
296  mon_ctrl : OUT std_logic_vector(31 downto 0);
297  buf_rqst : OUT std_logic_vector(3 downto 0);
298  ipb_rdata : OUT std_logic_vector(31 downto 0);
299  ipb_ack : OUT std_logic;
300  evn_buf_full : OUT std_logic;
301  ovfl_warning : OUT std_logic;
302  TrigData : OUT array12x8;
303  TTS_RQST : OUT std_logic_vector(2 downto 0);
304  TTS_coded : OUT std_logic_vector(4 downto 0)
305  );
306 END COMPONENT;
307 COMPONENT I2C
308  PORT(
309  clk : IN std_logic;
310  ipb_clk : IN std_logic;
311  reset : IN std_logic;
312  addr : IN std_logic_vector(31 downto 0);
313  SFP_ABS : IN std_logic_vector(3 downto 0);
314  SFP_LOS : IN std_logic_vector(2 downto 0);
315  CLK_SDA : INOUT std_logic;
316  SFP_SDA : INOUT std_logic_vector(3 downto 0);
317  rdata : OUT std_logic_vector(31 downto 0);
318  CLK_rdy : OUT std_logic;
319  CLK_SCL : OUT std_logic;
320  SFP_SCL : OUT std_logic_vector(3 downto 0)
321  );
322 END COMPONENT;
323 COMPONENT SPI_if
324  PORT(
325  SCK : IN std_logic;
326  CSn : IN std_logic;
327  MOSI : IN std_logic;
328  SN : IN std_logic_vector(8 downto 0);
329  OT : IN std_logic;
330  IsT1 : IN std_logic;
331  SPI_rdata : IN std_logic_vector(7 downto 0);
332  MISO : OUT std_logic;
333  SPI_we : OUT std_logic;
334  en_RARP : out STD_LOGIC;
335  newIPADDR : OUT std_logic;
336  IPADDR : OUT std_logic_vector(31 downto 0);
337  SPI_wdata : OUT std_logic_vector(7 downto 0);
338  SPI_addr : OUT std_logic_vector(7 downto 0)
339  );
340 END COMPONENT;
341 COMPONENT ddr_if
342  port(
343  clk_ref : in std_logic;
344  mem_clk_p : in std_logic;
345  mem_clk_n : in std_logic;
346  mem_rst : in std_logic;
347  sysclk : in std_logic;
348  TCPclk : in std_logic;
349  reset : in std_logic;
350  resetsys : in std_logic;
351  run : in std_logic;
352  mem_test : in std_logic_VECTOR(1 downto 0);
353  EventData : in array3X67;
354  EventData_we : in std_logic_VECTOR(2 downto 0);
355  wport_rdy : out std_logic_VECTOR(2 downto 0);
356  WrtMonBlkDone : OUT std_logic_VECTOR(2 downto 0);
357  WrtMonEvtDone : OUT std_logic_VECTOR(2 downto 0);
358  KiloByte_toggle : OUT std_logic_VECTOR(2 downto 0);
359  EoB_toggle : OUT std_logic_VECTOR(2 downto 0);
360  EventBufAddr : in array3x14;
361  EventBufAddr_we : in std_logic_VECTOR(2 downto 0);
362  EventFIFOfull : out std_logic_VECTOR(2 downto 0);
363  TCP_din : in std_logic_vector(31 downto 0);
364  TCP_channel : in STD_LOGIC_VECTOR (1 downto 0);
365  TCP_we : in STD_LOGIC;
366  TCP_wcount : out STD_LOGIC_VECTOR (2 downto 0);
367  TCP_dout : out STD_LOGIC_VECTOR(31 downto 0); -- TCP data are written in unit of 32-bit words
368  TCP_dout_type : out STD_LOGIC_VECTOR(2 downto 0); -- TCP data destination
369  TCP_raddr : in std_logic_vector(28 downto 0); -- 28-26 encoded request source 25-0 address in 64 bit word
370  TCP_length : in std_logic_vector(12 downto 0); -- in 64 bit word, actual length - 1
371  TCP_dout_valid : out STD_LOGIC;
372  TCP_rrqst : in STD_LOGIC;
373  TCP_rack : out STD_LOGIC;
374  TCP_lastword : out STD_LOGIC;
375  cs_out : out STD_LOGIC_VECTOR(511 downto 0);
376 -- ipbus signals
377  ipb_clk : in STD_LOGIC;
378  ipb_write : in STD_LOGIC;
379  ipb_strobe : in STD_LOGIC;
380  page_addr : in STD_LOGIC_VECTOR(9 downto 0);
381  ipb_addr : in STD_LOGIC_VECTOR(31 downto 0);
382  ipb_wdata : in STD_LOGIC_VECTOR(31 downto 0);
383  ipb_rdata : out STD_LOGIC_VECTOR(31 downto 0);
384  ipb_ack : out STD_LOGIC;
385  mem_stat : out STD_LOGIC_VECTOR (63 downto 0);
386  device_temp : in STD_LOGIC_VECTOR(11 downto 0);
387 -- ddr3 memory pins
388  ddr3_dq : inout STD_LOGIC_VECTOR (31 downto 0);
389  ddr3_dm : out STD_LOGIC_VECTOR (3 downto 0);
390  ddr3_addr : out STD_LOGIC_VECTOR (13 downto 0);
391  ddr3_ba : out STD_LOGIC_VECTOR (2 downto 0);
392  ddr3_dqs_p : inout STD_LOGIC_VECTOR (3 downto 0);
393  ddr3_dqs_n : inout STD_LOGIC_VECTOR (3 downto 0);
394  ddr3_ras_n : out STD_LOGIC;
395  ddr3_cas_n : out STD_LOGIC;
396  ddr3_we_n : out STD_LOGIC;
397  ddr3_reset_n : out STD_LOGIC;
398  ddr3_cke : out STD_LOGIC_vector(0 to 0);
399  ddr3_odt : out STD_LOGIC_vector(0 to 0);
400  ddr3_ck_p : out STD_LOGIC_vector(0 to 0);
401  ddr3_ck_n : out STD_LOGIC_vector(0 to 0)
402  );
403 END COMPONENT;
404 COMPONENT ipbus_if
405  generic(RXPOLARITY : std_logic := '0'; TXPOLARITY : std_logic := '0');
406  port(
407  ipb_clk : IN std_logic;
408  UsRclk : IN std_logic;
409  DRPclk : IN std_logic;
410  got_SN : out std_logic;
411  reset : IN std_logic;
412  GTX_RESET : IN std_logic;
413  GbE_REFCLK : in std_logic;
414  S6LINK_RXN : in std_logic;
415  S6LINK_RXP : in std_logic;
416  S6LINK_TXN : out std_logic;
417  S6LINK_TXP : out std_logic;
418  wr_amc_en : in std_logic;
419  amc_en : in STD_LOGIC_VECTOR(11 downto 0);
420  en_RARP : in std_logic;
421  IPADDR : in STD_LOGIC_VECTOR(31 downto 0);
422  MACADDR : in STD_LOGIC_VECTOR(47 downto 0);
423  ipb_out : out ipb_wbus;
424  ipb_in : in ipb_rbus;
425  SN : out STD_LOGIC_VECTOR(8 downto 0);
426  debug_in : IN std_logic_vector(31 downto 0);
427  debug_out : OUT std_logic_vector(127 downto 0)
428  );
429 end COMPONENT;
430 COMPONENT sysmon_if
431  PORT(
432  DRPclk : IN std_logic;
433  DB_cmd : IN std_logic;
434  SN : IN std_logic_vector(8 downto 0);
435  VAUXN_IN : IN std_logic_vector(12 downto 0);
436  VAUXP_IN : IN std_logic_vector(12 downto 0);
437  addr : IN std_logic_vector(15 downto 0);
438  data : OUT std_logic_vector(31 downto 0);
439  device_temp : OUT std_logic_vector(11 downto 0);
440  ALM : OUT std_logic_vector(7 downto 0);
441  OT : OUT std_logic
442  );
443 END COMPONENT;
444 COMPONENT DAQLSCXG_if
445  PORT(
446  sysclk : IN std_logic;
447  clk125 : IN std_logic;
448  DRPclk : IN std_logic;
449  reset : IN std_logic;
450  daq_reset : IN std_logic;
451  gtx_reset : IN std_logic;
452  rstCntr : IN std_logic;
453  Dis_pd : in STD_LOGIC;
454  test : IN std_logic;
455  DB_cmd : IN std_logic;
456  enSFP : IN std_logic_vector(3 downto 0);
457  SFP_ABS : IN std_logic_vector(2 downto 0);
458  LSC_ID : IN std_logic_vector(15 downto 0);
459  inc_ddr_pa : IN std_logic;
460  evt_data_rdy : IN std_logic_vector(2 downto 0);
461  EventData_in : IN array3x67;
462  EventData_we : IN std_logic_vector(2 downto 0);
463  buf_rqst : IN std_logic_vector(3 downto 0);
464  WaitMonBuf : IN std_logic;
465  WrtMonBlkDone : IN std_logic_vector(2 downto 0);
466  WrtMonEvtDone : IN std_logic_vector(2 downto 0);
467  wport_rdy : IN std_logic_vector(2 downto 0);
468  wport_FIFO_full : IN std_logic_vector(2 downto 0);
469  SFP0_RXN : IN std_logic;
470  SFP0_RXP : IN std_logic;
471  SFP1_RXN : IN std_logic;
472  SFP1_RXP : IN std_logic;
473  SFP2_RXN : IN std_logic;
474  SFP2_RXP : IN std_logic;
475  SFP_REFCLK_P : in std_logic;
476  SFP_REFCLK_N : in std_logic;
477  GbE_REFCLK : in std_logic;
478  ipb_clk : IN std_logic;
479  ipb_write : IN std_logic;
480  ipb_strobe : IN std_logic;
481  ipb_addr : IN std_logic_vector(31 downto 0);
482  ipb_wdata : IN std_logic_vector(31 downto 0);
483  SFP_down : OUT std_logic_vector(2 downto 0);
484  EventData_re : OUT std_logic_vector(2 downto 0);
485  evt_buf_full : OUT std_logic_vector(2 downto 0);
486  MonBufOverWrite : IN std_logic;
487  MonBuf_avl : OUT std_logic;
488  TCPBuf_avl : out STD_LOGIC;
489  MonBuf_empty : OUT std_logic;
490  MonBufOvfl : OUT std_logic;
491  mon_evt_cnt : OUT std_logic_vector(31 downto 0);
492  EventBufAddr_we : OUT std_logic_vector(2 downto 0);
493  EventBufAddr : OUT array3x14;
494  SFP0_TXN : OUT std_logic;
495  SFP0_TXP : OUT std_logic;
496  SFP1_TXN : OUT std_logic;
497  SFP1_TXP : OUT std_logic;
498  SFP2_TXN : OUT std_logic;
499  SFP2_TXP : OUT std_logic;
500  ipb_rdata : OUT std_logic_vector(31 downto 0);
501  ipb_ack : OUT std_logic
502  );
503 END COMPONENT;
504 COMPONENT TCPIP_if
505  generic (simulation : boolean := false; en_KEEPALIVE : std_logic := '1');
506  Port ( sysclk : in STD_LOGIC;
507  DRPclk : in STD_LOGIC;
508  reset : in STD_LOGIC;
509  TCPreset : in STD_LOGIC;
510  rstCntr : in STD_LOGIC;
511  test : in STD_LOGIC;
512  SN : IN std_logic_vector(8 downto 0);
513  Dis_pd : in STD_LOGIC;
514  enSFP : IN std_logic_vector(3 downto 0);
515  SFP_down : OUT std_logic_vector(2 downto 0);
516  inc_ddr_pa : in STD_LOGIC;
517 -- event data in
518  evt_data_rdy : in std_logic_vector(2 downto 0);
519  EventData_in : in array3X67;
520  EventData_we : in std_logic_VECTOR(2 downto 0);
521  EventData_re : out std_logic_VECTOR(2 downto 0); --
522  evt_buf_full : out std_logic_vector(2 downto 0);
523  buf_rqst : in std_logic_vector(3 downto 0);
524  WaitMonBuf : IN std_logic;
525  MonBufOverWrite : in STD_LOGIC;
526  TCPBuf_avl : out STD_LOGIC;
527  MonBuf_avl : out STD_LOGIC;
528  MonBuf_empty : out STD_LOGIC;
529  MonBufOvfl : out STD_LOGIC;
530  mon_evt_cnt : out std_logic_vector(31 downto 0);
531  WrtMonBlkDone : in STD_LOGIC_VECTOR(2 downto 0);
532  WrtMonEvtDone : in STD_LOGIC_VECTOR(2 downto 0);
533  KiloByte_toggle : in STD_LOGIC_VECTOR(2 downto 0);
534  EoB_toggle : in STD_LOGIC_VECTOR(2 downto 0);
535 -- ddr wportA status
536  wport_rdy : in std_logic_vector(2 downto 0);
537  wport_FIFO_full : in std_logic_vector(2 downto 0);
538 -- signal to ddr_if, AMC_if to start moving data
539  EventBufAddr_we : out std_logic_VECTOR(2 downto 0);
540  EventBufAddr : out array3X14;
541 -- ddr wportB signals in sysclk domain
542  TCPclk : out STD_LOGIC;
543  TCP_dout : out std_logic_vector(31 downto 0); -- TCP data are written in unit of 32-bit words
544  TCP_channel : out std_logic_vector(1 downto 0); -- Each entry has four 32bit words, each address saves two entries. Addresses are kept in ddr_wportB
545  TCP_we : out STD_LOGIC;
546  TCP_wcount : in STD_LOGIC_VECTOR (2 downto 0);
547 -- ddr rport signals
548  TCP_raddr : out STD_LOGIC_VECTOR(28 downto 0); -- 28-26 encoded request source 25-0 address in 64 bit word
549  TCP_length : out STD_LOGIC_VECTOR(12 downto 0); -- in 64 bit word, actual length - 1
550  TCP_rrqst : out STD_LOGIC;
551  TCP_rack : in STD_LOGIC;
552  TCP_din : in STD_LOGIC_VECTOR(31 downto 0); -- TCP data are written in unit of 32-bit words
553  TCP_din_type : in STD_LOGIC_VECTOR(2 downto 0); -- TCP data destination
554  TCP_din_valid : in STD_LOGIC;
555  TCP_lastword : in STD_LOGIC;
556 -- SFP ports
557  SFP0_RXN : in STD_LOGIC;
558  SFP0_RXP : in STD_LOGIC;
559  SFP1_RXN : in STD_LOGIC;
560  SFP1_RXP : in STD_LOGIC;
561  SFP2_RXN : in STD_LOGIC;
562  SFP2_RXP : in STD_LOGIC;
563  SFP0_TXN : out STD_LOGIC;
564  SFP0_TXP : out STD_LOGIC;
565  SFP1_TXN : out STD_LOGIC;
566  SFP1_TXP : out STD_LOGIC;
567  SFP2_TXN : out STD_LOGIC;
568  SFP2_TXP : out STD_LOGIC;
569  SFP_REFCLK_N : in STD_LOGIC;
570  SFP_REFCLK_P : in STD_LOGIC;
571  cs_out : out STD_LOGIC_VECTOR(511 downto 0);
572 -- ipbus signals
573  ipb_clk : in STD_LOGIC;
574  ipb_write : in STD_LOGIC;
575  ipb_strobe : in STD_LOGIC;
576  ipb_addr : in STD_LOGIC_VECTOR(31 downto 0);
577  ipb_wdata : in STD_LOGIC_VECTOR(31 downto 0);
578  ipb_rdata : out STD_LOGIC_VECTOR(31 downto 0)
579  );
580 END COMPONENT;
581 COMPONENT TTC_cntr
582  PORT(
583  sysclk : IN std_logic;
584  clk125 : IN std_logic;
585  ipb_clk : IN std_logic;
586  reset : IN std_logic;
587  rst_cntr : IN std_logic;
588  DB_cmd : IN std_logic;
589  inc_serr : IN std_logic;
590  inc_derr : IN std_logic;
591  inc_bcnterr : IN std_logic;
592  inc_l1ac : IN std_logic;
593  run : IN std_logic;
594  state : IN std_logic_vector(3 downto 0);
595  ttc_resync : IN std_logic;
596  ipb_addr : IN std_logic_vector(15 downto 0);
597  ipb_rdata : OUT std_logic_vector(31 downto 0)
598  );
599 END COMPONENT;
600 constant ipbus_ver_addr : std_logic_vector(15 downto 0) := x"0000";
601 constant ipbus_sfp_addr: std_logic_vector(15 downto 0) := x"0002";
602 constant CDRclk_pol : std_logic := '0';
603 constant CDRdata_pol : std_logic := '1';
604 constant TTCclk_pol : std_logic := '1';
605 constant TTCdata_pol : std_logic := '1';
606 constant Coarse_Delay: std_logic_vector(3 downto 0) := x"0";
607 signal rst_ipbus : std_logic := '0';
608 signal LDC_UsrClk : std_logic := '0';
609 signal wr_AMC_en : std_logic := '0';
610 signal wr_EnSFP : std_logic := '0';
611 signal fake_length : std_logic_vector(19 downto 0) := x"00400";
612 signal AMC_en : std_logic_vector(11 downto 0) := (others =>'0');
613 signal TTS_disable : std_logic_vector(11 downto 0) := (others =>'0');
614 signal AMC_Ready : std_logic_vector(11 downto 0) := (others =>'0');
615 signal TTC_lock : std_logic := '0';
616 signal BC0_lock : std_logic_vector(11 downto 0) := (others =>'0');
617 signal AMC_status : std_logic_vector(31 downto 0) := (others =>'0');
618 signal AMC_DATA : std_logic_vector(31 downto 0) := (others =>'0');
619 signal AMC_ack : std_logic := '0';
620 signal L1Aovfl_warning : std_logic := '0';
621 signal HCAL_trigger : std_logic := '0';
622 signal TRIGDATA : array12x8 := (others => (others => '0'));
623 signal TTS_coded : std_logic_vector(4 downto 0) := (others =>'0');
624 signal TTS_RQST : std_logic_vector(2 downto 0) := (others =>'0');
625 signal pattern : std_logic_vector(3 downto 0) := (others =>'0');
626 --signal Trig_mask : std_logic_vector(7 downto 0) := (others =>'0');
627 signal SPI_SCK_buf : std_logic := '0';
628 signal CLK_rdy : std_logic := '0';
629 signal I2C_data : std_logic_vector(31 downto 0) := (others =>'0');
630 signal TTCclk_in : std_logic := '0';
631 signal TTC_Clk : std_logic := '0';
632 signal TTC_strobe : std_logic := '0';
633 signal BcntErr_cnt : std_logic_vector(7 downto 0) := (others =>'0');
634 signal SinErr_cnt : std_logic_vector(7 downto 0) := (others =>'0');
635 signal DbErr_cnt : std_logic_vector(7 downto 0) := (others =>'0');
636 signal L1_reg : std_logic_vector(15 downto 0) := (others =>'0');
637 signal Bcnt_reg : std_logic_vector(11 downto 0) := (others =>'0');
638 signal OC_reg : std_logic_vector(31 downto 0) := (others =>'0');
639 signal DB_cmd : std_logic := '0';
640 signal V2S : std_logic := '0';
641 signal S2V : std_logic := '0';
642 signal S2V_cntr : std_logic_vector(5 downto 0) := (others => '0');
643 signal S2V_sr : std_logic_vector(3 downto 0) := (others => '0');
644 signal ddr_rdata : std_logic_vector(7 downto 0) := (others =>'0');
645 signal ipb_clk_dcm : std_logic := '0';
646 signal ipb_clk : std_logic := '0';
647 signal clk125_dcm : std_logic := '0';
648 signal clk125 : std_logic := '0';
649 signal DRPclk_dcm : std_logic := '0';
650 signal DRPclk : std_logic := '0';
651 signal sysclk_dcm : std_logic := '0';
652 signal sysclk : std_logic := '0';
653 signal clkfb : std_logic := '0';
654 signal refclk_dcm : std_logic := '0';
655 signal refclk : std_logic := '0';
656 signal mem_clk_dcm : std_logic := '0';
657 signal mem_clk : std_logic := '0';
658 signal sysclk_inp : std_logic := '0';
659 signal sysclk_in : std_logic := '0';
660 --signal clk125 : std_logic := '0';
661 signal sys_lock : std_logic := '0';
662 signal sys_lock_n : std_logic := '0';
663 signal ldc_reset : std_logic := '0';
664 signal ldc_GTXreset : std_logic := '0';
665 signal lsc_start : std_logic := '0';
666 signal lsc_reset : std_logic := '0';
667 signal lsc_GTXreset : std_logic := '0';
668 signal amc_reset : std_logic := '0';
669 signal amc_GTXreset : std_logic := '0';
670 signal conf7_q : std_logic := '0';
671 signal conf7_fall : std_logic := '0';
672 signal run : std_logic := '0';
673 signal LSC_LinkDown : std_logic := '0';
674 signal mem_rst : std_logic := '0';
675 signal mem_test : std_logic_vector(1 downto 0) := (others =>'0');
676 signal mem_stat : std_logic_vector(63 downto 0) := (others =>'0');
677 signal mem_ack : std_logic := '0';
678 signal mem_data : std_logic_vector(31 downto 0) := (others =>'0');
679 signal EventData : array3X67 := (others => (others => '0'));
680 signal wport_rdy : std_logic_vector(2 downto 0) := (others =>'0');
681 signal EventBufAddr : array3x14 := (others => (others => '0'));
682 signal EventBufAddr_we : std_logic_vector(2 downto 0) := (others =>'0');
683 signal evt_buf_full : std_logic_vector(2 downto 0) := (others =>'0');
684 signal wport_FIFO_full : std_logic_vector(2 downto 0) := (others =>'0');
685 signal TCPclk : std_logic := '0';
686 signal TCP_din : std_logic_vector(31 downto 0) := (others =>'0');
687 signal TCP_channel : std_logic_vector(1 downto 0) := (others =>'0');
688 signal TCP_we : std_logic := '0';
689 signal TCP_wcount : std_logic_vector(2 downto 0) := (others =>'0');
690 signal TCP_dout : std_logic_vector(31 downto 0) := (others =>'0');
691 signal TCP_dout_type : std_logic_vector(2 downto 0) := (others =>'0');
692 signal TCP_raddr : std_logic_vector(28 downto 0) := (others =>'0');
693 signal TCP_length : std_logic_vector(12 downto 0) := (others =>'0');
694 signal TCP_dout_valid : std_logic := '0';
695 signal TCP_rrqst : std_logic := '0';
696 signal TCP_rack : std_logic := '0';
697 signal TCP_lastword : std_logic := '0';
698 signal TCPIP_GTXreset : std_logic := '0';
699 signal MonBufOvfl : std_logic := '0';
700 signal MonBuf_empty : std_logic := '0';
701 --signal inc_mon_cntr : std_logic := '0';
702 signal mon_evt_wc : std_logic_vector(47 downto 0) := (others =>'0');
703 signal mon_evt_cnt : std_logic_vector(31 downto 0) := (others =>'0');
704 signal mon_ctrl : std_logic_vector(31 downto 0) := (others =>'0');
705 signal TCPbuf_avl : std_logic := '0';
706 signal mon_buf_avl : std_logic := '0';
707 signal EventBufAddrAvl : std_logic := '0';
708 signal EventBufAddrRe : std_logic := '0';
709 signal mon_wp : std_logic_vector(31 downto 0) := (others =>'0');
710 --signal TCP_releaseAck : std_logic_vector(2 downto 0) := (others =>'0');
711 --signal TCP_releaseRqst : std_logic_vector(2 downto 0) := (others =>'0');
712 --signal TCP_releaseAddr : array3X13 := (others => (others => '0'));
713 signal EventBuf_rqst : std_logic_vector(3 downto 0) := (others =>'0');
714 signal rst_cntr : std_logic := '0';
715 signal rst_ddr_pa : std_logic := '0';
716 signal inc_ddr_pa : std_logic := '0';
717 signal Source_ID : array3X12 := (others => (others => '0'));
718 signal ddr_pa : std_logic_vector(9 downto 0) := (others =>'0');
719 signal CDRclk : std_logic := '0';
720 signal TTS_clk : std_logic := '0';
721 signal chk_lock : std_logic := '0';
722 signal chk_lock_q : std_logic := '0';
723 signal BC0 : std_logic := '0';
724 signal BC0_dl : std_logic := '0';
725 signal T3_trigger : std_logic := '0';
726 signal BX_offset2SC : std_logic_vector(11 downto 0) := (others =>'0');
727 signal bcnt : std_logic_vector(11 downto 0) := x"000";
728 signal LocalL1A_cfg : std_logic_vector(31 downto 0) := (others =>'0');
729 signal BCN_off : std_logic_vector(12 downto 0) := (others =>'0');
730 signal OC_off : std_logic_vector(3 downto 0) := (others =>'0');
731 signal en_cal_win : std_logic := '0';
732 signal CalibCtrl : std_logic_vector(31 downto 0) := x"0d800d80";
733 signal cal_win_high : std_logic_vector(11 downto 0) := (others =>'0');
734 signal cal_win_low : std_logic_vector(11 downto 0) := (others =>'0');
735 signal CalType : std_logic_vector(3 downto 0) := (others =>'0');
736 signal TTC_Brcst : std_logic_vector(3 downto 0) := (others =>'0');
737 signal local_TTCcmd : std_logic := '0';
738 --signal IsG2 : std_logic := '0';
739 signal en_brcst : std_logic := '0';
740 signal ttc_start : std_logic := '0';
741 signal ttc_stop : std_logic := '0';
742 signal ttc_soft_reset : std_logic := '0';
743 signal ttc_soft_resetp : std_logic := '0';
744 signal ttc_ready : std_logic := '0';
745 signal ttc_serr : std_logic := '0';
746 signal ttc_derr : std_logic := '0';
747 signal ttc_bcnt_err : std_logic := '0';
748 signal ttc_evcnt_reset : std_logic := '0';
749 signal inc_rate_ofw : std_logic := '0';
750 signal rate_ofw : std_logic := '0';
751 signal rate_ofwp : std_logic := '0';
752 signal rate_ofw_q : std_logic := '0';
753 signal sync_lost : std_logic := '0';
754 signal oc_cntr : std_logic_vector(3 downto 0) := (others =>'0');
755 signal trig_BX : std_logic_vector(12 downto 0) := "0000111110100";
756 signal ttc_resync : std_logic := '0';
757 signal AllEventBuilt : std_logic := '0';
758 signal dcc_quiet : std_logic := '0';
759 signal inc_oc : std_logic := '0';
760 signal inc_L1ac : std_logic := '0';
761 signal inc_bcnterr : std_logic := '0';
762 signal inc_serr : std_logic := '0';
763 signal inc_derr : std_logic := '0';
764 signal evn_fifo_full : std_logic := '0';
765 signal event_number_avl : std_logic := '0';
766 signal state : std_logic_vector(3 downto 0) := (others =>'0');
767 signal TTS_wait : std_logic_vector(20 downto 0) := (others =>'0');
768 signal event_number : std_logic_vector(59 downto 0) := (others =>'0');
769 signal status_l : std_logic_vector(22 downto 0) := (others =>'0');
770 signal SFP_down_l : std_logic_vector(2 downto 0) := (others =>'0');
771 signal SFP_status_l : std_logic_vector(11 downto 0) := (others =>'0');
772 signal AMC_status_l : std_logic_vector(31 downto 0) := (others =>'0');
773 signal TTC_cntr_data : std_logic_vector(31 downto 0) := (others => '0');
774 signal got_SN : std_logic := '0';
775 signal ipb_strobe_q : std_logic := '0';
776 signal SFP_clk : std_logic := '0';
777 signal AMC_clk : std_logic := '0';
778 signal AMC_clk_in : std_logic := '0';
779 signal SV_Cntr : std_logic_vector(7 downto 0) := (others => '0');
780 signal sysclk_div : std_logic_vector(7 downto 0) := (others => '0');
781 signal SFP_UsrClk : std_logic := '0';
782 signal SFP_TxOutClk : std_logic := '0';
783 signal I2C_debug_out : std_logic_vector(15 downto 0) := (others =>'0');
784 signal SFPOSC_rdy : std_logic := '0';
785 signal reset : std_logic := '0';
786 signal DAQ_reset : std_logic := '0';
787 signal AMCOSC_rdy : std_logic := '0';
788 --signal cs_clk_in : std_logic := '0';
789 --signal cs_clk : std_logic := '0';
790 signal TTC_debug : std_logic_vector(63 downto 0) := (others =>'0');
791 signal TxDisable_i : std_logic_vector(3 downto 0) := (others => '0');
792 signal DAQfifo_re : std_logic := '0';
793 signal DAQfifoAlmostEmpty : std_logic := '0';
794 signal DAQfifoEmpty : std_logic := '0';
795 signal DAQfifo_do : std_logic_vector(63 downto 0) := (others =>'0');
796 signal DAQ_debug_in : std_logic_vector(63 downto 0) := (others =>'0');
797 signal LDC_debug_out : std_logic_vector(63 downto 0) := (others =>'0');
798 signal LSC_debug_out : std_logic_vector(63 downto 0) := (others =>'0');
799 signal ddr_debug_in : std_logic_vector(31 downto 0) := (others =>'0');
800 signal ddr_debug_out : std_logic_vector(127 downto 0) := (others =>'0');
801 signal GbE_REFCLK : std_logic := '0';
802 signal S6Link_debug_in : std_logic_vector(31 downto 0) := (others =>'0');
803 signal S6Link_debug_out : std_logic_vector(127 downto 0) := (others =>'0');
804 signal GbE_debug_in : std_logic_vector(31 downto 0) := (others =>'0');
805 signal GbE_debug_out : std_logic_vector(127 downto 0) := (others =>'0');
806 signal AMC_debug_in : std_logic_vector(255 downto 0) := (others =>'0');
807 signal AMC_debug_out : std_logic_vector(255 downto 0) := (others =>'0');
808 signal SFP0_debug_in : std_logic_vector(31 downto 0) := (others =>'0');
809 signal SFP0_debug_out : std_logic_vector(127 downto 0) := (others =>'0');
810 signal SFP1_debug_in : std_logic_vector(31 downto 0) := (others =>'0');
811 signal SFP1_debug_out : std_logic_vector(127 downto 0) := (others =>'0');
812 signal ipb_master_out : ipb_wbus;
813 signal ipb_master_in : ipb_rbus;
814 signal SN : std_logic_vector(8 downto 0) := (others =>'0');
815 signal MACADDR : std_logic_vector(47 downto 0) := (others =>'0');
816 signal ipaddr : std_logic_vector(31 downto 0) := (others =>'0');
817 signal en_RARP : std_logic := '0';
818 --signal SPI_IP : std_logic_vector(31 downto 0) := (others =>'0');
819 signal status : std_logic_vector(31 downto 0) := (others =>'0');
820 signal cmd : std_logic_vector(31 downto 0) := (others =>'0');
821 signal cmd0_dl : std_logic_vector(1 downto 0) := (others =>'0');
822 signal cmd2_dl : std_logic_vector(1 downto 0) := (others =>'0');
823 signal conf : std_logic_vector(15 downto 0) := (others =>'0');
824 signal LSC_ID : std_logic_vector(15 downto 0) := x"1234";
825 signal OT : std_logic := '0';
826 signal inc_HTRCRC_err : std_logic := '0';
827 signal ttc_data : std_logic_vector(31 downto 0) := (others => '0');
828 signal sysmon_data : std_logic_vector(31 downto 0) := (others => '0');
829 signal HCAL_trig_data : std_logic_vector(31 downto 0) := (others => '0');
830 signal device_temp : std_logic_vector(11 downto 0) := (others =>'0');
831 signal ALM : std_logic_vector(7 downto 0) := (others =>'0');
832 signal evt_data_rdy : std_logic_vector(2 downto 0) := (others => '0');
833 signal evt_data_re : std_logic_vector(2 downto 0) := (others => '0');
834 signal evt_data_we : std_logic_vector(2 downto 0) := (others => '0');
835 --signal event_size : array3x13;
836 signal SFP_data : std_logic_vector(31 downto 0) := (others =>'0');
837 signal SFP_ack : std_logic := '0';
838 --signal TCP_data : std_logic_vector(31 downto 0) := (others =>'0');
839 --signal TCP_ack : std_logic := '0';
840 signal S2V_SyncRegs : std_logic_vector(2 downto 0) := (others => '0');
841 signal resetSyncRegs : std_logic_vector(2 downto 0) := (others => '0');
842 signal sysclk_div7SyncRegs : std_logic_vector(3 downto 0) := (others => '0');
843 signal resetCntr_SyncRegs : std_logic_vector(2 downto 0) := (others =>'0');
844 signal newIPADDR : std_logic := '0';
845 signal newIPADDRSyncRegs : std_logic_vector(2 downto 0) := (others =>'0');
846 signal DNA_out : std_logic := '0';
847 signal load_DNA : std_logic := '0';
848 signal shift_DNA : std_logic_vector(2 downto 0) := (others =>'0');
849 signal DNA_cntr : std_logic_vector(5 downto 0) := (others =>'0');
850 signal DNA : std_logic_vector(56 downto 0) := (others =>'0');
851 signal Dis_pd : std_logic := '0';
852 signal DAQ_bp : std_logic := '0';
853 signal IgnoreDAQ : std_logic := '0';
854 signal WaitMonBuf : std_logic := '0';
855 signal enSFP : std_logic_vector(3 downto 0) := (others =>'0');
856 signal SFP_down : std_logic_vector(2 downto 0) := (others =>'0');
857 signal WrtMonBlkDone : std_logic_vector(2 downto 0) := (others =>'0');
858 signal WrtMonEvtDone : std_logic_vector(2 downto 0) := (others =>'0');
859 signal KiloByte_toggle : std_logic_vector(2 downto 0) := (others =>'0');
860 signal EoB_toggle : std_logic_vector(2 downto 0) := (others =>'0');
861 signal Cntr2ms : std_logic_vector(18 downto 0) := (others => '0');
862 signal LiveTime : std_logic_vector(7 downto 0) := (others => '0');
863 signal LiveTime_l : std_logic_vector(7 downto 0) := (others => '0');
864 signal LiveTimeCntr : std_logic_vector(18 downto 0) := (others => '0');
865 signal DataRate : array3x19 := (others => (others => '0'));
866 signal DataRate_l : array3x19 := (others => (others => '0'));
867 signal DataRateCntr : array3x19 := (others => (others => '0'));
868 component icon2
869  PORT (
870  CONTROL0 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
871  CONTROL1 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0));
872 
873 end component;
874 component ila16x32k
875  PORT (
876  CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
877  CLK : IN STD_LOGIC;
878  DATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
879  TRIG0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0));
880 
881 end component;
882 signal CONTROL0 : std_logic_vector(35 downto 0) := (others => '0');
883 signal CONTROL1 : std_logic_vector(35 downto 0) := (others => '0');
884 signal TRIG0 : std_logic_vector(7 downto 0) := (others => '0');
885 signal TRIG1 : std_logic_vector(7 downto 0) := (others => '0');
886 signal DATA0 : std_logic_vector(15 downto 0) := (others => '0');
887 signal DATA1 : std_logic_vector(15 downto 0) := (others => '0');
888 begin
889 --i_icon : icon2
890 -- port map (
891 -- CONTROL0 => CONTROL0,
892 -- CONTROL1 => CONTROL1);
893 --i_ila : ila16x32k
894 -- port map (
895 -- CONTROL => CONTROL0,
896 -- CLK => sysclk,
897 -- DATA => DATA0,
898 -- TRIG0 => TRIG0);
899 --DATA0(14) <= evt_buf_full(0);
900 --DATA0(13) <= evt_data_re(0);
901 --DATA0(12) <= evt_data_rdy(0);
902 --DATA0(11 downto 10) <= EventBufAddr(0)(5 downto 4);
903 --DATA0(9 downto 8) <= EventData(0)(65 downto 64);
904 --DATA0(7) <= wport_rdy(0);
905 --DATA0(6) <= wport_FIFO_full(0);
906 --DATA0(5) <= evt_data_we(0);
907 --DATA0(4) <= EventBufAddr_we(0);
908 --DATA0(3 downto 0) <= mem_stat(3 downto 0);
909 --TRIG0(7 downto 4) <= (others => '0');
910 --TRIG0(3) <= wport_rdy(0);
911 --TRIG0(2) <= EventBufAddr_we(0);
912 --TRIG0(1) <= evt_data_re(0);
913 --TRIG0(0) <= evt_data_rdy(0);
914 --
915 --i_il2 : ila16x32k
916 -- port map (
917 -- CONTROL => CONTROL1,
918 -- CLK => mem_stat(19),
919 -- DATA => DATA1,
920 -- TRIG0 => TRIG1);
921 --DATA1(14 downto 0) <= mem_stat(18 downto 4);
922 --TRIG1(7 downto 2) <= (others => '0');
923 --TRIG1(1 downto 0) <= mem_stat(18 downto 17);
924 --IsG2 <= '1' when flavor = "G2" else '0';
925 i_TTS_if: TTS_if PORT MAP(
926  sysclk => sysclk,
927  TTS_clk => TTS_clk,
928  reset => sys_lock_n,
929  local_TTC => conf(8),
930  TTS => state,
931  TTS_out_p => TTS_out_p,
932  TTS_out_n => TTS_out_n
933  );
934 g_HCAL_trig : if(flavor = "HCAL") generate
935  i_HCAL_trig: HCAL_trig PORT MAP(
936  TTC_clk => TTC_clk,
937  DRPCLK => DRPclk,
938  reset => reset,
939  SFP_ABS => SFP_ABS(2),
940  BC0 => BC0,
941  BC0_dl => BC0_dl,
942  Trigdata => Trigdata,
943  triggerOut => HCAL_trigger,
944  TTC_lock => TTC_lock,
945  BC0_lock => BC0_lock,
946  AMC_en => AMC_en,
947  BX_offset2SC => BX_offset2SC,
948  ipb_clk => ipb_clk,
949  ipb_write => ipb_master_out.ipb_write ,
950  ipb_strobe => ipb_master_out.ipb_strobe ,
951  ipb_addr => ipb_master_out.ipb_addr ,
952  ipb_wdata => ipb_master_out.ipb_wdata ,
953  ipb_rdata => HCAL_trig_data ,
954  GTX_REFCLKp => CDR_REFCLK_P,
955  GTX_REFCLKn => CDR_REFCLK_N,
956  GTX_RXp => SFP2_RXP,
957  GTX_RXn => SFP2_RXN,
958  GTX_TXp => SFP2_TXP,
959  GTX_TXn => SFP2_TXN
960  );
961 end generate g_HCAL_trig;
962 TxDisable <= TxDisable_i;
963 i_I2C: I2C PORT MAP(
964  clk => DRPclk ,
965  ipb_clk => clk125,
966  reset => sys_lock_n,
967  addr => ipb_master_out.ipb_addr,
968  rdata => I2C_data,
969  CLK_rdy => CLK_rdy,
970  CLK_SCL => CLK_SCL,
971  CLK_SDA => CLK_SDA,
972  SFP_ABS => SFP_ABS,
973  SFP_LOS => SFP_LOS,
974  SFP_SCL => SFP_SCL,
975  SFP_SDA => SFP_SDA
976  );
977 i_SPI_SCK_buf: bufh port map(i => SPI_SCK, o => SPI_SCK_buf);
978 i_SPI_if: SPI_if PORT MAP(
979  SCK => SPI_SCK,
980  CSn => SPI_CS_b,
981  MOSI => SPI_MOSI,
982  MISO => SPI_MISO,
983  SN => SN,
984  OT => ALM(0),
985  IsT1 => '1',
986  SPI_we => open,
987  en_RARP => en_RARP,
988  newIPADDR => newIPADDR,
989  IPADDR => IPADDR,
990  SPI_rdata => (others => '0'),
991  SPI_wdata => open,
992  SPI_addr => open
993  );
994 i_ttc_if: ttc_if PORT MAP(
995  clk => sysclk ,
996  refclk => sysclk,
997  reset => reset,
998  rst_PLL => cmd(3),
999  run => run,
1000  DB_cmd_in => cmd(9),
1001  DB_cmd_out => DB_cmd,
1002  IgnoreDAQ => IgnoreDAQ,
1003  TTC_strobe => TTC_strobe,
1004  sys_lock => sys_lock,
1005  local_TTC => conf(8),
1006  local_TTCcmd => local_TTCcmd,
1007  single_TTCcmd => cmd(8),
1008  TTS_clk => TTS_clk,
1009  BC0 => BC0,
1010  DIV4 => DIV4,
1011  DIV_nRST => DIV_nRST,
1012  CDRclk_p => CDRclk_p,
1013  CDRclk_n => CDRclk_n,
1014  CDRclk_out => CDRclk,
1015  CDRdata_p => CDRdata_p,
1016  CDRdata_n => CDRdata_n,
1017  TTCdata_p => TTCdata_p,
1018  TTCdata_n => TTCdata_n,
1019  TTC_LOS => TTC_LOS,
1020  TTC_LOL => TTC_LOL,
1021  BCN_off => BCN_off,
1022  OC_off => OC_off,
1023  en_cal_win => en_cal_win,
1024  cal_win_high => cal_win_high,
1025  cal_win_low => cal_win_low,
1026  CalType => CalType,
1027  TTC_Brcst => TTC_Brcst,
1028  ovfl_warning => L1Aovfl_warning,
1029  ipb_clk => ipb_clk,
1030  ipb_write => ipb_master_out.ipb_write ,
1031  ipb_strobe => ipb_master_out.ipb_strobe ,
1032  ipb_addr => ipb_master_out.ipb_addr ,
1033  ipb_wdata => ipb_master_out.ipb_wdata ,
1034  ipb_rdata => ttc_data,
1035  en_localL1A => conf(2),
1036  trig_BX => trig_BX,
1037  LocalL1A_cfg => LocalL1A_cfg,
1038  localL1A_s => cmd(26),
1039  localL1A_r => cmd(10),
1040  localL1A_periodic => status(10),
1041  T3_trigger => T3_trigger,
1042  HCAL_trigger => HCAL_trigger,
1043  EvnRSt_l => cmd(11),
1044  OcnRSt_l => cmd(12),
1045  en_brcst => en_brcst,
1046  ttc_start => ttc_start,
1047  ttc_stop => ttc_stop,
1048  ttc_soft_reset => ttc_soft_reset ,
1049  ttc_ready => ttc_ready,
1050  ttc_serr => ttc_serr,
1051  ttc_derr => ttc_derr,
1052  ttc_bcnt_err => ttc_bcnt_err,
1053  rate_OFW => rate_OFW,
1054  sync_lost => sync_lost,
1055  inc_oc => inc_oc,
1056  inc_l1ac => inc_l1ac,
1057  inc_bcnterr => inc_bcnterr,
1058  inc_serr => inc_serr,
1059  inc_derr => inc_derr,
1060  state => state,
1061  evn_fifo_full => evn_fifo_full,
1062  ttc_evcnt_reset => ttc_evcnt_reset,
1063  event_number_avl => event_number_avl,
1064  event_number => event_number
1065  );
1066 local_TTCcmd <= conf(5) or conf(8);
1067 --local_TTCcmd <= conf(5);
1068 CalibCtrl(31) <= en_cal_win;
1069 CalibCtrl(30 downto 28) <= "000";
1070 CalibCtrl(27 downto 16) <= cal_win_high;
1071 CalibCtrl(15 downto 12) <= CalType;
1072 CalibCtrl(11 downto 0) <= cal_win_low;
1073 cal_win_high(11 downto 6) <= "110110";
1074 cal_win_low(11 downto 6) <= "110110";
1075 i_S2V: IBUFDS generic map(DIFF_TERM => TRUE,IOSTANDARD => "LVDS_25") port map(i => S2V_p, ib => S2V_n, o => S2V);
1076 process(CDRclk)
1077 begin
1078  if(CDRclk'event and CDRclk = '1')then
1079  if(conf(15) = '0')then
1080  T3_trigger <= '0';
1081  else
1082  T3_trigger <= S2V;
1083  end if;
1084  end if;
1085 end process;
1086 i_GbE_REFCLK: IBUFDS_GTE2
1087  port map
1088  (
1089  O => GbE_REFCLK,
1090  ODIV2 => open,
1091  CEB => '0',
1092  I => GbE_REFCLK_P, -- Connect to package pin AB6
1093  IB => GbE_REFCLK_N -- Connect to package pin AB5
1094  );
1095 i_TTCclk_in : IBUFGDS generic map (DIFF_TERM => TRUE,IOSTANDARD => "LVDS_25")
1096  port map (
1097  O => TTCclk_in, -- Clock buffer output
1098  I => TTCclk_p, -- Diff_p clock buffer input
1099  IB => TTCclk_n -- Diff_n clock buffer input
1100  );
1101 i_TTC_CLK_buf: bufg port map(i => TTCclk_in, o => TTC_Clk);
1102 i_sysclk_in_buf: bufh port map(i => GbE_REFCLK, o => sysclk_in);
1103 i_PLL_sysclk : PLLE2_BASE
1104  generic map (
1105  BANDWIDTH => "OPTIMIZED", -- OPTIMIZED, HIGH, LOW
1106  CLKFBOUT_MULT => 8, -- Multiply value for all CLKOUT, (2-64)
1107  CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB, (-360.000-360.000).
1108  CLKIN1_PERIOD => 8.0, -- Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
1109  -- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for each CLKOUT (1-128)
1110  CLKOUT0_DIVIDE => 5,
1111  CLKOUT1_DIVIDE => 32,
1112  CLKOUT2_DIVIDE => 20,
1113  DIVCLK_DIVIDE => 1, -- Master division value, (1-56)
1114  REF_JITTER1 => 0.0, -- Reference input jitter in UI, (0.000-0.999).
1115  STARTUP_WAIT => "FALSE" -- Delay DONE until PLL Locks, ("TRUE"/"FALSE")
1116  )
1117  port map (
1118  -- Clock Outputs: 1-bit (each) output: User configurable clock outputs
1119  CLKOUT0 => sysclk_dcm,
1120  CLKOUT1 => ipb_clk_dcm,
1121  CLKOUT2 => DRPclk_dcm,
1122  -- Feedback Clocks: 1-bit (each) output: Clock feedback ports
1123  CLKFBOUT => clk125_dcm, -- 1-bit output: Feedback clock
1124  -- Status Port: 1-bit (each) output: PLL status ports
1125  LOCKED => sys_lock, -- 1-bit output: LOCK
1126  -- Clock Input: 1-bit (each) input: Clock input
1127  CLKIN1 => sysclk_in, -- 1-bit input: Input clock
1128  -- Control Ports: 1-bit (each) input: PLL control ports
1129  PWRDWN => '0', -- 1-bit input: Power-down
1130  RST => '0', -- 1-bit input: Reset
1131  -- Feedback Clocks: 1-bit (each) input: Clock feedback ports
1132  CLKFBIN => clk125 -- 1-bit input: Feedback clock
1133  );
1134 i_clk125_buf: bufg port map(i => clk125_dcm, o => clk125 );
1135 i_ipb_clk_buf: bufg port map(i => ipb_clk_dcm, o => ipb_clk);
1136 i_DRPclk_buf: bufg port map(i => DRPclk_dcm, o => DRPclk );
1137 i_sysclk_buf: bufg port map(i => sysclk_dcm, o => sysclk );
1138 --i_refclk_buf: bufg port map(i => refclk_dcm, o => refclk);
1139 reset <= not sys_lock or cmd(0);
1140 --sysclk <= refclk;
1141 process(sysclk,reset)
1142 begin
1143  if(reset = '1')then
1144  resetSyncRegs <= (others => '1');
1145  elsif(sysclk'event and sysclk = '1')then
1146  resetSyncRegs <= resetSyncRegs(1 downto 0) & '0';
1147  end if;
1148 end process;
1149 i_ddr_if: ddr_if PORT MAP(
1150  mem_clk_p => sys_clk_p,
1151  mem_clk_n => sys_clk_n,
1152  mem_rst => mem_rst,
1153  clk_ref => sysclk ,
1154  sysclk => sysclk,
1155  TCPclk => TCPclk,
1156  reset => reset,
1157  resetsys => resetSyncRegs(2),
1158  run => run,
1159  mem_test => mem_test,
1160  EventData => EventData,
1161  EventData_we => evt_data_we,
1162  wport_rdy => wport_rdy,
1163  WrtMonBlkDone => WrtMonBlkDone,
1164  WrtMonEvtDone => WrtMonEvtDone,
1165  KiloByte_toggle => KiloByte_toggle,
1166  EoB_toggle => EoB_toggle,
1167  EventBufAddr => EventBufAddr,
1168  EventBufAddr_we => EventBufAddr_we,
1169  EventFIFOfull => wport_FIFO_full,
1170  TCP_din => TCP_din,
1171  TCP_channel => TCP_channel,
1172  TCP_we => TCP_we ,
1173  TCP_wcount => TCP_wcount,
1174  TCP_dout => TCP_dout,
1175  TCP_dout_type => TCP_dout_type,
1176  TCP_raddr => TCP_raddr,
1177  TCP_length => TCP_length,
1178  TCP_dout_valid => TCP_dout_valid ,
1179  TCP_rrqst => TCP_rrqst,
1180  TCP_rack => TCP_rack,
1181  TCP_lastword => TCP_lastword,
1182  page_addr => ddr_pa,
1183  ipb_clk => ipb_clk,
1184  ipb_write => ipb_master_out.ipb_write ,
1185  ipb_strobe => ipb_master_out.ipb_strobe ,
1186  ipb_addr => ipb_master_out.ipb_addr ,
1187  ipb_wdata => ipb_master_out.ipb_wdata ,
1188  ipb_rdata => mem_data,
1189  ipb_ack => mem_ack,
1190  mem_stat => mem_stat,
1191  device_temp => device_temp,
1192  ddr3_dq => ddr3_dq,
1193  ddr3_dm => ddr3_dm,
1194  ddr3_addr => ddr3_addr,
1195  ddr3_ba => ddr3_ba,
1196  ddr3_dqs_p => ddr3_dqs_p,
1197  ddr3_dqs_n => ddr3_dqs_n,
1198  ddr3_ras_n => ddr3_ras_n,
1199  ddr3_cas_n => ddr3_cas_n,
1200  ddr3_we_n => ddr3_we_n,
1201  ddr3_reset_n => ddr3_reset_n,
1202  ddr3_cke => ddr3_cke,
1203  ddr3_odt => ddr3_odt,
1204  ddr3_ck_p => ddr3_ck_p,
1205  ddr3_ck_n => ddr3_ck_n
1206  );
1207 --mem_rst <= not sys_lock or not CLK_rdy or cmd(5) or cmd(0);
1208 mem_rst <= not sys_lock or not CLK_rdy or cmd(5);
1209 MACADDR <= x"080030f30" & '0' & not SN(8) & '0' & not SN(7 downto 6) & '1' & SN(5 downto 0);
1210 i_ipbus_if: ipbus_if PORT MAP(
1211  ipb_clk => ipb_clk,
1212  UsRclk => clk125,
1213  DRPclk => DRPclk,
1214  reset => rst_ipbus,
1215  GTX_RESET => sys_lock_n,
1216  MACADDR => MACADDR, -- new mac range 08-00-30-F3-00-00 to 08-00-30-F3-00-7F
1217  en_RARP => en_RARP,
1218  IPADDR => IPADDR,
1219  GbE_REFCLK => GbE_REFCLK,
1220  S6LINK_RXN => S6LINK_RXN,
1221  S6LINK_RXP => S6LINK_RXP,
1222  S6LINK_TXN => S6LINK_TXN,
1223  S6LINK_TXP => S6LINK_TXP,
1224  wr_AMC_en => wr_AMC_en,
1225  amc_en => AMC_en,
1226  ipb_out => ipb_master_out ,
1227  ipb_in => ipb_master_in,
1228  got_SN => got_SN,
1229  SN => SN,
1230  debug_in => (others => '0'),
1231  debug_out => open
1232  );
1233 --LSC_LinkDown <= '1' when conf(1) = '0' or or_reduce(EnSFP(2 downto 0) and SFP_down) = '1' else '0';
1234 --status(0) <= LSC_LinkDown;
1235 status(0) <= or_reduce(SFP_down);
1236 status(1) <= MonBufOvfl;
1237 status(2) <= mon_evt_cnt(10);
1238 status(3) <= MonBuf_empty;
1239 status(4) <= mem_stat(0); -- monitor input FIFO overflow
1240 status(5) <= not ttc_ready;
1241 status(6) <= ttc_bcnt_err;
1242 status(7) <= ttc_serr;
1243 status(8) <= ttc_derr;
1244 status(9) <= sync_lost;
1245 status(13) <= L1Aovfl_warning;
1246 status(15) <= mem_stat(63);
1247 status(23) <= '0';
1248 run <= conf(0);
1249 EnSFP(3) <= not conf(1);
1250 mem_test <= conf(6) & conf(4);
1251 --en_brcst <= conf(5);
1252 en_brcst <= '0';
1253 i_cmd0_dl0 : SRL16E
1254  port map (
1255  Q => cmd0_dl(0), -- SRL data output
1256  A0 => '1', -- Select[0] input
1257  A1 => '1', -- Select[1] input
1258  A2 => '1', -- Select[2] input
1259  A3 => '0', -- Select[3] input
1260  CE => '1', -- Clock enable input
1261  CLK => ipb_clk, -- Clock input
1262  D => cmd(0) -- SRL data input
1263  );
1264 i_cmd0_dl1 : SRL16E
1265  port map (
1266  Q => cmd0_dl(1), -- SRL data output
1267  A0 => '1', -- Select[0] input
1268  A1 => '1', -- Select[1] input
1269  A2 => '1', -- Select[2] input
1270  A3 => '0', -- Select[3] input
1271  CE => '1', -- Clock enable input
1272  CLK => ipb_clk, -- Clock input
1273  D => cmd0_dl(0) -- SRL data input
1274  );
1275 i_cmd2_dl0 : SRL16E
1276  port map (
1277  Q => cmd2_dl(0), -- SRL data output
1278  A0 => '1', -- Select[0] input
1279  A1 => '1', -- Select[1] input
1280  A2 => '1', -- Select[2] input
1281  A3 => '0', -- Select[3] input
1282  CE => '1', -- Clock enable input
1283  CLK => ipb_clk, -- Clock input
1284  D => cmd(2) -- SRL data input
1285  );
1286 i_cmd2_dl1 : SRL16E
1287  port map (
1288  Q => cmd2_dl(1), -- SRL data output
1289  A0 => '1', -- Select[0] input
1290  A1 => '1', -- Select[1] input
1291  A2 => '1', -- Select[2] input
1292  A3 => '0', -- Select[3] input
1293  CE => '1', -- Clock enable input
1294  CLK => ipb_clk, -- Clock input
1295  D => cmd2_dl(0) -- SRL data input
1296  );
1297 process(ipb_clk)
1298 begin
1299  if(ipb_clk'event and ipb_clk = '1')then
1300  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = CSR_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1301  cmd <= ipb_master_out.ipb_wdata;
1302  else
1303  cmd <= (others => '0');
1304  end if;
1305  conf7_q <= conf(7);
1306  conf7_fall <= conf7_q and not conf(7);
1307  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = CFG_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1308  conf <= ipb_master_out.ipb_wdata(15 downto 0);
1309  end if;
1310  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = HTR_EN_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1311  if(flavor = "G2")then
1312  IgnoreDAQ <= '0';
1313  else
1314  IgnoreDAQ <= ipb_master_out.ipb_wdata(31);
1315  end if;
1316  Dis_pd <= ipb_master_out.ipb_wdata(15);
1317  if(flavor /= "HCAL")then
1318  EnSFP(2) <= ipb_master_out.ipb_wdata(14);
1319  else
1320  EnSFP(2) <= '0';
1321  end if;
1322  EnSFP(1 downto 0) <= ipb_master_out.ipb_wdata(13 downto 12);
1323  AMC_en <= ipb_master_out.ipb_wdata(11 downto 0);
1324  if(AMC_en = ipb_master_out.ipb_wdata(11 downto 0))then
1325  wr_AMC_en <= '0';
1326  else
1327  wr_AMC_en <= '1';
1328  end if;
1329  if(flavor /= "HCAL" and EnSFP(2) /= ipb_master_out.ipb_wdata(14))then
1330  wr_EnSFP <= '1';
1331  elsif(EnSFP(1 downto 0) /= ipb_master_out.ipb_wdata(13 downto 12))then
1332  wr_EnSFP <= '1';
1333  else
1334  wr_EnSFP <= '0';
1335  end if;
1336  else
1337  wr_AMC_en <= '0';
1338  wr_EnSFP <= '0';
1339  end if;
1340  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = x"001a" and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1341  TTS_disable <= ipb_master_out.ipb_wdata(11 downto 0);
1342  end if;
1343  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = TTC_cal_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1344  en_cal_win <= ipb_master_out.ipb_wdata(31);
1345  cal_win_high(5 downto 0) <= ipb_master_out.ipb_wdata(21 downto 16);
1346  cal_win_low(5 downto 0) <= ipb_master_out.ipb_wdata(5 downto 0);
1347  end if;
1348  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = SRC_id_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1349  Source_ID(0)(11 downto 0) <= ipb_master_out.ipb_wdata(11 downto 0);
1350  end if;
1351  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = SRC_id1_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1352  Source_ID(1)(11 downto 0) <= ipb_master_out.ipb_wdata(11 downto 0);
1353  end if;
1354  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = x"001c" and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1355  LocalL1A_cfg <= ipb_master_out.ipb_wdata;
1356  end if;
1357  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = x"001b" and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1358  trig_BX(11 downto 0) <= ipb_master_out.ipb_wdata(11 downto 0);
1359  end if;
1360  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = SFP_CSR_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1361  LSC_ID(15 downto 2) <= ipb_master_out.ipb_wdata(31 downto 18);
1362  TxDisable_i <= ipb_master_out.ipb_wdata(15 downto 12);
1363  end if;
1364  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = TTC_bcnt_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1365  OC_OFF <= ipb_master_out.ipb_wdata(19 downto 16);
1366  BCN_OFF <= ipb_master_out.ipb_wdata(12 downto 0);
1367  end if;
1368  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = fake_length_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1369  fake_length <= ipb_master_out.ipb_wdata(19 downto 0);
1370  end if;
1371  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = x"0019" and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1372  pattern <= ipb_master_out.ipb_wdata(11 downto 8);
1373 -- Trig_mask <= ipb_master_out.ipb_wdata(7 downto 0);
1374  end if;
1375  if(reset = '1' or (ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = MON_ctrl_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1'))then
1376  ddr_pa <= (others => '0');
1377  elsif(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = PAGE_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1')then
1378  if(run = '1')then
1379  if(MonBuf_empty = '0')then
1380  ddr_pa <= ddr_pa + 1;
1381  end if;
1382  else
1383  ddr_pa <= ipb_master_out.ipb_wdata(9 downto 0);
1384  end if;
1385  end if;
1386  if(ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(15 downto 0) = PAGE_addr and ipb_master_out.ipb_write = '1' and ipb_master_out.ipb_strobe = '1' and run = '1' and MonBuf_empty = '0')then
1387  inc_ddr_pa <= '1';
1388  else
1389  inc_ddr_pa <= '0';
1390  end if;
1391  if(DB_cmd = '1')then
1392  status_l <= status(22 downto 0);
1393  SFP_down_l <= SFP_down;
1394  SFP_status_l <= TxFault & (TTC_LOL or TTC_LOL) & SFP_LOS & SFP_ABS;
1395  AMC_status_l <= AMC_status;
1396  DataRate_l <= DataRate;
1397  LiveTime_l <= LiveTime;
1398  end if;
1399  end if;
1400 end process;
1401 ipb_master_in.ipb_ack <= ipb_master_out.ipb_strobe when ipb_master_out.ipb_addr(27) = '0' and ipb_master_out.ipb_addr(17) = '0' else mem_ack;
1402 process(ipb_master_out.ipb_addr)
1403 begin
1404  if(ipb_master_out.ipb_addr(27) = '1' or ipb_master_out.ipb_addr(17) = '1')then
1405  ipb_master_in.ipb_rdata <= mem_data;
1406  elsif(ipb_master_out.ipb_addr(14 downto 5) = CSR_addr(14 downto 5))then
1407  if(ipb_master_out.ipb_addr(15) = '0')then
1408  case ipb_master_out.ipb_addr(4 downto 0) is
1409  when "00000" => ipb_master_in.ipb_rdata <= not SN(7 downto 0) & not SN(8) & status(22 downto 0);
1410  when "00001" => ipb_master_in.ipb_rdata <= K7version & conf;
1411  when "00010" => ipb_master_in.ipb_rdata <= mon_ctrl;
1412  when "00011" => ipb_master_in.ipb_rdata <= IgnoreDAQ & SFP_down & AMC_Ready & Dis_pd & EnSFP(2 downto 0) & AMC_en;
1413  when "00100" => ipb_master_in.ipb_rdata <= LSC_ID & TxDisable_i & TxFault & (TTC_LOL or TTC_LOL) & SFP_LOS & SFP_ABS;
1414  when "00101" => ipb_master_in.ipb_rdata <= AMC_status;
1415  when "00110" => ipb_master_in.ipb_rdata <= x"0" & BC0_lock & x"0" & BX_offset2SC;
1416  when "00111" => ipb_master_in.ipb_rdata <= x"00000" & Source_ID(0);
1417  when "01000" => ipb_master_in.ipb_rdata <= x"000" & OC_OFF & "000" & BCN_OFF;
1418  when "01001" => ipb_master_in.ipb_rdata <= CalibCtrl;
1419  when "01010" => ipb_master_in.ipb_rdata <= mem_stat(31 downto 0);
1420  when "01011" => ipb_master_in.ipb_rdata <= mem_stat(63 downto 32);
1421  when "01100" => ipb_master_in.ipb_rdata <= x"00000" & "00" & ddr_pa;
1422  when "01101" => ipb_master_in.ipb_rdata <= x"000" & "000" & mon_evt_wc(15 downto 0) & '0';
1423  when "01110" => ipb_master_in.ipb_rdata <= mon_evt_cnt;
1424  when "01111" => ipb_master_in.ipb_rdata <= x"000" & "000" & mon_evt_wc(31 downto 16) & '0';
1425  when "10000" => ipb_master_in.ipb_rdata <= x"000" & "00" & mon_buf_avl & '1' & '0' & wport_FIFO_full & '0' & wport_rdy & x"0" & '0' & evt_data_rdy;
1426  when "10001" => ipb_master_in.ipb_rdata <= x"00000" & Source_ID(1);
1427  when "10010" => ipb_master_in.ipb_rdata <= x"00000" & Source_ID(2);
1428  when "10100" => ipb_master_in.ipb_rdata <= x"000" & '0' & DataRate(0);
1429  when "10101" => ipb_master_in.ipb_rdata <= x"000" & '0' & DataRate(1);
1430  when "10110" => ipb_master_in.ipb_rdata <= x"000" & '0' & DataRate(2);
1431  when "10111" => ipb_master_in.ipb_rdata <= x"000000" & LiveTime;
1432  when "11000" => ipb_master_in.ipb_rdata <= x"000" & fake_length;
1433  when "11001" => ipb_master_in.ipb_rdata <= x"00" & "000" & TTS_coded & state & pattern & x"0" & '0' & TTS_RQST;
1434  when "11010" => ipb_master_in.ipb_rdata <= x"00000" & TTS_disable;
1435  when "11011" => ipb_master_in.ipb_rdata <= x"00000" & trig_BX(11 downto 0);
1436  when "11100" => ipb_master_in.ipb_rdata <= LocalL1A_cfg;
1437  when "11101" => ipb_master_in.ipb_rdata <= x"000" & "000" & mon_evt_wc(47 downto 32) & '0';
1438  when "11110" => ipb_master_in.ipb_rdata <= DNA(31 downto 0);
1439  when "11111" => ipb_master_in.ipb_rdata <= "0000000" & DNA(56 downto 32);
1440  when others => ipb_master_in.ipb_rdata <= (others => '0');
1441  end case;
1442  else
1443  case ipb_master_out.ipb_addr(4 downto 0) is
1444  when "00000" => ipb_master_in.ipb_rdata <= not SN(7 downto 0) & not SN(8) & status_l;
1445  when "00001" => ipb_master_in.ipb_rdata <= K7version & conf;
1446  when "00010" => ipb_master_in.ipb_rdata <= mon_ctrl;
1447  when "00011" => ipb_master_in.ipb_rdata <= IgnoreDAQ & SFP_down_l & AMC_Ready & Dis_pd & EnSFP(2 downto 0) & AMC_en;
1448  when "00100" => ipb_master_in.ipb_rdata <= LSC_ID & TxDisable_i & SFP_status_l;
1449  when "00101" => ipb_master_in.ipb_rdata <= AMC_status_l;
1450  when "00110" => ipb_master_in.ipb_rdata <= x"0" & BC0_lock & x"0" & BX_offset2SC;
1451  when "00111" => ipb_master_in.ipb_rdata <= x"00000" & Source_ID(0);
1452  when "01000" => ipb_master_in.ipb_rdata <= x"000" & OC_OFF & "000" & BCN_OFF;
1453  when "01001" => ipb_master_in.ipb_rdata <= CalibCtrl;
1454  when "01010" => ipb_master_in.ipb_rdata <= mem_stat(31 downto 0);
1455  when "01011" => ipb_master_in.ipb_rdata <= mem_stat(63 downto 32);
1456  when "01100" => ipb_master_in.ipb_rdata <= x"00000" & "00" & ddr_pa;
1457  when "01101" => ipb_master_in.ipb_rdata <= x"000" & "000" & mon_evt_wc(15 downto 0) & '0';
1458  when "01110" => ipb_master_in.ipb_rdata <= mon_evt_cnt;
1459  when "01111" => ipb_master_in.ipb_rdata <= x"000" & "000" & mon_evt_wc(31 downto 16) & '0';
1460  when "10000" => ipb_master_in.ipb_rdata <= x"000" & "00" & mon_buf_avl & '1' & '0' & wport_FIFO_full & '0' & wport_rdy & x"0" & '0' & evt_data_rdy;
1461  when "10001" => ipb_master_in.ipb_rdata <= x"00000" & Source_ID(1);
1462  when "10010" => ipb_master_in.ipb_rdata <= x"00000" & Source_ID(2);
1463  when "10100" => ipb_master_in.ipb_rdata <= x"000" & '0' & DataRate_l(0);
1464  when "10101" => ipb_master_in.ipb_rdata <= x"000" & '0' & DataRate_l(1);
1465  when "10110" => ipb_master_in.ipb_rdata <= x"000" & '0' & DataRate_l(2);
1466  when "10111" => ipb_master_in.ipb_rdata <= x"000000" & LiveTime_l;
1467  when "11000" => ipb_master_in.ipb_rdata <= x"000" & fake_length;
1468  when "11001" => ipb_master_in.ipb_rdata <= x"00" & "000" & TTS_coded & state & pattern & x"00";
1469  when "11010" => ipb_master_in.ipb_rdata <= x"00000" & TTS_disable;
1470  when "11011" => ipb_master_in.ipb_rdata <= x"00000" & trig_BX(11 downto 0);
1471  when "11100" => ipb_master_in.ipb_rdata <= LocalL1A_cfg;
1472  when "11101" => ipb_master_in.ipb_rdata <= x"000" & "000" & mon_evt_wc(47 downto 32) & '0';
1473  when "11110" => ipb_master_in.ipb_rdata <= DNA(31 downto 0);
1474  when "11111" => ipb_master_in.ipb_rdata <= "0000000" & DNA(56 downto 32);
1475  when others => ipb_master_in.ipb_rdata <= (others => '0');
1476  end case;
1477  end if;
1478  else
1479  ipb_master_in.ipb_rdata <= AMC_data or TTC_cntr_data or I2C_data or sysmon_data or SFP_data or ttc_data or HCAL_trig_data;
1480  end if;
1481 end process;
1482 rst_cntr <= cmd(1) or cmd(0);
1483 ttc_resync <= ttc_soft_reset;
1484 process(sysClk)
1485 begin
1486  if(sysClk'event and sysClk = '1')then
1487  if(Cntr2ms(18 downto 17) = "11" and Cntr2ms(14) = '1')then
1488  Cntr2ms <= (others => '0');
1489  LiveTimeCntr <= (others => '0');
1490  LiveTime <= '0' & LiveTimeCntr(18 downto 12);
1491  DataRateCntr <= (others => (others => '0'));
1492  DataRate <= DataRateCntr;
1493  else
1494  Cntr2ms <= Cntr2ms + 1;
1495  if(state = x"8")then
1496  LiveTimeCntr <= LiveTimeCntr + 1;
1497  end if;
1498  for i in 0 to 2 loop
1499  if(evt_data_we(i) = '1')then
1500  DataRateCntr(i) <= DataRateCntr(i) + 1;
1501  end if;
1502  end loop;
1503  end if;
1504  end if;
1505 end process;
1506 process(sysClk,reset)
1507 begin
1508  if(reset = '1')then
1509  TTS_wait <= (others => '0');
1510  elsif(sysClk'event and sysClk = '1')then
1511  if(ttc_resync = '1')then
1512  TTS_wait <= (others => '0');
1513  elsif(TTS_wait(20) = '0' and sync_lost = '0' and AllEventBuilt = '1')then
1514  TTS_wait <= TTS_wait + 1;
1515  end if;
1516  end if;
1517 end process;
1518 process(sysClk)
1519 begin
1520  if(sysClk'event and sysClk = '1')then
1521  if(flavor = "G2" or conf(1) = '0' or conf(9) = '0')then
1522  DAQ_bp <= '0';
1523  else
1524  DAQ_bp <= or_reduce(EnSFP(2 downto 0) and (evt_buf_full or SFP_down));
1525  end if;
1526  end if;
1527 end process;
1528 process(sysClk,reset)
1529 begin
1530  if(reset = '1')then
1531  state <= x"4";
1532  elsif(sysClk'event and sysClk = '1')then
1533  if(run = '0' and conf(12) = '1')then
1534  state <= pattern;
1535  elsif(run = '0')then
1536  state <= x"4"; -- changed upon request starting version 0x3023
1537  elsif(ttc_resync = '1')then
1538  state <= x"4";
1539  else
1540  case state is
1541  when x"8" | x"9" | x"a" | x"b" => -- Ready
1542  if(TTS_coded(4) = '1')then
1543  state <= x"f";
1544  elsif(TTS_coded(3) = '1')then
1545  state <= x"c";
1546  elsif(sync_lost = '1' or TTS_coded(2) = '1')then
1547  state <= x"2";
1548  elsif(L1Aovfl_warning = '1' or evn_fifo_full = '1' or rate_OFWp = '1' or TTS_coded(1) = '1' or TTS_coded(0) = '1')then
1549  if(DAQ_bp = '1')then
1550  state <= x"6";
1551  else
1552  state <= x"1";
1553  end if;
1554  else
1555  state(3 downto 2) <= "10";
1556  state(1) <= (TTS_RQST(2) or TTS_RQST(1)) and conf(9);
1557  state(0) <= (TTS_RQST(2) or (not TTS_RQST(1) and TTS_RQST(0))) and conf(9);
1558  end if;
1559  when x"1" | x"6" => -- OFW
1560  if(TTS_coded(4) = '1')then
1561  state <= x"f";
1562  elsif(TTS_coded(3) = '1')then
1563  state <= x"c";
1564  elsif(sync_lost = '1' or TTS_coded(2) = '1')then
1565  state <= x"2";
1566  elsif(evn_fifo_full = '1' or rate_OFWp = '1' or TTS_coded(1) = '1')then
1567  state <= x"4";
1568  elsif(L1Aovfl_warning = '0' and rate_OFWp = '0' and TTS_coded(0) = '0')then
1569  state(3 downto 2) <= "10";
1570  state(1) <= (TTS_RQST(2) or TTS_RQST(1)) and conf(9);
1571  state(0) <= (TTS_RQST(2) or (not TTS_RQST(1) and TTS_RQST(0))) and conf(9);
1572  elsif(DAQ_bp = '1')then
1573  state <= x"6";
1574  else
1575  state <= x"1";
1576  end if;
1577  when x"4" => -- Busy
1578  if(TTS_wait(20) = '0')then
1579  elsif(TTS_coded(4) = '1')then
1580  state <= x"f";
1581  elsif(TTS_coded(3) = '1')then
1582  state <= x"c";
1583  elsif(sync_lost = '1' or TTS_coded(2) = '1')then
1584  state <= x"2";
1585  elsif(evn_fifo_full = '0' and rate_OFWp = '0' and TTS_coded(1) = '0')then
1586  if(DAQ_bp = '1')then
1587  state <= x"6";
1588  else
1589  state <= x"1";
1590  end if;
1591  end if;
1592 -- when others => null; -- x"0" or x"f" disconnected, x"2" OOS, x"c" error
1593  when others =>
1594  if(IgnoreDAQ = '1')then
1595  if(TTS_coded(4) = '1')then
1596  state <= x"f";
1597  elsif(TTS_coded(3) = '1')then
1598  state <= x"c";
1599  elsif(TTS_coded(2) = '1')then
1600  state <= x"2";
1601  elsif(TTS_coded(1) = '1')then
1602  state <= x"4";
1603  else
1604  state <= x"1";
1605  end if;
1606  end if;
1607  end case;
1608  end if;
1609  end if;
1610 end process;
1611 ipb_master_in.ipb_err <= '0';
1612 i_AMC_if: AMC_if PORT MAP(
1613  sysclk => sysclk,
1614  ipb_clk => ipb_clk,
1615  clk125 => clk125,
1616  DRPclk => DRPclk,
1617  reset => AMC_reset,
1618  DB_cmd => DB_cmd,
1619  ReSync => ttc_resync,
1620  GTXreset => amc_GTXreset,
1621  resetCntr => rst_cntr,
1622  AllEventBuilt => AllEventBuilt,
1623  run => run,
1624  en_inject_err => conf(10),
1625  Dis_pd => Dis_pd,
1626  enSFP => enSFP,
1627  test => conf(7),
1628  NoReSyncFake => conf(11),
1629  WaitMonBuf => WaitMonBuf,
1630  fake_length => fake_length,
1631  en_localL1A => conf(2),
1632  T1_version => K7version(7 downto 0),
1633  Source_ID => Source_ID,
1634  AMC_en => AMC_en,
1635  TTS_disable => TTS_disable,
1636  AMC_Ready => AMC_Ready,
1637  TTC_lock => TTC_lock,
1638  BC0_lock => BC0_lock,
1639  AMC_REFCLK_P => AMC_REFCLK_P,
1640  AMC_REFCLK_N => AMC_REFCLK_N,
1641  AMC_RXN => AMC_RXN,
1642  AMC_RXP => AMC_RXP,
1643  AMC_TXN => AMC_TXN,
1644  AMC_TXP => AMC_TXP,
1645  AMC_status => AMC_status,
1646  evt_data => EventData,
1647  evt_data_we => evt_data_we,
1648  evt_buf_full => evt_buf_full,
1649  evt_data_re => evt_data_re,
1650  evt_data_rdy => evt_data_rdy,
1651  ddr_pa => ddr_pa,
1652  MonBuf_empty => MonBuf_empty,
1653  mon_evt_wc => mon_evt_wc,
1654  mon_ctrl => mon_ctrl,
1655  mon_buf_avl => mon_buf_avl,
1656  TCPbuf_avl => TCPbuf_avl,
1657  buf_rqst => EventBuf_rqst,
1658  ipb_write => ipb_master_out.ipb_write ,
1659  ipb_strobe => ipb_master_out.ipb_strobe ,
1660  ipb_addr => ipb_master_out.ipb_addr ,
1661  ipb_wdata => ipb_master_out.ipb_wdata ,
1662  ipb_rdata => AMC_data,
1663  ipb_ack => AMC_ack,
1664  TTC_clk => TTC_clk,
1665  TTC_LOS => TTC_LOS,
1666  BC0 => BC0_dl ,
1667  ttc_evcnt_reset => ttc_evcnt_reset,
1668  event_number_avl => event_number_avl,
1669  event_number => event_number,
1670  evn_buf_full => evn_fifo_full,
1671  ovfl_warning => L1Aovfl_warning,
1672  TrigData => TrigData,
1673  TTS_RQST => TTS_RQST,
1674  TTS_coded => TTS_coded
1675  );
1676 AMC_reset <= not sys_lock or cmd(0) or cmd0_dl(1);
1677 amc_GTXreset <= wr_AMC_en or conf7_fall or not sys_lock;
1678 sys_lock_n <= not sys_lock;
1679 g_DAQLSC_if : if(flavor /= "G2") generate
1680  i_DAQLSC_if: DAQLSCXG_if PORT MAP(
1681  sysclk => sysclk,
1682  clk125 => clk125,
1683  DRPclk => DRPclk,
1684  reset => AMC_reset,
1685  daq_reset => lsc_reset,
1686  gtx_reset => lsc_GTXreset,
1687  rstCntr => rst_cntr,
1688  test => '0',
1689  DB_cmd => DB_cmd,
1690  Dis_pd => Dis_pd,
1691  enSFP => enSFP,
1692  SFP_ABS => SFP_ABS(2 downto 0),
1693  LSC_ID => LSC_ID,
1694  SFP_down => SFP_down,
1695  inc_ddr_pa => inc_ddr_pa,
1696  evt_data_rdy => evt_data_rdy,
1697  EventData_in => EventData,
1698  EventData_we => evt_data_we,
1699  EventData_re => evt_data_re,
1700  evt_buf_full => evt_buf_full,
1701  buf_rqst => EventBuf_rqst,
1702  WaitMonBuf => WaitMonBuf,
1703  MonBufOverWrite => conf(13),
1704  TCPBuf_avl => TCPbuf_avl,
1705  MonBuf_avl => mon_buf_avl,
1706  MonBuf_empty => MonBuf_empty,
1707  MonBufOvfl => MonBufOvfl,
1708  mon_evt_cnt => mon_evt_cnt,
1709  WrtMonBlkDone => WrtMonBlkDone,
1710  WrtMonEvtDone => WrtMonEvtDone,
1711  wport_rdy => wport_rdy,
1712  wport_FIFO_full => wport_FIFO_full,
1713  EventBufAddr_we => EventBufAddr_we,
1714  EventBufAddr => EventBufAddr,
1715  SFP0_RXN => SFP0_RXN,
1716  SFP0_RXP => SFP0_RXP,
1717  SFP1_RXN => SFP1_RXN,
1718  SFP1_RXP => SFP1_RXP,
1719  SFP2_RXN => SFP2_RXN,
1720  SFP2_RXP => SFP2_RXP,
1721  SFP0_TXN => SFP0_TXN,
1722  SFP0_TXP => SFP0_TXP,
1723  SFP1_TXN => SFP1_TXN,
1724  SFP1_TXP => SFP1_TXP,
1725  SFP2_TXN => SFP2_TXN,
1726  SFP2_TXP => SFP2_TXP,
1727  SFP_REFCLK_P => SFP_REFCLK_P,
1728  SFP_REFCLK_N => SFP_REFCLK_N,
1729  GbE_REFCLK => GbE_REFCLK,
1730  ipb_clk => ipb_clk,
1731  ipb_write => ipb_master_out.ipb_write ,
1732  ipb_strobe => ipb_master_out.ipb_strobe ,
1733  ipb_addr => ipb_master_out.ipb_addr ,
1734  ipb_wdata => ipb_master_out.ipb_wdata ,
1735  ipb_rdata => SFP_data,
1736  ipb_ack => SFP_ack
1737  );
1738  lsc_reset <= lsc_start or cmd(2) or cmd2_dl(1);
1739  lsc_GTXreset <= lsc_start or cmd2_dl(0);
1740 end generate g_DAQLSC_if;
1741 WaitMonBuf <= conf(14) when flavor /= "G2" else '1' when conf(14) = '1' and (conf(1) = '0' or enSFP(2 downto 0) = "000") else '0';
1742 g_TCPIP_if : if(flavor = "G2") generate
1743  i_TCPIP_if: TCPIP_if PORT MAP(
1744  sysclk => sysclk,
1745  DRPclk => DRPclk,
1746  reset => AMC_reset,
1747  TCPreset => TCPIP_GTXreset ,
1748  rstCntr => rst_cntr,
1749  test => conf(9),
1750  SN => SN,
1751  Dis_pd => Dis_pd,
1752  enSFP => enSFP,
1753  SFP_down => SFP_down,
1754  inc_ddr_pa => inc_ddr_pa,
1755  evt_data_rdy => evt_data_rdy,
1756  EventData_in => EventData,
1757  EventData_we => evt_data_we,
1758  EventData_re => evt_data_re,
1759  evt_buf_full => evt_buf_full,
1760  buf_rqst => EventBuf_rqst,
1761  TCPBuf_avl => TCPbuf_avl,
1762  MonBuf_avl => mon_buf_avl,
1763  WaitMonBuf => WaitMonBuf,
1764  MonBufOverWrite => conf(13),
1765  MonBuf_empty => MonBuf_empty,
1766  MonBufOvfl => MonBufOvfl,
1767  mon_evt_cnt => mon_evt_cnt,
1768  WrtMonBlkDone => WrtMonBlkDone,
1769  WrtMonEvtDone => WrtMonEvtDone,
1770  KiloByte_toggle => KiloByte_toggle,
1771  EoB_toggle => EoB_toggle,
1772  wport_rdy => wport_rdy,
1773  wport_FIFO_full => wport_FIFO_full,
1774  EventBufAddr_we => EventBufAddr_we,
1775  EventBufAddr => EventBufAddr,
1776  TCPclk => TCPclk,
1777  TCP_dout => TCP_din,
1778  TCP_channel => TCP_channel,
1779  TCP_we => TCP_we,
1780  TCP_wcount => TCP_wcount,
1781  TCP_raddr => TCP_raddr,
1782  TCP_length => TCP_length,
1783  TCP_rrqst => TCP_rrqst,
1784  TCP_rack => TCP_rack,
1785  TCP_din => TCP_dout,
1786  TCP_din_type => TCP_dout_type,
1787  TCP_din_valid => TCP_dout_valid ,
1788  TCP_lastword => TCP_lastword,
1789  SFP0_RXN => SFP0_RXN,
1790  SFP0_RXP => SFP0_RXP,
1791  SFP1_RXN => SFP1_RXN,
1792  SFP1_RXP => SFP1_RXP,
1793  SFP2_RXN => SFP2_RXN,
1794  SFP2_RXP => SFP2_RXP,
1795  SFP0_TXN => SFP0_TXN,
1796  SFP0_TXP => SFP0_TXP,
1797  SFP1_TXN => SFP1_TXN,
1798  SFP1_TXP => SFP1_TXP,
1799  SFP2_TXN => SFP2_TXN,
1800  SFP2_TXP => SFP2_TXP,
1801  SFP_REFCLK_N => SFP_REFCLK_N,
1802  SFP_REFCLK_P => SFP_REFCLK_P,
1803  cs_out => open,
1804  ipb_clk => ipb_clk,
1805  ipb_write => ipb_master_out.ipb_write ,
1806  ipb_strobe => ipb_master_out.ipb_strobe ,
1807  ipb_addr => ipb_master_out.ipb_addr ,
1808  ipb_wdata => ipb_master_out.ipb_wdata ,
1809  ipb_rdata => SFP_data
1810  );
1811 TCPIP_GTXreset <= wr_AMC_en or not sys_lock or cmd(4) or cmd0_dl(0);
1812 end generate g_TCPIP_if;
1813 process(DRPclk, sys_lock)
1814 begin
1815  if(sys_lock = '0')then
1816  lsc_start <= '1';
1817  elsif(DRPclk'event and DRPclk = '1')then
1818  if(CLK_rdy = '1')then
1819  lsc_start <= '0';
1820  end if;
1821  end if;
1822 end process;
1823 i_sysmon_if: sysmon_if PORT MAP(
1824  DRPclk => ipb_clk,
1825  DB_cmd => DB_cmd,
1826  SN => SN,
1827  VAUXN_IN => VAUXN,
1828  VAUXP_IN => VAUXP,
1829  addr => ipb_master_out.ipb_addr(15 downto 0),
1830  data => sysmon_data,
1831  device_temp => device_temp,
1832  ALM => ALM,
1833  OT => OT
1834  );
1835 process(ipb_clk)
1836 begin
1837  if(ipb_clk'event and ipb_clk = '1')then
1838  newIPADDRSyncRegs <= newIPADDRSyncRegs(1 downto 0) & newIPADDR;
1839  rst_ipbus <= not newIPADDRSyncRegs(2) and newIPADDR;
1840  end if;
1841 end process;
1842 i_TTC_cntr: TTC_cntr PORT MAP(
1843  sysclk => sysclk ,
1844  clk125 => clk125,
1845  ipb_clk => ipb_clk,
1846  reset => reset,
1847  rst_cntr => rst_cntr,
1848  DB_cmd => DB_cmd ,
1849  inc_serr => inc_serr,
1850  inc_derr => inc_derr,
1851  inc_bcnterr => inc_bcnterr,
1852  inc_l1ac => inc_l1ac,
1853  run => run,
1854  state => state,
1855  ttc_resync => ttc_resync,
1856  ipb_addr => ipb_master_out.ipb_addr (15 downto 0),
1857  ipb_rdata => TTC_cntr_data
1858  );
1859 i_DNA_PORT : DNA_PORT
1860  generic map (
1861  SIM_DNA_VALUE => X"00123456789abcd" -- Specifies a sample 57-bit DNA value for simulation
1862  )
1863  port map (
1864  DOUT => DNA_out, -- 1-bit output: DNA output data.
1865  CLK => ipb_clk, -- 1-bit input: Clock input.
1866  DIN => '0', -- 1-bit input: User data input pin.
1867  READ => load_DNA, -- 1-bit input: Active high load DNA, active low read input.
1868  SHIFT => shift_DNA(1) -- 1-bit input: Active high shift enable input.
1869  );
1870 process(ipb_clk)
1871 begin
1872  if(ipb_clk'event and ipb_clk = '1')then
1873  load_DNA <= not sys_lock;
1874  if(sys_lock = '0')then
1875  shift_DNA(0) <= '0';
1876  elsif(load_DNA = '1')then
1877  shift_DNA(0) <= '1';
1878  elsif(shift_DNA(2) = '1' and or_reduce(DNA_cntr(5 downto 1)) = '0')then
1879  shift_DNA(0) <= '0';
1880  end if;
1881  shift_DNA(2) <= shift_DNA(0);
1882  if(shift_DNA(2) = '1')then
1883  DNA_cntr <= DNA_cntr - 1;
1884  elsif(shift_DNA(0) = '1')then
1885  DNA_cntr <= "110111";
1886  end if;
1887  if(shift_DNA(2) = '1')then
1888  DNA <= DNA(55 downto 0) & DNA_OUT;
1889  end if;
1890  end if;
1891 end process;
1892 process(ipb_clk)
1893 begin
1894  if(ipb_clk'event and ipb_clk = '0')then
1895  shift_DNA(1) <= shift_DNA(0);
1896  end if;
1897 end process;
1898 end Behavioral;
1899 
Generated on Wed Apr 18 2018 10:55:29 for AMC13 by   doxygen 1.8.1