AMC13
Firmwares for the different applications of the AMC13 uTCA board made at Boston University
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slink_opt.vhd
1 ------------------------------------------------------
2 -- SLINK Optical interface sender
3 --
4 -- Ver 1.00
5 --
6 -- Dominique Gigi Feb 2012
7 ------------------------------------------------------
8 -- INstatiate the differents components for sender optical SLINK
9 --
10 --
11 --
12 ------------------------------------------------------
13 LIBRARY ieee;
14 -- LIBRARY altera_mf;
15 -- LIBRARY altera;
16 
17 
18 USE ieee.std_logic_1164.all;
19 use ieee.numeric_std.all;
20 use ieee.std_logic_unsigned.all;
21 -- LIBRARY lpm;
22 -- USE lpm.lpm_components.all;
23 -- USE altera_mf.altera_mf_components.all;
24 -- USE altera.altera_primitives_components.all;
25 
26 entity SLINK_opt is
27 port (
28  reset : in std_logic;
29  -- FED interface
30  SYS_CLK : in std_logic;
31  LINKWe : in std_logic;
32  LINKCtrl : in std_logic;
33  LINKData : in std_logic_vector(63 downto 0);
34  src_ID : in std_logic_vector(15 downto 0);
35  inject_err : in std_logic_vector(17 downto 0);
36  read_CE : in std_logic;
37  Addr : in std_logic_vector(15 downto 0);
38  status_data : out std_logic_vector(63 downto 0);
39  LINKDown : out std_logic;
40  LINK_LFF : out std_logic;
41 
42  -- interface SERDES
43  clock : in std_logic;
44  serdes_init : in std_logic;
45  SD_Data_o : out std_logic_vector(31 downto 0);
46  SD_Kb_o : out std_logic_vector(3 downto 0);
47  clock_r : in std_logic;
48  SD_Data_i : in std_logic_vector(31 downto 0);
49  SD_Kb_i : in std_logic_vector(3 downto 0);
50  Serdes_status : in std_logic_vector(31 downto 0)
51 
52  );
53 end SLINK_opt;
54 
55 architecture behavioral of SLINK_opt is
56 
57 component fed_itf
58 generic (generator : boolean := true);
59 port (
60  reset_sysCLK : in std_logic;
61  Greset_sysCLK : in std_logic;
62  sys_clk : in std_logic;
63  LinkWe : in STD_LOGIC;
64  LinkCtrl : in STD_LOGIC;
65  LinkData : in STD_LOGIC_VECTOR (63 downto 0);
66  LinkAlmostFull : out STD_LOGIC;
67  LinkDown : out STD_LOGIC;
68  src_ID : in STD_LOGIC_VECTOR (15 downto 0);
69  inject_err : in STD_LOGIC_VECTOR (17 downto 0);
70  read_ce : in STD_LOGIC;
71  addr : in STD_LOGIC_VECTOR (15 downto 0);
72  status_data : out STD_LOGIC_VECTOR (63 downto 0);
73  reset_CLK : in std_logic;
74  Greset_CLK : in std_logic;
75  clock : in std_logic; -- clock from internal logic
76  block_free : in std_logic; -- almost one block is free
77  data_fed : out std_logic_vector(63 downto 0);
78  block_sz_fed : out std_logic_vector(15 downto 0);
79  wr_ena : out std_logic;
80  start_evt : out std_logic;
81  stop_evt : out std_logic;
82  end_blk_fed : out std_logic;
83  wr_cmd : in std_logic;
84  func : in std_logic_vector(31 downto 0);
85  data_wr : in std_logic_vector(31 downto 0);
86  data_rd : out std_logic_vector(63 downto 0);
87  cnt_evt : out std_logic; -- pulse for each event (on sys_clk)
88  cnt_pckt_rcv : in std_logic_vector(31 downto 0);
89  cnt_pckt_snd : in std_logic_vector(31 downto 0);
90  -- status
91  retransmit_ena : in std_logic;
92  status_state_build_p : in std_logic_vector(31 downto 0);
93  status_state_core : in std_logic_vector(31 downto 0);
94  Serdes_status : in std_logic_vector(31 downto 0)
95  );
96 end component;
97 
98 component Core_logic
99 port (
100  reset_clk : in std_logic;
101  Greset_clk : in std_logic;
102  clock : in std_logic;
103  -- interface from the FED block
104  data_fed : in std_logic_vector(63 downto 0);
105  wen : in std_logic;
106  start_evt : in std_logic;
107  stop_evt : in std_logic;
108  block_sz_fed : in std_logic_vector(15 downto 0);
109  end_blk_fed : in std_logic;
110  block_free : out std_logic;
111  src_ID : in std_logic_vector(15 downto 0);
112  req_reset_resync : out std_logic;
113  -- interface to the SERDES OUT (send part)
114  start_pckt : out std_logic; -- trigger the packet send
115  init_pckt : out std_logic; -- indicates that the packet is a Init packet
116  ack_pckt : out std_logic; -- indicates that the packet is a acknoldge packet
117  data_pckt : out std_logic; -- indicates that the packet is a data packet
118  data_evt : out std_logic_vector(63 downto 0); --data for data packet
119  status : out std_logic_vector(63 downto 0); --status data for acknowledge packet
120  card_ID : out std_logic_vector(15 downto 0); -- CARD_ID
121  Seq_nb : out std_logic_vector(30 downto 0); -- sequence number
122  len_pckt : out std_logic_vector(15 downto 0); -- length of the packet (for data packet only) other 0
123  cmd : out std_logic_vector(63 downto 0); -- command bit for data packet only
124  rd_dt : in std_logic;
125  end_snd_pckt : in std_logic;
126  idle_state : in std_logic;
127  serdes_init : in std_logic;
128  -- interface to the SERDES IN (receiver part)
129  cmd_rcv : in std_logic_vector(31 downto 0); -- command from MOL
130  data_rcv : in std_logic_vector(31 downto 0); -- data from MOL
131  ena_cmd : in std_logic; -- validate command
132  sta_dt : in std_logic_vector(63 downto 0); -- value return in an ack packet
133  ena_ack : in std_logic;
134  seqnb_rcv : in std_logic_vector(30 downto 0); -- seq numb from cmd (need an ack)
135  card_ID_rcv : in std_logic_vector(15 downto 0);
136  retransmit : out std_logic;
137  wr_cmd : out std_logic;
138  func : out std_logic_vector(31 downto 0);
139  data_wr : out std_logic_vector(31 downto 0);
140  data_rd : in std_logic_vector(63 downto 0);
141  status_state : out std_logic_vector(31 downto 0)
142  );
143 end component;
144 
145 component build_pckt_s
146 port (
147  reset_CLK : in std_logic;
148  Greset_CLK : in std_logic;
149  clock : in std_logic;
150 
151  start_pckt : in std_logic; -- trigger the packet send
152  init_pckt : in std_logic; -- indicates that the packet is a Init packet
153  ack_pckt : in std_logic; -- indicates that the packet is a acknoldge packet
154  data_pckt : in std_logic; -- indicates that the packet is a data packet
155  data_evt : in std_logic_vector(63 downto 0); --data for data packet
156  status : in std_logic_vector(63 downto 0); --status data for acknowledge packet
157  card_ID : in std_logic_vector(15 downto 0); -- CARD_ID
158  Seq_nb : in std_logic_vector(30 downto 0); -- sequence number
159  len_pckt : in std_logic_vector(15 downto 0); -- length of the packet (for data packet only) other 0
160  cmd : in std_logic_vector(63 downto 0); -- command bit for data packet only
161  error_gen : in std_logic_vector(3 downto 0);
162  rd_dt : out std_logic; -- request data for data packet only
163  end_pckt : out std_logic;
164 
165  datao : out std_logic_vector(31 downto 0); --- data and K bit send to SERDES
166  k_byte : out std_logic_vector( 3 downto 0);
167  idle_state : out std_logic;
168  cnt_pckt_snd : out std_logic_vector(31 downto 0);
169  status_state : out std_logic_vector(31 downto 0) );
170 end component;
171 
172 component rcv_pckt_s
173 port (
174  reset_clk : in std_logic;
175  reset_clkT : in std_logic;
176  Greset_clk : in std_logic;
177  Greset_clkT : in std_logic;
178  clock : in std_logic;
179  clock_t : in std_logic;
180 
181  datai : in std_logic_vector(31 downto 0); --- data and K bit send from SERDES
182  k_byte : in std_logic_vector( 3 downto 0);
183 
184  error_gen : in std_logic;
185 
186  cmd : out std_logic_vector(31 downto 0); -- command from MOL
187  data : out std_logic_vector(31 downto 0); -- data from MOL
188  ena_cmd : out std_logic; -- validate command
189 
190  status : out std_logic_vector(63 downto 0); -- value return from read command request
191  seqnb : out std_logic_vector(30 downto 0); -- seq numb from cmd (need an ack)
192  ena_ack : out std_logic;
193 
194  card_ID : out std_logic_vector(15 downto 0);
195  cnt_pckt_rcv : out std_logic_vector(31 downto 0) );
196 end component;
197 
198 component swapp_byte
199 port (
200  data_i : in std_logic_vector(31 downto 0);
201  ctrl_i : in std_logic_vector(3 downto 0);
202 
203  data_o : out std_logic_vector(31 downto 0);
204  ctrl_o : out std_logic_vector(3 downto 0)
205  );
206 end component;
207 
208 component reset_resync
209 port (
210  reset : in std_logic;
211  clock : in std_logic;
212  Reset_sync : out std_logic
213  );
214 end component;
215 
216 SIGNAL data_rcv : std_logic_vector(31 downto 0);
217 SIGNAL ena_cmd : std_logic;
218 SIGNAL sta_dt : std_logic_vector(63 downto 0);
219 SIGNAL ena_ack : std_logic;
220 SIGNAL seqnb_rcv : std_logic_vector(30 downto 0);
221 SIGNAL idle_state : std_logic;
222 SIGNAL end_snd_pckt : std_logic;
223 SIGNAL rd_dt : std_logic;
224 SIGNAL cmd_rcv : std_logic_vector(31 downto 0);
225 SIGNAL cmd : std_logic_vector(63 downto 0);
226 SIGNAL len_pckt : std_logic_vector(15 downto 0);
227 SIGNAL Seq_nb : std_logic_vector(30 downto 0);
228 SIGNAL card_ID_rcv : std_logic_vector(15 downto 0);
229 SIGNAL card_ID_snd : std_logic_vector(15 downto 0);
230 SIGNAL status : std_logic_vector(63 downto 0);
231 SIGNAL data_evt : std_logic_vector(63 downto 0);
232 SIGNAL data_pckt : std_logic;
233 SIGNAL ack_pckt : std_logic;
234 SIGNAL init_pckt : std_logic;
235 SIGNAL start_pckt : std_logic;
236 SIGNAL end_blk_fed : std_logic;
237 SIGNAL stop_evt : std_logic;
238 SIGNAL start_evt : std_logic;
239 SIGNAL wr_ena : std_logic;
240 SIGNAL block_sz_fed : std_logic_vector(15 downto 0);
241 SIGNAL data_fed : std_logic_vector(63 downto 0);
242 SIGNAL block_free : std_logic;
243  -- interface slave to read and write
244 SIGNAL wr_cmd : std_logic;
245 SIGNAL func : std_logic_vector(31 downto 0);
246 SIGNAL data_wr : std_logic_vector(31 downto 0);
247 SIGNAL data_rd : std_logic_vector(63 downto 0);
248 
249 SIGNAL cnt_pckt_rcv : std_logic_vector(31 downto 0);
250 SIGNAL cnt_pckt_snd : std_logic_vector(31 downto 0);
251 SIGNAL status_state_build_p : std_logic_vector(31 downto 0);
252 SIGNAL status_state_core : std_logic_vector(31 downto 0);
253 
254 SIGNAL DATAo_unswapped : std_logic_vector(31 downto 0);
255 SIGNAL CTRLo_unswapped : std_logic_vector( 3 downto 0);
256 SIGNAL DATAi_unswapped : std_logic_vector(31 downto 0);
257 SIGNAL CTRLi_unswapped : std_logic_vector( 3 downto 0);
258 SIGNAL req_reset_resync : std_logic;
259 SIGNAL retransmit : std_logic;
260 
261 --
262 SIGNAL reg_datai : std_logic_vector(63 downto 0);
263 SIGNAL req_uctrli : std_logic;
264 SIGNAL req_weni : std_logic;
265 
266 SIGNAL G_reset : std_logic;
267 
268 
269 SIGNAL GRst_sysckl : std_logic;
270 SIGNAL GRst_T_ckl : std_logic;
271 SIGNAL GRst_R_ckl : std_logic;
272 SIGNAL Rst_sysckl : std_logic;
273 SIGNAL Rst_T_ckl : std_logic;
274 SIGNAL Rst_R_ckl : std_logic;
275 SIGNAL LINKDown_s : std_logic;
276 --******************************************************************
277 --******************* BEGIN **************************************
278 --******************************************************************
279 begin
280 
281 --#################################################
282 -- reset resync
283 --#################################################
284 -- reset coming form FED
285 Rst_sysckl_i1:reset_resync
286 port map(
287  reset => reset,
288  clock => SYS_CLK,
289  Reset_sync => Rst_sysckl
290  );
291 
292 Rst_T_ckl_i1:reset_resync
293 port map(
294  reset => reset,
295  clock => clock,
296  Reset_sync => Rst_T_ckl
297  );
298 
299 Rst_R_ckl_i1:reset_resync
300 port map(
301  reset => reset,
302  clock => clock_r,
303  Reset_sync => Rst_R_ckl
304  );
305 -- reset coming form FED or from DAQ
306 G_reset <= '0' when reset = '0' or req_reset_resync = '0' else '1';
307 
308 GRst_sysckl_i1:reset_resync
309 port map(
310  reset => G_reset,
311  clock => SYS_CLK,
312  Reset_sync => GRst_sysckl
313  );
314 
315 GRst_T_ckl_i1:reset_resync
316 port map(
317  reset => G_reset,
318  clock => clock,
319  Reset_sync => GRst_T_ckl
320  );
321 
322 GRst_R_ckl_i1:reset_resync
323 port map(
324  reset => G_reset,
325  clock => clock_r,
326  Reset_sync => GRst_R_ckl
327  );
328 --#################################################
329 -- registers FED interface
330 --#################################################
331 process(LINKDown_s,SYS_CLK)
332 begin
333  if LINKDown_s = '0' then
334  req_weni <= '1';
335  elsif rising_edge(SYS_CLK) then
336  reg_datai <= LINKData;
337  req_uctrli <= LINKCtrl;
338  req_weni <= LINKWe;
339  end if;
340 end process;
341 
342 LINKDown <= LINKDown_s;
343 
344 i1:fed_itf
345 port map(
346  reset_sysCLK => Rst_sysckl,
347  Greset_sysCLK => GRst_sysckl,
348  sys_clk => SYS_CLK,
349  LinkWe => req_weni,
350  LinkCtrl => req_uctrli,
351  LinkData => reg_datai,
352  LinkAlmostFull => LINK_LFF,
353  LinkDown => LINKDown_s,
354  src_ID => src_ID,
355  inject_err => inject_err,
356  read_ce => read_CE,
357  addr => Addr,
358  status_data => status_data,
359  reset_CLK => Rst_T_ckl,
360  Greset_CLK => GRst_T_ckl,
361  clock => clock,
362  block_free => block_free,
363  data_fed => data_fed,
364  block_sz_fed => block_sz_fed,
365  wr_ena => wr_ena,
366  start_evt => start_evt,
367  stop_evt => stop_evt,
368  end_blk_fed => end_blk_fed,
369  wr_cmd => wr_cmd,
370  func => func,
371  data_wr => data_wr,
372  data_rd => data_rd,
373  --cnt_evt => cnt_evt,
374  cnt_pckt_rcv => cnt_pckt_rcv,
375  cnt_pckt_snd => cnt_pckt_snd,
376  retransmit_ena => retransmit,
377  status_state_build_p => status_state_build_p,
378  status_state_core => status_state_core,
379  Serdes_status => Serdes_status);
380 
381 i2:Core_logic
382 port map(
383  reset_clk => Rst_T_ckl,
384  Greset_clk => GRst_T_ckl,
385  clock => clock,
386  -- interface from the FED block
387  data_fed => data_fed,
388  wen => wr_ena,
389  start_evt => start_evt,
390  stop_evt => stop_evt,
391  block_sz_fed => block_sz_fed,
392  end_blk_fed => end_blk_fed,
393  block_free => block_free,
394  src_ID => src_ID,
395  req_reset_resync => req_reset_resync,
396  -- interface to the SERDES OUT (send part)
397  start_pckt => start_pckt,
398  init_pckt => init_pckt,
399  ack_pckt => ack_pckt,
400  data_pckt => data_pckt,
401  data_evt => data_evt,
402  status => status,
403  card_ID => card_ID_snd,
404  Seq_nb => Seq_nb,
405  len_pckt => len_pckt,
406  cmd => cmd,
407  rd_dt => rd_dt,
408  end_snd_pckt => end_snd_pckt,
409  idle_state => idle_state,
410  serdes_init => serdes_init,
411  -- interface to the SERDES IN (receiver part)
412  cmd_rcv => cmd_rcv,
413  data_rcv => data_rcv,
414  ena_cmd => ena_cmd,
415  sta_dt => sta_dt,
416  ena_ack => ena_ack,
417  seqnb_rcv => seqnb_rcv,
418  card_ID_rcv => card_ID_rcv,
419  retransmit => retransmit,
420  wr_cmd => wr_cmd,
421  func => func,
422  data_wr => data_wr,
423  data_rd => data_rd,
424  status_state => status_state_core);
425 
426 i3:build_pckt_s
427 port map(
428  reset_CLK => Rst_T_ckl,
429  Greset_CLK => GRst_T_ckl,
430  clock => clock,
431  start_pckt => start_pckt,
432  init_pckt => init_pckt,
433  ack_pckt => ack_pckt,
434  data_pckt => data_pckt,
435  data_evt => data_evt,
436  status => status,
437  card_ID => card_ID_snd,
438  Seq_nb => Seq_nb,
439  len_pckt => len_pckt,
440  cmd => cmd,
441  error_gen => inject_err(4 downto 1),
442  rd_dt => rd_dt,
443  end_pckt => end_snd_pckt,
444 
445  datao => DATAo_unswapped,
446  k_byte => CTRLo_unswapped,
447  idle_state => idle_state,
448  status_state => status_state_build_p,
449  cnt_pckt_snd => cnt_pckt_snd);
450 
451 
452 -- i_swapp:swapp_byte
453 -- port (
454  -- data_i => DATAo_unswapped,
455  -- ctrl_i => CTRLo_unswapped,
456  -- data_o => SD_Data_o,
457  -- ctrl_o => SD_Kb_o
458  -- );
459 
460  SD_Data_o <= DATAo_unswapped;
461  SD_Kb_o <= CTRLo_unswapped;
462 
463 
464 
465  -- i_unswapp:swapp_byte
466 -- port (
467  -- data_i => SD_Data_i,
468  -- ctrl_i => SD_Kb_i,
469  -- data_o => DATAi_unswapped,
470  -- ctrl_o => CTRLi_unswapped
471  -- );
472 
473 DATAi_unswapped <= SD_Data_i;
474 CTRLi_unswapped <= SD_Kb_i;
475 
476 i4:rcv_pckt_s
477 port map(
478  reset_clk => Rst_R_ckl,
479  reset_clkT => Rst_T_ckl,
480  Greset_clk => GRst_R_ckl,
481  Greset_clkT => GRst_T_ckl,
482  clock => clock_r,
483  clock_t => clock,
484  datai => DATAi_unswapped,
485  k_byte => CTRLi_unswapped,
486  error_gen => inject_err(5),
487  cmd => cmd_rcv,
488  data => data_rcv,
489  ena_cmd => ena_cmd,
490  status => sta_dt,
491  ena_ack => ena_ack,
492  seqnb => seqnb_rcv,
493  card_ID => card_ID_rcv,
494  cnt_pckt_rcv => cnt_pckt_rcv);
495 
496 end behavioral;
497 
498 
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