Device Usage Page (device_usage_statistics.html)

This HTML page displays the device usage statistics that will be sent to Xilinx. The file also contains predefined XML tags used to simplify processing.
 
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Software Version and Target Device
Product Version: ISE:10.1.03 (Foundation Simulator) Target Family: spartan3a
OS Platform: NT Target Device: xc3s400a
Project ID (random number) 26951.27637.126 Target Package: ft256
Registration ID 182TANLZJHKZXTUAMZ450J4DT Target Speed: -4
Date Generated Sat Jul 11 06:33:42 2009
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Xors=172
  • 1-bit xor10=3
  • 1-bit xor13=3
  • 1-bit xor2=124
  • 1-bit xor3=12
  • 1-bit xor4=3
  • 1-bit xor5=9
  • 1-bit xor6=9
  • 1-bit xor7=6
  • 4-bit xor2=3
 Comparators=9
  • 16-bit comparator equal=3
  • 16-bit comparator lessequal=1
  • 8-bit comparator not equal=3
  • 9-bit comparator equal=2
 FSMs=1 Registers=1612
  • Flip-Flops=1612
 Counters=55
  • 10-bit up counter=4
  • 11-bit up counter=1
  • 14-bit up counter=1
  • 16-bit updown counter=1
  • 2-bit updown counter=3
  • 3-bit up counter=1
  • 32-bit up counter=1
  • 4-bit up counter=3
  • 4-bit updown counter=7
  • 5-bit down counter=1
  • 5-bit up counter=3
  • 6-bit up counter=1
  • 7-bit up counter=4
  • 8-bit updown counter=4
  • 9-bit up counter=17
  • 9-bit updown counter=3
 Multiplexers=1
  • 36-bit 4-to-1 multiplexer=1
 Adders/Subtractors=24
  • 12-bit adder=9
  • 16-bit adder=1
  • 2-bit adder=1
  • 3-bit subtractor=1
  • 32-bit adder=1
  • 36-bit adder=1
  • 4-bit adder=2
  • 6-bit adder=1
  • 7-bit adder=4
  • 8-bit adder=1
  • 9-bit adder=2
 Accumulators=1
  • 32-bit up accumulator=1
 		MiscellaneousStatistics
  • AGG_BONDED_IO=104
  • AGG_IO=104
  • AGG_SLICE=1849
  • NUM_4_INPUT_LUT=2558
  • NUM_BONDED_DIFFMI=17
  • NUM_BONDED_DIFFMTB=10
  • NUM_BONDED_DIFFSI=17
  • NUM_BONDED_DIFFSTB=10
  • NUM_BONDED_IBUF=3
  • NUM_BONDED_IOB=47
  • NUM_BUFGMUX=9
  • NUM_CYMUX=436
  • NUM_DCM=4
  • NUM_DP_RAM=234
  • NUM_IDDR2_C0=2
  • NUM_IDDR2_C1=6
  • NUM_IOB_FF=39
  • NUM_LUT_RT=292
  • NUM_ODDR2_C0=18
  • NUM_ODDR2_NONE=21
  • NUM_RAM16=19
  • NUM_RAMB16BWE=8
  • NUM_SHIFT=49
  • NUM_SLICEL=1677
  • NUM_SLICEM=172
  • NUM_SLICE_FF=1906
  • NUM_XOR=448
 		NetStatistics
  • NumNets_Active=3892
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BRAMADDR=138
  • NumNodesOfType_Active_BRAMDUMMY=610
  • NumNodesOfType_Active_CLKPIN=1684
  • NumNodesOfType_Active_CNTRLPIN=1703
  • NumNodesOfType_Active_DOUBLE=6777
  • NumNodesOfType_Active_DUMMY=7374
  • NumNodesOfType_Active_DUMMYBANK=144
  • NumNodesOfType_Active_DUMMYESC=28
  • NumNodesOfType_Active_GLOBAL=418
  • NumNodesOfType_Active_HFULLHEX=118
  • NumNodesOfType_Active_HLONG=6
  • NumNodesOfType_Active_HUNIHEX=619
  • NumNodesOfType_Active_INPUT=8982
  • NumNodesOfType_Active_IOBOUTPUT=50
  • NumNodesOfType_Active_OMUX=3997
  • NumNodesOfType_Active_OUTPUT=3741
  • NumNodesOfType_Active_PREBXBY=1532
  • NumNodesOfType_Active_VFULLHEX=593
  • NumNodesOfType_Active_VLONG=34
  • NumNodesOfType_Active_VUNIHEX=590
  • NumNodesOfType_Gnd_BRAMADDR=6
  • NumNodesOfType_Gnd_BRAMDUMMY=66
  • NumNodesOfType_Gnd_CNTRLPIN=70
  • NumNodesOfType_Gnd_DOUBLE=140
  • NumNodesOfType_Gnd_DUMMY=180
  • NumNodesOfType_Gnd_DUMMYBANK=6
  • NumNodesOfType_Gnd_HFULLHEX=1
  • NumNodesOfType_Gnd_INPUT=302
  • NumNodesOfType_Gnd_OMUX=128
  • NumNodesOfType_Gnd_OUTPUT=96
  • NumNodesOfType_Gnd_PREBXBY=46
  • NumNodesOfType_Gnd_VFULLHEX=9
  • NumNodesOfType_Gnd_VUNIHEX=1
  • NumNodesOfType_Vcc_BRAMDUMMY=11
  • NumNodesOfType_Vcc_CNTRLPIN=61
  • NumNodesOfType_Vcc_DUMMY=186
  • NumNodesOfType_Vcc_INPUT=221
  • NumNodesOfType_Vcc_PREBXBY=21
  • NumNodesOfType_Vcc_VCCOUT=120
 		SiteSummary
  • BUFGMUX=9
  • BUFGMUX_GCLKMUX=9
  • BUFGMUX_GCLK_BUFFER=9
  • DCM=4
  • DCM_DCM=4
  • DIFFMI=17
  • DIFFMI_DELAY_ADJ_BBOX=17
  • DIFFMI_IFF1=17
  • DIFFMI_IFF2=4
  • DIFFMI_INBUF=17
  • DIFFMI_PAD=17
  • DIFFMTB=10
  • DIFFMTB_OFF1=10
  • DIFFMTB_OFF2=10
  • DIFFMTB_OFFDDRBLACKBOX=10
  • DIFFMTB_OUTBUF=10
  • DIFFMTB_PAD=10
  • DIFFSI=17
  • DIFFSI_IFF1=1
  • DIFFSI_IFF2=3
  • DIFFSI_PAD=17
  • DIFFSI_PADOUT_USED=17
  • DIFFSTB=10
  • DIFFSTB_DIFFO_IN_USED=10
  • DIFFSTB_OFF1=9
  • DIFFSTB_OUTBUF=10
  • DIFFSTB_PAD=10
  • IBUF=3
  • IBUF_DELAY_ADJ_BBOX=3
  • IBUF_INBUF=3
  • IBUF_PAD=3
  • IOB=47
  • IOB_DELAY_ADJ_BBOX=18
  • IOB_INBUF=18
  • IOB_OFF1=46
  • IOB_OFF2=20
  • IOB_OFFDDRBLACKBOX=20
  • IOB_OUTBUF=47
  • IOB_PAD=47
  • RAMB16BWE=8
  • RAMB16BWE_RAMB16BWE=8
  • SLICEL=1677
  • SLICEL_C1VDD=24
  • SLICEL_CYMUXF=229
  • SLICEL_CYMUXG=207
  • SLICEL_F=1041
  • SLICEL_F5MUX=64
  • SLICEL_FFX=784
  • SLICEL_FFY=1041
  • SLICEL_G=1179
  • SLICEL_GNDF=169
  • SLICEL_GNDG=180
  • SLICEL_XORF=236
  • SLICEL_XORG=212
  • SLICEM=172
  • SLICEM_F=166
  • SLICEM_FFX=38
  • SLICEM_FFY=43
  • SLICEM_G=172
  • SLICEM_GMC15_BLACKBOX=1
  • SLICEM_WSGEN=156
 
Configuration Data
BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:9]
 DCM_DCM
  • CLKDV_DIVIDE=[2:4]
  • CLKOUT_PHASE_SHIFT=[VARIABLE:4]
  • CLK_FEEDBACK=[1X:4]
  • DESKEW_ADJUST=[0:4]
  • DFS_FREQUENCY_MODE=[LOW:4]
  • DLL_FREQUENCY_MODE=[LOW:4]
  • DUTY_CYCLE_CORRECTION=[TRUE:4]
  • FACTORY_JF1=[0XC0:4]
  • FACTORY_JF2=[0X80:4]
 DIFFMI_DELAY_ADJ_BBOX
  • DELAY_ADJ_ATTRBOX=[FIXED:17]
  • IBUF_DELAY_VALUE=[DLY0:17]
  • IFD_DELAY_VALUE=[DLY0:15] [DLY1:2]
 DIFFMI_IFF1
  • IFF1_INIT_ATTR=[INIT0:17]
  • IFF1_SR_ATTR=[SRLOW:4]
  • IFFATTRBOX=[SYNC:4]
  • LATCH_OR_FF=[FF:17]
 DIFFMI_IFF2
  • IFF2_INIT_ATTR=[INIT0:4]
  • IFF2_SR_ATTR=[SRLOW:4]
  • IFFATTRBOX=[SYNC:4]
  • LATCH_OR_FF=[FF:4]
 DIFFMI_PAD
  • DIFF_TERM=[TRUE:17]
  • IOATTRBOX=[LVDS_33:17]
 DIFFMTB_OFF1
  • LATCH_OR_FF=[FF:10]
  • OFF1_INIT_ATTR=[INIT0:10]
  • OFF1_SR_ATTR=[SRLOW:10]
  • OFFATTRBOX=[SYNC:10]
 DIFFMTB_OFF2
  • LATCH_OR_FF=[FF:10]
  • OFF2_INIT_ATTR=[INIT0:10]
  • OFF2_SR_ATTR=[SRLOW:10]
  • OFFATTRBOX=[SYNC:10]
 DIFFMTB_OUTBUF
  • SUSPEND=[3STATE:10]
 DIFFMTB_PAD
  • IOATTRBOX=[LVDS_33:10]
 DIFFSI_IFF1
  • IFF1_INIT_ATTR=[INIT0:1]
  • IFF1_SR_ATTR=[SRLOW:1]
  • IFFATTRBOX=[SYNC:1]
  • LATCH_OR_FF=[FF:1]
 DIFFSI_IFF2
  • IFF2_INIT_ATTR=[INIT0:3]
  • IFF2_SR_ATTR=[SRLOW:3]
  • IFFATTRBOX=[SYNC:3]
  • LATCH_OR_FF=[FF:3]
 DIFFSI_PAD
  • DIFF_TERM=[TRUE:17]
  • IOATTRBOX=[LVDS_33:17]
 DIFFSTB_OFF1
  • LATCH_OR_FF=[FF:9]
  • OFF1_INIT_ATTR=[INIT0:9]
  • OFF1_SR_ATTR=[SRLOW:9]
  • OFFATTRBOX=[SYNC:9]
 DIFFSTB_OUTBUF
  • SUSPEND=[3STATE:10]
 DIFFSTB_PAD
  • IOATTRBOX=[LVDS_33:10]
 IBUF_DELAY_ADJ_BBOX
  • DELAY_ADJ_ATTRBOX=[FIXED:3]
  • IBUF_DELAY_VALUE=[DLY0:3]
  • IFD_DELAY_VALUE=[DLY0:3]
 IBUF_PAD
  • IOATTRBOX=[LVCMOS25:3]
  • PULL=[PULLUP:3]
 IOB_DELAY_ADJ_BBOX
  • DELAY_ADJ_ATTRBOX=[FIXED:18]
  • IBUF_DELAY_VALUE=[DLY0:16] [DLY4:2]
  • IFD_DELAY_VALUE=[DLY0:18]
 IOB_OFF1
  • LATCH_OR_FF=[FF:46]
  • OFF1_INIT_ATTR=[INIT0:45] [INIT1:1]
  • OFF1_SR_ATTR=[SRLOW:20] [SRHIGH:1]
  • OFFATTRBOX=[ASYNC:1] [SYNC:20]
 IOB_OFF2
  • LATCH_OR_FF=[FF:20]
  • OFF2_INIT_ATTR=[INIT0:20]
  • OFF2_SR_ATTR=[SRLOW:20]
  • OFFATTRBOX=[SYNC:20]
 IOB_OUTBUF
  • SUSPEND=[3STATE:47]
 IOB_PAD
  • DRIVEATTRBOX=[8:5]
  • IOATTRBOX=[SSTL2_I:42] [LVCMOS33:5]
  • SLEW=[SLOW:5]
 RAMB16BWE_RAMB16BWE
  • DATA_WIDTH_A=[36:8]
  • DATA_WIDTH_B=[36:8]
  • WRITE_MODE_A=[WRITE_FIRST:8]
  • WRITE_MODE_B=[WRITE_FIRST:8]
 SLICEL_FFX
  • FFX_INIT_ATTR=[INIT0:777] [INIT1:7]
  • FFX_SR_ATTR=[SRLOW:764] [SRHIGH:20]
  • LATCH_OR_FF=[FF:784]
  • SYNC_ATTR=[ASYNC:615] [SYNC:169]
 SLICEL_FFY
  • FFY_INIT_ATTR=[INIT0:1035] [INIT1:6]
  • FFY_SR_ATTR=[SRLOW:1012] [SRHIGH:29]
  • LATCH_OR_FF=[FF:1041]
  • SYNC_ATTR=[ASYNC:871] [SYNC:170]
 SLICEM_F
  • F_ATTR=[DUAL_PORT:117] [SHIFT_REG:20]
  • LUT_OR_MEM=[LUT:20] [RAM:146]
 SLICEM_FFX
  • FFX_INIT_ATTR=[INIT0:38]
  • FFX_SR_ATTR=[SRLOW:38]
  • LATCH_OR_FF=[FF:38]
  • SYNC_ATTR=[ASYNC:38]
 SLICEM_FFY
  • FFY_INIT_ATTR=[INIT0:43]
  • FFY_SR_ATTR=[SRLOW:43]
  • LATCH_OR_FF=[FF:43]
  • SYNC_ATTR=[ASYNC:43]
 SLICEM_G
  • G_ATTR=[DUAL_PORT:117] [SHIFT_REG:29]
  • LUT_OR_MEM=[LUT:16] [RAM:156]
 SLICEM_WSGEN
  • SYNC_ATTR=[ASYNC:28]
 
Pin Data
BUFGMUX
  • I0=9
  • O=9
  • S=9
 BUFGMUX_GCLKMUX
  • I0=9
  • OUT=9
  • S=9
 BUFGMUX_GCLK_BUFFER
  • IN=9
  • OUT=9
 DCM
  • CLK0=4
  • CLK180=1
  • CLK90=1
  • CLKFB=4
  • CLKFX180=3
  • CLKIN=4
  • LOCKED=4
  • PSCLK=4
  • PSDONE=4
  • PSEN=4
  • PSINCDEC=4
  • RST=4
  • STATUS0=4
  • STATUS1=4
  • STATUS2=4
 DCM_DCM
  • CLK0=4
  • CLK180=1
  • CLK90=1
  • CLKFB=4
  • CLKFX180=3
  • CLKIN=4
  • LOCKED=4
  • PSCLK=4
  • PSDONE=4
  • PSEN=4
  • PSINCDEC=4
  • RST=4
  • STATUS0=4
  • STATUS1=4
  • STATUS2=4
 DIFFMI
  • DIFFI_IN=17
  • I=4
  • ICE=4
  • ICLK1=17
  • ICLK2=4
  • IQ1=17
  • IQ2=4
  • PAD=17
  • REV=4
  • SR=4
 DIFFMI_DELAY_ADJ_BBOX
  • IBUF_OUT=4
  • IFD_OUT=17
  • SEL_IN=17
 DIFFMI_IFF1
  • CE=4
  • CK=17
  • D=17
  • Q=17
  • REV=4
  • SR=4
 DIFFMI_IFF2
  • CE=4
  • CK=4
  • D=4
  • Q=4
  • REV=4
  • SR=4
 DIFFMI_INBUF
  • DIFFI_IN=17
  • OUT=17
  • PAD=17
 DIFFMI_PAD
  • PAD=17
 DIFFMTB
  • DIFFO_OUT=10
  • O1=10
  • O2=1
  • OCE=10
  • ODDRIN2=9
  • OTCLK1=10
  • OTCLK2=10
  • PAD=10
  • REV=10
  • SR=10
 DIFFMTB_OFF1
  • CE=10
  • CK=10
  • D=10
  • Q=10
  • REV=10
  • SR=10
 DIFFMTB_OFF2
  • CE=10
  • CK=10
  • D=10
  • Q=10
  • REV=10
  • SR=10
 DIFFMTB_OFFDDRBLACKBOX
  • OFF1=10
  • OFF2=10
  • OFFDDR=10
 DIFFMTB_OUTBUF
  • IN=10
  • OUTN=10
  • OUTP=10
 DIFFMTB_PAD
  • PAD=10
 DIFFSI
  • ICE=4
  • ICLK1=1
  • ICLK2=3
  • IDDRIN1=3
  • IDDRIN2=1
  • IQ1=1
  • IQ2=3
  • PAD=17
  • PADOUT=17
  • REV=4
  • SR=4
 DIFFSI_IFF1
  • CE=1
  • CK=1
  • D=1
  • Q=1
  • REV=1
  • SR=1
 DIFFSI_IFF2
  • CE=3
  • CK=3
  • D=3
  • Q=3
  • REV=3
  • SR=3
 DIFFSI_PAD
  • PAD=17
 DIFFSI_PADOUT_USED
  • 0=17
  • OUT=17
 DIFFSTB
  • DIFFO_IN=10
  • O1=9
  • OCE=9
  • ODDROUT1=9
  • OTCLK1=9
  • PAD=10
  • REV=9
  • SR=9
 DIFFSTB_DIFFO_IN_USED
  • 0=10
  • OUT=10
 DIFFSTB_OFF1
  • CE=9
  • CK=9
  • D=9
  • Q=9
  • REV=9
  • SR=9
 DIFFSTB_OUTBUF
  • DIFFO_IN=10
  • OUTP=10
 DIFFSTB_PAD
  • PAD=10
 IBUF
  • I=3
  • PAD=3
 IBUF_DELAY_ADJ_BBOX
  • IBUF_OUT=3
  • SEL_IN=3
 IBUF_INBUF
  • IN=3
  • OUT=3
 IBUF_PAD
  • PAD=3
 IOB
  • I=18
  • O1=47
  • O2=20
  • OCE=25
  • OTCLK1=46
  • OTCLK2=20
  • PAD=47
  • REV=20
  • SR=21
  • T1=18
 IOB_DELAY_ADJ_BBOX
  • IBUF_OUT=18
  • SEL_IN=18
 IOB_INBUF
  • IN=18
  • OUT=18
 IOB_OFF1
  • CE=25
  • CK=46
  • D=46
  • Q=46
  • REV=20
  • SR=21
 IOB_OFF2
  • CE=20
  • CK=20
  • D=20
  • Q=20
  • REV=20
  • SR=20
 IOB_OFFDDRBLACKBOX
  • OFF1=20
  • OFF2=20
  • OFFDDR=20
 IOB_OUTBUF
  • IN=47
  • OUT=47
  • TRI=18
 IOB_PAD
  • PAD=47
 RAMB16BWE
  • ADDRA10=8
  • ADDRA11=8
  • ADDRA12=8
  • ADDRA13=8
  • ADDRA5=8
  • ADDRA6=8
  • ADDRA7=8
  • ADDRA8=8
  • ADDRA9=8
  • ADDRB10=8
  • ADDRB11=8
  • ADDRB12=8
  • ADDRB13=8
  • ADDRB5=8
  • ADDRB6=8
  • ADDRB7=8
  • ADDRB8=8
  • ADDRB9=8
  • CLKA=8
  • CLKB=8
  • DIA0=5
  • DIA1=5
  • DIA10=5
  • DIA11=5
  • DIA12=5
  • DIA13=5
  • DIA14=5
  • DIA15=5
  • DIA16=5
  • DIA17=5
  • DIA18=5
  • DIA19=5
  • DIA2=5
  • DIA20=5
  • DIA21=5
  • DIA22=5
  • DIA23=5
  • DIA24=5
  • DIA25=5
  • DIA26=5
  • DIA27=5
  • DIA28=5
  • DIA29=5
  • DIA3=5
  • DIA30=5
  • DIA31=5
  • DIA4=5
  • DIA5=5
  • DIA6=5
  • DIA7=5
  • DIA8=5
  • DIA9=5
  • DIB0=3
  • DIB1=3
  • DIB10=3
  • DIB11=3
  • DIB12=3
  • DIB13=3
  • DIB14=3
  • DIB15=3
  • DIB16=3
  • DIB17=3
  • DIB18=3
  • DIB19=3
  • DIB2=3
  • DIB20=3
  • DIB21=3
  • DIB22=3
  • DIB23=3
  • DIB24=3
  • DIB25=3
  • DIB26=3
  • DIB27=3
  • DIB28=3
  • DIB29=3
  • DIB3=3
  • DIB30=3
  • DIB31=3
  • DIB4=3
  • DIB5=3
  • DIB6=3
  • DIB7=3
  • DIB8=3
  • DIB9=3
  • DIPA0=5
  • DIPA1=5
  • DIPA2=5
  • DIPA3=5
  • DIPB0=3
  • DIPB1=3
  • DIPB2=3
  • DIPB3=3
  • DOA0=4
  • DOA1=4
  • DOA10=4
  • DOA11=4
  • DOA12=4
  • DOA13=4
  • DOA14=4
  • DOA15=4
  • DOA16=4
  • DOA17=4
  • DOA18=4
  • DOA19=4
  • DOA2=4
  • DOA20=4
  • DOA21=4
  • DOA22=4
  • DOA23=4
  • DOA24=4
  • DOA25=4
  • DOA26=4
  • DOA27=4
  • DOA28=4
  • DOA29=4
  • DOA3=4
  • DOA30=4
  • DOA31=4
  • DOA4=4
  • DOA5=4
  • DOA6=4
  • DOA7=4
  • DOA8=4
  • DOA9=4
  • DOB0=5
  • DOB1=5
  • DOB10=5
  • DOB11=5
  • DOB12=5
  • DOB13=5
  • DOB14=5
  • DOB15=5
  • DOB16=5
  • DOB17=5
  • DOB18=5
  • DOB19=5
  • DOB2=5
  • DOB20=5
  • DOB21=5
  • DOB22=5
  • DOB23=5
  • DOB24=5
  • DOB25=5
  • DOB26=5
  • DOB27=5
  • DOB28=5
  • DOB29=4
  • DOB3=5
  • DOB30=4
  • DOB31=4
  • DOB4=5
  • DOB5=5
  • DOB6=5
  • DOB7=5
  • DOB8=5
  • DOB9=5
  • DOPA0=4
  • DOPA1=1
  • DOPA2=4
  • DOPA3=4
  • DOPB0=2
  • DOPB1=1
  • DOPB2=1
  • DOPB3=1
  • ENA=8
  • ENB=8
  • SSRA=8
  • SSRB=8
  • WEA0=8
  • WEA1=8
  • WEA2=8
  • WEA3=8
  • WEB0=8
  • WEB1=8
  • WEB2=8
  • WEB3=8
 RAMB16BWE_RAMB16BWE
  • ADDRA10=8
  • ADDRA11=8
  • ADDRA12=8
  • ADDRA13=8
  • ADDRA5=8
  • ADDRA6=8
  • ADDRA7=8
  • ADDRA8=8
  • ADDRA9=8
  • ADDRB10=8
  • ADDRB11=8
  • ADDRB12=8
  • ADDRB13=8
  • ADDRB5=8
  • ADDRB6=8
  • ADDRB7=8
  • ADDRB8=8
  • ADDRB9=8
  • CLKA=8
  • CLKB=8
  • DIA0=5
  • DIA1=5
  • DIA10=5
  • DIA11=5
  • DIA12=5
  • DIA13=5
  • DIA14=5
  • DIA15=5
  • DIA16=5
  • DIA17=5
  • DIA18=5
  • DIA19=5
  • DIA2=5
  • DIA20=5
  • DIA21=5
  • DIA22=5
  • DIA23=5
  • DIA24=5
  • DIA25=5
  • DIA26=5
  • DIA27=5
  • DIA28=5
  • DIA29=5
  • DIA3=5
  • DIA30=5
  • DIA31=5
  • DIA4=5
  • DIA5=5
  • DIA6=5
  • DIA7=5
  • DIA8=5
  • DIA9=5
  • DIB0=3
  • DIB1=3
  • DIB10=3
  • DIB11=3
  • DIB12=3
  • DIB13=3
  • DIB14=3
  • DIB15=3
  • DIB16=3
  • DIB17=3
  • DIB18=3
  • DIB19=3
  • DIB2=3
  • DIB20=3
  • DIB21=3
  • DIB22=3
  • DIB23=3
  • DIB24=3
  • DIB25=3
  • DIB26=3
  • DIB27=3
  • DIB28=3
  • DIB29=3
  • DIB3=3
  • DIB30=3
  • DIB31=3
  • DIB4=3
  • DIB5=3
  • DIB6=3
  • DIB7=3
  • DIB8=3
  • DIB9=3
  • DIPA0=5
  • DIPA1=5
  • DIPA2=5
  • DIPA3=5
  • DIPB0=3
  • DIPB1=3
  • DIPB2=3
  • DIPB3=3
  • DOA0=4
  • DOA1=4
  • DOA10=4
  • DOA11=4
  • DOA12=4
  • DOA13=4
  • DOA14=4
  • DOA15=4
  • DOA16=4
  • DOA17=4
  • DOA18=4
  • DOA19=4
  • DOA2=4
  • DOA20=4
  • DOA21=4
  • DOA22=4
  • DOA23=4
  • DOA24=4
  • DOA25=4
  • DOA26=4
  • DOA27=4
  • DOA28=4
  • DOA29=4
  • DOA3=4
  • DOA30=4
  • DOA31=4
  • DOA4=4
  • DOA5=4
  • DOA6=4
  • DOA7=4
  • DOA8=4
  • DOA9=4
  • DOB0=5
  • DOB1=5
  • DOB10=5
  • DOB11=5
  • DOB12=5
  • DOB13=5
  • DOB14=5
  • DOB15=5
  • DOB16=5
  • DOB17=5
  • DOB18=5
  • DOB19=5
  • DOB2=5
  • DOB20=5
  • DOB21=5
  • DOB22=5
  • DOB23=5
  • DOB24=5
  • DOB25=5
  • DOB26=5
  • DOB27=5
  • DOB28=5
  • DOB29=4
  • DOB3=5
  • DOB30=4
  • DOB31=4
  • DOB4=5
  • DOB5=5
  • DOB6=5
  • DOB7=5
  • DOB8=5
  • DOB9=5
  • DOPA0=4
  • DOPA1=1
  • DOPA2=4
  • DOPA3=4
  • DOPB0=2
  • DOPB1=1
  • DOPB2=1
  • DOPB3=1
  • ENA=8
  • ENB=8
  • SSRA=8
  • SSRB=8
  • WEA0=8
  • WEA1=8
  • WEA2=8
  • WEA3=8
  • WEB0=8
  • WEB1=8
  • WEB2=8
  • WEB3=8
 SLICEL
  • BX=298
  • BY=511
  • CE=969
  • CIN=204
  • CLK=1364
  • COUT=207
  • F1=1039
  • F2=875
  • F3=652
  • F4=439
  • G1=1175
  • G2=1023
  • G3=745
  • G4=384
  • SR=484
  • X=433
  • XB=1
  • XQ=784
  • Y=566
  • YQ=1041
 SLICEL_C1VDD
  • 1=24
 SLICEL_CYMUXF
  • 0=229
  • 1=229
  • OUT=229
  • S0=229
 SLICEL_CYMUXG
  • 0=207
  • 1=207
  • OUT=207
  • S0=207
 SLICEL_F
  • A1=1039
  • A2=875
  • A3=652
  • A4=439
  • D=1041
 SLICEL_F5MUX
  • F=64
  • G=64
  • OUT=64
  • S0=64
 SLICEL_FFX
  • CE=641
  • CK=784
  • D=784
  • Q=784
  • REV=6
  • SR=313
 SLICEL_FFY
  • CE=677
  • CK=1041
  • D=1041
  • Q=1041
  • SR=343
 SLICEL_G
  • A1=1175
  • A2=1023
  • A3=745
  • A4=384
  • D=1179
 SLICEL_GNDF
  • 0=169
 SLICEL_GNDG
  • 0=180
 SLICEL_XORF
  • 0=236
  • 1=236
  • O=236
 SLICEL_XORG
  • 0=212
  • 1=212
  • O=212
 SLICEM
  • BX=29
  • BY=156
  • CE=39
  • CLK=172
  • F1=166
  • F2=166
  • F3=164
  • F4=147
  • G1=171
  • G2=171
  • G3=171
  • G4=155
  • SR=156
  • X=129
  • XQ=38
  • Y=119
  • YQ=43
 SLICEM_CYMUXF
  • 0=1
  • 1=1
  • OUT=1
  • S0=1
 SLICEM_F
  • A1=166
  • A2=166
  • A3=164
  • A4=147
  • D=166
  • DI=146
  • WF1=126
  • WF2=126
  • WF3=126
  • WF4=126
  • WS=146
 SLICEM_FFX
  • CE=35
  • CK=38
  • D=38
  • Q=38
 SLICEM_FFY
  • CE=39
  • CK=43
  • D=43
  • Q=43
 SLICEM_G
  • A1=171
  • A2=171
  • A3=171
  • A4=155
  • D=162
  • DI=156
  • WG1=127
  • WG2=127
  • WG3=127
  • WG4=127
  • WS=156
 SLICEM_GMC15_BLACKBOX
  • MC15=1
  • WS2=1
 SLICEM_GNDF
  • 0=1
 SLICEM_WSGEN
  • CK=156
  • WE=156
  • WSF=146
  • WSG=156
 
Tool Usage
Command Line History
  • xst -ise <ise_file>
  • ngdbuild -ise <ise_file> <fname>.ngd
  • map -ise <ise_file> -intstyle ise -p xc3s200a-ft256-4 -timing -logic_opt on -ol high -xe c -t 1 -register_duplication -cm speed -detail -ignore_keep_hierarchy -pr b -k 4 -power on -o <fname>.ncd <fname>.ngd <fname>.pcf
  • ngdbuild -ise <ise_file> <fname>.ngd
  • map -ise <ise_file> -intstyle ise -p xc3s200a-ft256-4 -timing -logic_opt on -ol high -xe c -t 1 -register_duplication -cm speed -detail -ignore_keep_hierarchy -pr b -k 4 -power on -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -ise <ise_file> -w -intstyle ise -ol high -xe c -t 1 -power on <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -ise <ise_file> -intstyle ise -e 3 -s 4 -xml <design> <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • ngdbuild -ise <ise_file> <fname>.ngd
  • map -ise <ise_file> -intstyle ise -p xc3s200a-ft256-4 -timing -logic_opt on -ol high -xe c -t 1 -register_duplication -cm speed -detail -ignore_keep_hierarchy -pr b -k 4 -power on -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -ise <ise_file> -w -intstyle ise -ol high -xe c -t 1 -power on <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -ise <ise_file> -intstyle ise -e 3 -s 4 -xml <design> <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • ngdbuild -ise <ise_file> <fname>.ngd
  • map -ise <ise_file> -intstyle ise -p xc3s200a-ft256-4 -timing -logic_opt on -ol high -xe c -t 1 -register_duplication -cm speed -detail -ignore_keep_hierarchy -pr b -k 4 -power on -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -ise <ise_file> -w -intstyle ise -ol high -xe c -t 1 -power on <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -ise <ise_file> -intstyle ise -e 3 -s 4 -xml <design> <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • ngdbuild -ise <ise_file> <fname>.ngd
  • map -ise <ise_file> -intstyle ise -p xc3s200a-ft256-4 -timing -logic_opt on -ol high -xe c -t 1 -register_duplication -cm speed -detail -ignore_keep_hierarchy -pr b -k 4 -power on -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -ise <ise_file> -w -intstyle ise -ol high -xe c -t 1 -power on <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -ise <ise_file> -intstyle ise -e 3 -s 4 -xml <design> <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • xst -ise <ise_file>
  • ngdbuild -ise <ise_file> <fname>.ngd
  • ngdbuild -ise <ise_file> <fname>.ngd
  • map -ise <ise_file> -intstyle ise -p xc3s200a-ft256-4 -timing -logic_opt on -ol high -xe c -t 1 -register_duplication -cm speed -detail -ignore_keep_hierarchy -pr b -k 4 -power on -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -ise <ise_file> -w -intstyle ise -ol high -xe c -t 1 -power on <fname>.ncd <fname>.ncd <fname>.pcf
  • ngdbuild -ise <ise_file> <fname>.ngd
  • map -ise <ise_file> -intstyle ise -p xc3s200a-ft256-4 -timing -logic_opt on -ol high -xe c -t 1 -register_duplication -cm speed -detail -ignore_keep_hierarchy -pr b -k 4 -power on -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -ise <ise_file> -w -intstyle ise -ol high -xe c -t 1 -power on <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -ise <ise_file> -intstyle ise -e 3 -s 4 -xml <design> <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • xst -ise <ise_file>
  • ngdbuild -ise <ise_file> <fname>.ngd
  • map -ise <ise_file> -intstyle ise -p xc3s200a-ft256-4 -timing -logic_opt on -ol high -xe c -t 1 -register_duplication -cm speed -detail -ignore_keep_hierarchy -pr b -k 4 -power on -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -ise <ise_file> -w -intstyle ise -ol high -xe c -t 1 -power on <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -ise <ise_file> -intstyle ise -e 3 -s 4 -xml <design> <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • xst -ise <ise_file>
  • ngdbuild -ise <ise_file> <fname>.ngd
  • map -ise <ise_file> -intstyle ise -p xc3s200a-ft256-4 -timing -logic_opt on -ol high -xe c -t 1 -register_duplication -cm speed -detail -ignore_keep_hierarchy -pr b -k 4 -power on -o <fname>.ncd <fname>.ngd <fname>.pcf
  • xst -ise <ise_file>
  • ngdbuild -ise <ise_file> <fname>.ngd
  • map -ise <ise_file> -intstyle ise -p xc3s200a-ft256-4 -timing -logic_opt on -ol high -xe c -t 1 -register_duplication -cm speed -detail -ignore_keep_hierarchy -pr b -k 4 -power on -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -ise <ise_file> -w -intstyle ise -ol high -xe c -t 1 -power on <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -ise <ise_file> -intstyle ise -e 3 -s 4 -xml <design> <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -ise <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -ise <ise_file>
  • ngdbuild -ise <ise_file> <fname>.ngd
  • map -ise <ise_file> -intstyle ise -p xc3s200a-ft256-4 -timing -logic_opt on -ol high -xe c -t 1 -register_duplication -cm speed -detail -ignore_keep_hierarchy -pr b -k 4 -power on -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -ise <ise_file> -w -intstyle ise -ol high -xe c -t 1 -power on <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -ise <ise_file> -intstyle ise -e 3 -s 4 -xml <design> <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -ise <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -ise <ise_file>
  • ngdbuild -ise <ise_file> <fname>.ngd
  • map -ise <ise_file> -intstyle ise -p xc3s200a-ft256-4 -timing -logic_opt on -ol high -xe c -t 1 -register_duplication -cm speed -detail -ignore_keep_hierarchy -pr b -k 4 -power on -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -ise <ise_file> -w -intstyle ise -ol high -xe c -t 1 -power on <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -ise <ise_file> -intstyle ise -e 3 -s 4 -xml <design> <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -ise <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -ise <ise_file>
  • ngdbuild -ise <ise_file> <fname>.ngd
  • map -ise <ise_file> -intstyle ise -p xc3s200a-ft256-4 -timing -logic_opt on -ol high -xe c -t 1 -register_duplication -cm speed -detail -ignore_keep_hierarchy -pr b -k 4 -power on -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -ise <ise_file> -w -intstyle ise -ol high -xe c -t 1 -power on <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -ise <ise_file> -intstyle ise -e 3 -s 4 -xml <design> <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -ise <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -ise <ise_file>
  • ngdbuild -ise <ise_file> <fname>.ngd
  • map -ise <ise_file> -intstyle ise -p xc3s400a-ft256-4 -timing -logic_opt on -ol high -xe c -t 1 -register_duplication -cm speed -detail -ignore_keep_hierarchy -pr b -k 4 -power on -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -ise <ise_file> -w -intstyle ise -ol high -xe c -t 1 -power on <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -ise <ise_file> -intstyle ise -e 3 -s 4 -xml <design> <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • ngdbuild -ise <ise_file> <fname>.ngd
  • map -ise <ise_file> -intstyle ise -p xc3s400a-ft256-4 -timing -logic_opt on -ol high -xe c -t 1 -register_duplication -cm speed -detail -ignore_keep_hierarchy -pr b -k 4 -power on -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -ise <ise_file> -w -intstyle ise -ol high -xe c -t 1 -power on <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -ise <ise_file> -intstyle ise -e 3 -s 4 -xml <design> <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • xst -ise <ise_file>
  • ngdbuild -ise <ise_file> <fname>.ngd
  • map -ise <ise_file> -intstyle ise -p xc3s400a-ft256-4 -timing -logic_opt on -ol high -xe c -t 1 -register_duplication -cm speed -detail -ignore_keep_hierarchy -pr b -k 4 -power on -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -ise <ise_file> -w -intstyle ise -ol high -xe c -t 1 -power on <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -ise <ise_file> -intstyle ise -e 3 -s 4 -xml <design> <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -ise <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -ise <ise_file>
  • ngdbuild -ise <ise_file> <fname>.ngd
  • map -ise <ise_file> -intstyle ise -p xc3s400a-ft256-4 -timing -logic_opt on -ol high -xe c -t 1 -register_duplication -cm speed -detail -ignore_keep_hierarchy -pr b -k 4 -power on -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -ise <ise_file> -w -intstyle ise -ol high -xe c -t 1 -power on <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -ise <ise_file> -intstyle ise -e 3 -s 4 -xml <design> <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -ise <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • ngdbuild -ise <ise_file> <fname>.ngd
  • map -ise <ise_file> -intstyle ise -p xc3s400a-ft256-4 -timing -logic_opt on -ol high -xe c -t 1 -register_duplication -cm speed -detail -ignore_keep_hierarchy -pr b -k 4 -power on -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -ise <ise_file> -w -intstyle ise -ol high -xe c -t 1 -power on <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -ise <ise_file> -intstyle ise -e 3 -s 4 -xml <design> <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -ise <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • ngdbuild -ise <ise_file> <fname>.ngd
  • map -ise <ise_file> -intstyle ise -p xc3s400a-ft256-4 -timing -logic_opt on -ol high -xe c -t 1 -register_duplication -cm speed -detail -ignore_keep_hierarchy -pr b -k 4 -power on -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -ise <ise_file> -w -intstyle ise -ol high -xe c -t 1 -power on <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -ise <ise_file> -intstyle ise -e 3 -s 4 -xml <design> <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -ise <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -ise <ise_file>
  • ngdbuild -ise <ise_file> <fname>.ngd
  • map -ise <ise_file> -intstyle ise -p xc3s400a-ft256-4 -timing -logic_opt on -ol high -xe c -t 1 -register_duplication -cm speed -detail -ignore_keep_hierarchy -pr b -k 4 -power on -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -ise <ise_file> -w -intstyle ise -ol high -xe c -t 1 -power on <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -ise <ise_file> -intstyle ise -e 3 -s 4 -xml <design> <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -ise <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • par -ise <ise_file> -w -intstyle ise -ol high -xe c -t 1 -power on <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -ise <ise_file> -intstyle ise -e 3 -s 4 -xml <design> <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -ise <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -ise <ise_file>
  • ngdbuild -ise <ise_file> <fname>.ngd
  • map -ise <ise_file> -intstyle ise -p xc3s400a-ft256-4 -timing -logic_opt on -ol high -xe c -t 1 -register_duplication -cm speed -detail -ignore_keep_hierarchy -pr b -k 4 -power on -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -ise <ise_file> -w -intstyle ise -ol high -xe c -t 1 -power on <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -ise <ise_file> -intstyle ise -e 3 -s 4 -xml <design> <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -ise <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
 
>
Software Quality
Run Statistics
ProgramRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
XSLTProcess 96 96 0 0 0 0 0
_impact 8 7 0 0 0 0 0
arwz 5 5 0 0 0 0 0
bitgen 849 849 0 0 0 0 0
cpldfit 96 96 0 0 0 0 0
edif2ngd 12 12 0 0 0 0 0
hprep6 96 96 0 0 0 0 0
map 1670 1403 0 0 0 0 0
netgen 100 99 0 0 0 0 0
ngdbuild 1826 1815 0 0 0 0 0
par 1327 1301 14 0 0 0 0
reportgen 1359 1359 0 0 0 0 0
taengine 96 96 0 0 0 0 0
trce 1302 1302 0 0 0 0 0
tsim 96 96 0 0 0 0 0
xst 2614 2589 0 0 0 0 0
 
Help Statistics
Unsuccessful Search words
dcm clock wizard ( 1 )
Help files
/doc/usenglish/books/docs/dev/dev.pdf ( 1 ) /doc/usenglish/isehelp/ite_c_overview.htm ( 2 )
/doc/usenglish/isehelp/pim_db_usbsetupdlg.htm ( 1 ) /doc/usenglish/isehelp/pim_p_connectingtocables.htm ( 1 )
/doc/usenglish/isehelp/pp_db_map_properties.htm ( 1 ) /doc/usenglish/isehelp/pp_n_process_check_syntax.htm ( 1 )
/doc/usenglish/isehelp/pta_c_ttc-path-end-points-tab.htm ( 1 ) /doc/usenglish/isehelp/pta_db_analyze_against_user_specified_paths_button.htm ( 1 )
/doc/usenglish/isehelp/pta_p_using_path_tracing.htm ( 1 ) /doc/usenglish/wizards/arwz/awz_db_dcmgen.htm ( 1 )
 
Project Statistics
PROP_Synthesis_Tool=XST (VHDL/Verilog) PROP_Simulator=ISE Simulator (VHDL/Verilog)
PROP_Top_Level_Module_Type=HDL PROP_PreferredLanguage=VHDL
PROP_Enable_Message_Filtering=false PROP_Enable_Incremental_Messaging=false
PROP_UseSmartGuide=false Partitions count=1
FILE_UCF=1 FILE_VERILOG=2
FILE_VHDL=24 PROP_xilxMapTimingDrivenPacking=true
PROP_DevDevice=xc3s400a PROP_DevFamily=Spartan3A and Spartan3AN
PROP_DevSpeed=-4 PROP_FitterReportFormat=HTML
PROP_ImpactProjectFile=changed PROP_MapEffortLevel=High
PROP_MapExtraEffort=Continue on Impossible PROP_MapLogicOptimization=true
PROP_MapPowerReduction=true PROP_MapRegDuplication=true
PROP_PreferredLanguage=VHDL PROP_SynthDecoderExtract=false
PROP_SynthExtractRAM=false PROP_SynthExtractROM=false
PROP_SynthLogicalShifterExtract=false PROP_SynthOptEffort=High
PROP_SynthShiftRegExtract=false PROP_UserConstraintEditorPreference=Constraints Editor
PROP_parGenAsyDlyRpt=true PROP_parPowerReduction=true
PROP_xilxBitgStart_Clk_DriveDone=true PROP_xilxMapAllowLogicOpt=true
PROP_xilxMapCoverMode=Speed PROP_xilxMapPackRegInto=For Inputs and Outputs
PROP_xilxMapReportDetail=true PROP_xilxNgdbldIOPads=true
PROP_xilxPAReffortLevel=High PROP_xilxPARextraEffortLevel=Continue on Impossible
PROP_xilxPostTrceRpt=Error Report PROP_xilxPreTrceRpt=Error Report
PROP_xilxSynthKeepHierarchy=Yes PROP_xstEquivRegRemoval=false
PROP_xstGenerateRTLNetlist=No Project duration(days)=306