| Environment Settings | ||||
| Environment Variable | xst | ngdbuild | map | par |
| PATHEXT | .COM; .EXE; .BAT; .CMD; .VBS; .VBE; .JS; .JSE; .WSF; .WSH; .MSC |
.COM; .EXE; .BAT; .CMD; .VBS; .VBE; .JS; .JSE; .WSF; .WSH; .MSC |
.COM; .EXE; .BAT; .CMD; .VBS; .VBE; .JS; .JSE; .WSF; .WSH; .MSC |
.COM; .EXE; .BAT; .CMD; .VBS; .VBE; .JS; .JSE; .WSF; .WSH; .MSC |
| Path | C:\Xilinx\13.4\ISE_DS\ISE\\lib\nt64; C:\Xilinx\13.4\ISE_DS\ISE\\bin\nt64; C:\Xilinx\13.4\ISE_DS\PlanAhead\bin; C:\Xilinx\13.4\ISE_DS\ISE\bin\nt64; C:\Xilinx\13.4\ISE_DS\ISE\lib\nt64; C:\Xilinx\13.4\ISE_DS\EDK\bin\nt64; C:\Xilinx\13.4\ISE_DS\EDK\lib\nt64; C:\Xilinx\13.4\ISE_DS\EDK\gnu\microblaze\nt64\bin; C:\Xilinx\13.4\ISE_DS\EDK\gnu\powerpc-eabi\nt64\bin; C:\Xilinx\13.4\ISE_DS\EDK\gnuwin\bin; C:\Xilinx\13.4\ISE_DS\common\bin\nt64; C:\Xilinx\13.4\ISE_DS\common\lib\nt64; c:\xilinx\13.1\ise_ds\ise\bin\nt; C:\Program Files\Common Files\Microsoft Shared\Windows Live; C:\Program Files (x86)\Common Files\Microsoft Shared\Windows Live; C:\Windows\system32; C:\Windows; C:\Windows\System32\Wbem; C:\Windows\System32\WindowsPowerShell\v1.0\; C:\Program Files (x86)\Windows Live\Shared; C:\Program Files (x86)\Altium Designer Summer 09\System |
C:\Xilinx\13.4\ISE_DS\ISE\\lib\nt64; C:\Xilinx\13.4\ISE_DS\ISE\\bin\nt64; C:\Xilinx\13.4\ISE_DS\PlanAhead\bin; C:\Xilinx\13.4\ISE_DS\ISE\bin\nt64; C:\Xilinx\13.4\ISE_DS\ISE\lib\nt64; C:\Xilinx\13.4\ISE_DS\EDK\bin\nt64; C:\Xilinx\13.4\ISE_DS\EDK\lib\nt64; C:\Xilinx\13.4\ISE_DS\EDK\gnu\microblaze\nt64\bin; C:\Xilinx\13.4\ISE_DS\EDK\gnu\powerpc-eabi\nt64\bin; C:\Xilinx\13.4\ISE_DS\EDK\gnuwin\bin; C:\Xilinx\13.4\ISE_DS\common\bin\nt64; C:\Xilinx\13.4\ISE_DS\common\lib\nt64; c:\xilinx\13.1\ise_ds\ise\bin\nt; C:\Program Files\Common Files\Microsoft Shared\Windows Live; C:\Program Files (x86)\Common Files\Microsoft Shared\Windows Live; C:\Windows\system32; C:\Windows; C:\Windows\System32\Wbem; C:\Windows\System32\WindowsPowerShell\v1.0\; C:\Program Files (x86)\Windows Live\Shared; C:\Program Files (x86)\Altium Designer Summer 09\System |
C:\Xilinx\13.4\ISE_DS\ISE\\lib\nt64; C:\Xilinx\13.4\ISE_DS\ISE\\bin\nt64; C:\Xilinx\13.4\ISE_DS\PlanAhead\bin; C:\Xilinx\13.4\ISE_DS\ISE\bin\nt64; C:\Xilinx\13.4\ISE_DS\ISE\lib\nt64; C:\Xilinx\13.4\ISE_DS\EDK\bin\nt64; C:\Xilinx\13.4\ISE_DS\EDK\lib\nt64; C:\Xilinx\13.4\ISE_DS\EDK\gnu\microblaze\nt64\bin; C:\Xilinx\13.4\ISE_DS\EDK\gnu\powerpc-eabi\nt64\bin; C:\Xilinx\13.4\ISE_DS\EDK\gnuwin\bin; C:\Xilinx\13.4\ISE_DS\common\bin\nt64; C:\Xilinx\13.4\ISE_DS\common\lib\nt64; c:\xilinx\13.1\ise_ds\ise\bin\nt; C:\Program Files\Common Files\Microsoft Shared\Windows Live; C:\Program Files (x86)\Common Files\Microsoft Shared\Windows Live; C:\Windows\system32; C:\Windows; C:\Windows\System32\Wbem; C:\Windows\System32\WindowsPowerShell\v1.0\; C:\Program Files (x86)\Windows Live\Shared; C:\Program Files (x86)\Altium Designer Summer 09\System |
C:\Xilinx\13.4\ISE_DS\ISE\\lib\nt64; C:\Xilinx\13.4\ISE_DS\ISE\\bin\nt64; C:\Xilinx\13.4\ISE_DS\PlanAhead\bin; C:\Xilinx\13.4\ISE_DS\ISE\bin\nt64; C:\Xilinx\13.4\ISE_DS\ISE\lib\nt64; C:\Xilinx\13.4\ISE_DS\EDK\bin\nt64; C:\Xilinx\13.4\ISE_DS\EDK\lib\nt64; C:\Xilinx\13.4\ISE_DS\EDK\gnu\microblaze\nt64\bin; C:\Xilinx\13.4\ISE_DS\EDK\gnu\powerpc-eabi\nt64\bin; C:\Xilinx\13.4\ISE_DS\EDK\gnuwin\bin; C:\Xilinx\13.4\ISE_DS\common\bin\nt64; C:\Xilinx\13.4\ISE_DS\common\lib\nt64; c:\xilinx\13.1\ise_ds\ise\bin\nt; C:\Program Files\Common Files\Microsoft Shared\Windows Live; C:\Program Files (x86)\Common Files\Microsoft Shared\Windows Live; C:\Windows\system32; C:\Windows; C:\Windows\System32\Wbem; C:\Windows\System32\WindowsPowerShell\v1.0\; C:\Program Files (x86)\Windows Live\Shared; C:\Program Files (x86)\Altium Designer Summer 09\System |
| XILINX | C:\Xilinx\13.4\ISE_DS\ISE\ | C:\Xilinx\13.4\ISE_DS\ISE\ | C:\Xilinx\13.4\ISE_DS\ISE\ | C:\Xilinx\13.4\ISE_DS\ISE\ |
| XILINX_DSP | C:\Xilinx\13.4\ISE_DS\ISE | C:\Xilinx\13.4\ISE_DS\ISE | C:\Xilinx\13.4\ISE_DS\ISE | C:\Xilinx\13.4\ISE_DS\ISE |
| XILINX_EDK | C:\Xilinx\13.4\ISE_DS\EDK | C:\Xilinx\13.4\ISE_DS\EDK | C:\Xilinx\13.4\ISE_DS\EDK | C:\Xilinx\13.4\ISE_DS\EDK |
| XILINX_PLANAHEAD | C:\Xilinx\13.4\ISE_DS\PlanAhead | C:\Xilinx\13.4\ISE_DS\PlanAhead | C:\Xilinx\13.4\ISE_DS\PlanAhead | C:\Xilinx\13.4\ISE_DS\PlanAhead |
| Synthesis Property Settings | |||
| Switch Name | Property Name | Value | Default Value |
| -ifn | LRB.prj | ||
| -ifmt | mixed | MIXED | |
| -ofn | LRB | ||
| -ofmt | NGC | NGC | |
| -p | xc3s200a-4-ft256 | ||
| -top | LRB | ||
| -opt_mode | Optimization Goal | Speed | SPEED |
| -opt_level | Optimization Effort | 1 | 1 |
| -iuc | Use synthesis Constraints File | NO | NO |
| -keep_hierarchy | Keep Hierarchy | Yes | NO |
| -netlist_hierarchy | Netlist Hierarchy | As_Optimized | as_optimized |
| -rtlview | Generate RTL Schematic | No | NO |
| -glob_opt | Global Optimization Goal | AllClockNets | ALLCLOCKNETS |
| -read_cores | Read Cores | YES | YES |
| -write_timing_constraints | Write Timing Constraints | NO | NO |
| -cross_clock_analysis | Cross Clock Analysis | NO | NO |
| -bus_delimiter | Bus Delimiter | <> | <> |
| -slice_utilization_ratio | Slice Utilization Ratio | 100 | 100% |
| -bram_utilization_ratio | BRAM Utilization Ratio | 100 | 100% |
| -verilog2001 | Verilog 2001 | YES | YES |
| -fsm_extract | YES | YES | |
| -fsm_encoding | Auto | AUTO | |
| -safe_implementation | No | NO | |
| -fsm_style | LUT | LUT | |
| -ram_extract | Yes | YES | |
| -ram_style | Auto | AUTO | |
| -rom_extract | Yes | YES | |
| -shreg_extract | YES | YES | |
| -rom_style | Auto | AUTO | |
| -auto_bram_packing | NO | NO | |
| -resource_sharing | YES | YES | |
| -async_to_sync | NO | NO | |
| -mult_style | Auto | AUTO | |
| -iobuf | YES | YES | |
| -max_fanout | 500 | 500 | |
| -bufg | 24 | 24 | |
| -register_duplication | YES | YES | |
| -register_balancing | No | NO | |
| -optimize_primitives | NO | NO | |
| -use_clock_enable | Yes | YES | |
| -use_sync_set | Yes | YES | |
| -use_sync_reset | Yes | YES | |
| -iob | True | AUTO | |
| -equivalent_register_removal | NO | YES | |
| -slice_utilization_ratio_maxmargin | 5 | 0% | |
| Translation Property Settings | |||
| Switch Name | Property Name | Value | Default Value |
| -a | Create I/O Pads from Ports | true | false |
| -intstyle | ise | None | |
| -dd | _ngo | None | |
| -p | xc3s200a-ft256-4 | None | |
| -uc | LRB.ucf | None | |
| Map Property Settings | |||
| Switch Name | Property Name | Value | Default Value |
| -ol | Place & Route Effort Level (Overall) | high | high |
| -ir | Use RLOC Constraints | OFF | OFF |
| -ignore_keep_hierarchy | Allow Logic Optimization Across Hierarchy | TRUE | FALSE |
| -logic_opt | Combinatorial Logic Optimization | TRUE | FALSE |
| -t | Starting Placer Cost Table (1-100) Map | 1 | 0 |
| -register_duplication | Register Duplication Map | TRUE | FALSE |
| -cm | Optimization Strategy (Cover Mode) | speed | area |
| -intstyle | ise | None | |
| -o | LRB_map.ncd | None | |
| -pr | Pack I/O Registers/Latches into IOBs | b | off |
| -p | xc3s200a-ft256-4 | None | |
| Place and Route Property Settings | |||
| Switch Name | Property Name | Value | Default Value |
| -t | 1 | 1 | |
| -intstyle | ise | ||
| -ol | Place & Route Effort Level (Overall) | high | std |
| -w | true | false | |
| Operating System Information | ||||
| Operating System Information | xst | ngdbuild | map | par |
| CPU Architecture/Speed | Intel(R) Xeon(R) CPU W3680 @ 3.33GHz/3340 MHz | Intel(R) Xeon(R) CPU W3680 @ 3.33GHz/3340 MHz | Intel(R) Xeon(R) CPU W3680 @ 3.33GHz/3340 MHz | Intel(R) Xeon(R) CPU W3680 @ 3.33GHz/3340 MHz |
| Host | wusx-PC | wusx-PC | wusx-PC | wusx-PC |
| OS Name | Microsoft Windows 7 , 64-bit | Microsoft Windows 7 , 64-bit | Microsoft Windows 7 , 64-bit | Microsoft Windows 7 , 64-bit |
| OS Release | Service Pack 1 (build 7601) | Service Pack 1 (build 7601) | Service Pack 1 (build 7601) | Service Pack 1 (build 7601) |