Programmer's manual for DCC2 author: S.X.Wu firmware revision: "dsp_chip3026" -- release notes 9/30/2011 designs migrated to ISE13.2, BcntErr now counts if BcntRes is missing firmware revision: "dsp_chip3025","lrb400_chip10f","vme400_chip105" -- release notes 10/14/2010 designs migrated to ISE12.3, no changes in designs themselvs firmware revision: x"3024" -- release notes 2/1/2010 Fixed BUSY counter problem. Now it counts only when in run mode firmware revision: x"3023" -- release notes 2/1/2010 Upon request, now TTS outputs BUSY state when not in run mode. The TTS output was set to DISCONNECTED before this version firmware revision: x"3022" -- release notes 11/18/2009 SLINK LFFn status added to bit 10 of register 0 for debugging purposes firmware revision: x"LRB10e" -- release notes 11/18/2009 Trying to fix a bug in reading counter high word. This version works with dsp_chip3021(low clock speed version) firmware revision: x"3021" -- release notes 11/9/2009 timing problem due to UCF problem with v301f. firmware revision: x"301f" -- release notes 10/23/2009 Bug in TTC BCNT error handling fixed firmware revision: x"301e" -- release notes 10/23/2009 A bug in HTR status counter is fixed. The bug causes counting errors and could stop the DCC event building The bug in L1A fifo readout for version 301b and earlier is also fixed. This version works only with LRB10b firmware revision: x"301d" -- release notes 8/3/2009 A bug in L1A fifo readout fixed. This version works only with LRB10d firmware revision: x"LRB10d" -- release notes 7/19/2009 LRB counter problem in LRB10c fixed firmware revision: x"LRB10c" -- release notes 7/12/2009 LRB version work with dsp_chip301c firmware revision: x"301c" -- release notes 7/12/2009 This is the first firmware version working with 150MHz LRB memory clock and 200MHz clock event buffer memory and 600Mbyte/s event building speed firmware revision: x"LRB10b" -- release notes 7/11/2009 A bug which could cause data corruption is fixed firmware revision: x"301b" -- release notes 7/3/2009 fixed problem with HTR counters firmware revision: x"LRB10a" -- release notes 6/28/2009 A bug in LRB counter read out fixed firmware revision: x"3018" -- release notes 6/18/2009 HTR counter problem fixed, new counters and ethernet controller put back firmware revision: x"3017" -- release notes 6/16/2009 version 3016 does not work as well. So new HTR counters are removed. Now the evn mismathc seems have been fixed. Will try to add new counters back in next release firmware revision: x"3016" -- release notes 6/15/2009 3015 does not work likely due to Xilinx compiler problem. Ethernet controller removed. Otherwise the same as 3015 firmware revision: x"3015" -- release notes 6/13/2009 Fixed a bug in HTR summary word which reports false event number mismatch added 5 monitoring counters for each HTR channel Ethernet controller added firmware revision: x"3013" -- release notes 5/8/2009 fixed a bug in spare connector testing added HTR_bz and HTR_OW mask to prevent from deadlocking the DAQ firmware revision: x"3012" -- release notes 5/6/2009 trigger rate rule bug fixed. Should allow 100KHz trigger rate. firmware revision: x"3011" -- release notes 5/2/2009 fixed a bug in TTCrx I2C interface ethernet access registers 0x15000-0x1500c added backplane spare connector test register 0x2718 added firmware revision: x"3010" -- release notes 4/29/2009 This should fix the slink event CRC problem definition for bit 23 of register 0x8 changed to capture event with slink CRC errors. firmware revision: x"300f" -- release notes 4/28/2009 added two more counters to monitor slink CRC error problem firmware revision: x"300e" -- release notes 4/27/2009 slink output data CRC check added CRC errors are counted by register 0x16c bit 3 of register 4 used to pause event building firmware revision: x"300d" -- release notes 4/21/2009 mismatch control register read/write bug fixed firmware revision: x"300c" -- release notes 4/15/2009 HTR status controlled TTS bug fixed firmware revision: x"3007" -- release notes 4/9/2009 disables LRB memory access from VME under run mode as a precaution lrb_chip104 should fix the bug which causes data corruption firmware revision: x"3006" -- release notes 4/9/2009 Logic modified to make it more error tolerant. And more debugging counters added. Notice that it only works with lrb_chip103 or later!!!! firmware revision: x"3005" -- release notes 4/8/2009 Logic modified to make it more error tolerant. Should be able to keep the run going even with some errors as encountered in Bat.28 firmware revision: x"3004" -- release notes 4/8/2009 A bug in HTR status word counters fixed firmware revision: x"3003" -- release notes 4/8/2009 trying to fix event builder problem and debug counters added firmware revision: x"3002" -- release notes 4/7/2009 VME block read fixed. high trigger rate with HTR empty event problem fixed firmware revision: x"3000" -- release notes 3/21/2009 first release, not all features tested DCC2 is access via both VME A24 and A32 cpld firmware revision: x"02" -- release notes 5/22/2009 This version is for boards populated with XC3S400A cpld firmware revision: x"01" -- release notes 5/22/2009 This version is for boards populated with XC3S200A vme chip firmware revision: x"0104" -- release notes 5/22/2009 This version is for boards populated with XC3S400A vme chip firmware revision: x"0101" -- release notes 4/30/2009 reigster 0x28 added to read back DIP switch position A24 space is used for FLASH access and reconfiguration purposes Its memory map is as following: OFFSET NAME ACCESS offset 0x0 ID register Read only bit31-16 vme chip firmware version bit15-0 device ID, always returns 0xdcc2 offset 0x4 vme chip mcs file CRC value Read Only bit31-24 always returns 0 bit23-0 CRC calculated during vme chip configuration offset 0x8 DCC chip mcs file CRC value Read Only bit31-24 always returns 0 bit23-0 CRC calculated during DCC chip configuration offset 0xc LRB chip mcs file CRC value Read Only bit31-24 always returns 0 bit23-0 CRC calculated during LRB chip configuration All LRBs are configured at the same time using a single mcs file offset 0x10 VME chip CSR register R/W bit31-3 not used for write bit2 set to '1' starts vme to dsp link and dsp chip SDRAM test bit 1-0 write 3 reconfigures all FPGAs from backup vme firmware write 2 reconfigures all FPGAs from default vme firmware write 1 reconfigures all FPGAs except VME chip (to start reconfiguration, first write register 0x294 to enable it) bit31-16 DCC2 board Serial Number(starting from 0x2001) bit15 DCC and LRB chips reconfiguration in progress bit14-3 always returns 0 bit2 vme to dsp link and dsp chip SDRAM test going bit1 reconfiguration enabled bit0 FLASH memory program/erase in progress offset 0x14 CPLD status register Read Only bit31-25 always returns 0 bit 24 '1' indicates bit23-0 data valid bit23-16 CPLD firmware version bit 15 '1' if configured using backup file bit 14 '1' if configured using default file bit 13 '1' if LRB5 configured successfully bit 12 '1' if LRB4 configured successfully bit 11 '1' if LRB3 configured successfully bit 10 '1' if LRB2 configured successfully bit 9 '1' if LRB1 configured successfully bit 8 '1' if DSP chip configured successfully bit 7-1 always returns 0 bit 0 should be '1' offset 0x18 link & SDRAM test error counter Read Only bit31-0 if non-zero, error detected offset 0x1c link & SDRAM test error location Read Only bit31-0 number of words received before error detected should count contineously if no errors offset 0x20 link & SDRAM test expected data Read Only bit31-0 expected data when error detected. Value should be changing if no error offset 0x24 link & SDRAM test actual data Read Only bit31-0 actual data when error detected. Value should be changing if no error offset 0x28 DIP switch readback register Read Only bit31-24 always reads 0 bit7-0 DIP switch setting offset 0x100 FLASH control register R/W bit31-9 not used bit8-0 starts sending n-1 bytes of data in FLASH write buffer to FLASH offset 0x294 reconfiguration enable register Write only write 0x4dcc2009 to this register enables reconfiguration once Any VME write operation will disable it again. This means that the first VME write after this must be a write to register 0x10 offset 0x800 FLASH write buffer R/W used to store FLASH command and up to 256 bytes of FLASH data to be written to the FLASH offset 0xa00 FLASH read buffer Read only used to store up to 256 bytes of FLASH data read from the FLASH A32 space is very similar to the log3_fmem space with some more extentions which cover the old LRB operations OFFSET NAME ACCESS offset 0x0 command and status register R/W read: bit 31 HTR does not stop after tcc reset bit 30-16 if '1', corresponding buffer for HTR channel 14 thru 0 overflow bit 15 DCC not ready bit 14 DCC BUSY bit 13 L1A OVERFLOW WARNING bit 12-11 returns 0 bit 10 slink LFFn inverted bit 9 TTCrx sync lost bit 8 TTCrx had double error bit 7 TTCrx had single error bit 6 TTCrx bcnt error bit 5 TTCrx not ready bit 4 returns 0 bit 3 monitor buffer empty bit 2 monitor buffer full bit 1 slink full bit 0 slink down write: bit 31-4 not used bit 3 reset errors bit 2 reset TTCrx only bit 1 reset slink only bit 0 reset all registers with offset from 0x30 up. offset 0x4 configuration register R/W read: bit 31-16 DCC chip firmware revision bit 15 if '1', trigger rule violation outputs TTS BUSY bit 14 if '1', monitor buffer full will stop event builder bit 13 if '1', send all data to downstream when ttc reset is received. if '0', flush all data when ttc reset is received. bit 12 if '1', TTS outputs correspond to bits 11-8 instead of TTS state when run bit(bit 0) is '1', this bit will be forced to '0' bit 11-8 used for TTS driver test bit 7 when run mode bit is '0', this bit is SLINK control/data bit. For SLINK test purpose bit 6 if set, ethernet write access enabled bit 5 '1' enables TTCrx broadcast commands bit 4 not used bit 3 if '1', pauses event building. For debugging only bit 2 slink test mode bit 1 slink enable bit 0 run mode write: bit 31-16 write '1' to bit n resets bit n-16 bit 15-0 write '1' to bit m sets bit m offset 0x8 monitoring event control R/W read: bit 31-24 read only. records the occurence of enabled error conditions happened to recorded events bit 23-16 read back what was written to. bit 15-0 scale factor, when bits 23-16 are not all zero, these bits are bit 15 set to '1' when when at least 128 events are in the buffer bit 14-8 monitor buffer write pointer bit 7-0 number of events captured after trigger event. Normally it should be 0x40, but could be less if event building stops due to other problems. write: if bits 23-16 are not all zeros, the monitor buffer keeps overwriting old events after 128 events are filled until the enabled error consition happens and it records 64 more events and stops. To re-enabling it, this register must be written again. If bits 23-16 are all zeros, buffering stops after becoming full. bit 23 If set to '1', catches events when slink CRC error detected bit 22 If set to '1', catches events when CRC error happened bit 21 If set to '1', catches events when oc/bcn mismatch happened bit 20 If set to '1', catches events when evn mismatch happened bit 19 If set to '1', catches events when HTR_CK set bit 18 If set to '1', catches events when HTR_EE set bit 17 If set to '1', catches events when HTR_BZ set bit 16 If set to '1', catches events when HTR_OW set bit 15-0 scale factor( = contents + 1) offset 0xc HTR channel enable register R/w read: bit 31-18 always '0' bit 17 '1' enables HTR14 bit 16 '1' enables HTR13 bit 15 '1' enables HTR12 bit 14 '1' enables HTR11 bit 13 '1' enables HTR10 bit 12 '1' enables HTR9 bit 11 '1' enables HTR8 bit 10 '1' enables HTR7 bit 9 '1' enables HTR6 bit 8 '1' enables HTR5 bit 7 '1' enables HTR4 bit 6 '1' enables HTR3 bit 5 '1' enables HTR2 bit 4 '1' enables HTR1 bit 3 '1' enables HTR0 bit 2-0 always '0' read: bit 31-18 not used bit 17-3 a '1' indicates the corresponding HTR channel enabled bit 2-0 not used offset 0x10 TTCrx ID register R/W read: bit 31-20 always '0' bit 19-16 Orbit number initial value at broadcast OCreset command bit 15-14 always '0' bit 13-0 TTCrx ID write: write access is allowed only when run mode bit(bit 0 of register 0x4) is '0' bit 31-20 not used bit 19-16 Orbit number initial value at broadcast OCreset command bit 15-14 always '0' bit 13-0 TTCrx ID offset 0x14 TTCrx I2C access register R/W read: bit 31-24 last TTCrx command received bit 23-16 always '0' bit 15 I2C busy bit 14 I2C access failed bit 13 last I2C access was a write operation bit 7-0 read data from last I2C read access if bit 15-13 = "000" write: bit 31-16 not used bit 15 '0' => write to I2C register file, '1' => read from I2C register file bit 14-13 not used bit 12-8 register address bit 7-0 write data, ignored if bit 15 = '1'(read access) Please note that the I2C access is extremely slow. Before writing to this register, first make sure that I2C is not busy offset 0x18 synchronization control register R/W read: bit 31-22 always '0' bit 21-0 as written write: write access is allowed only when run mode bit(bit 0 of register 0x4) is '0' bit 31-22 not used bit 21 If '1', disables level1 accept input. For debugging only bit 20 if '1', does not wait for next HTR data bit 19 if '1', does not skip HTR data bit 18 if '1', does not insert HTR data unless timeout occurs. bit 17 timeout enable. if '0', event build waits for level1 accept for ever. bit 16 timeout enable. if '0', event build waits for HTR data for ever. bit 15-8 timeout value in unit of 1/16 of microseconds. This is used for event number timeout bit 7-0 timeout value in unit of microseconds. This value should be greater than 128 for normal operation. This is for HTR data timeout offset 0x1C source ID register R/W read: bit 31-24 always '0' bit 23-0 source ID write: write access is allowed only when run mode bit(bit 0 of register 0x4) is '0' bit 31-24 not used bit 23-20 evt_ty bit 19-12 evt_stat bit 11-0 source ID offset 0x20 BCNT offset register R/W read: bit 31-13 always '0' bit 12 if '1', ttc_bcntres only works once after system reset bit 11-0 BCNT offset write: write access is allowed only when run mode bit(bit 0 of register 0x4) is '0' bit 31-20 not used bit 12 ttc_bcntres control bit bit 11-0 BCNT offset offset 0x24 calibration window register R/W read: bit 31 if '1', calibration events enabled bit 30-28 always '0' bit 27-16 calibration window upper limit(included) bit 15-12 current Laser position bit 11-0 calibration window lower limit(not included) write: bit 31 default to '1', enabling calibration events bit 30-28 always '0' bit 27-22 fixed as "110110" bit 21-16 settable part of calibration window upper limit,3519 maximum(included), default to "100110" bit 15-12 read only bit 11-6 fixed as "110110" bit 5-0 settable part of calibration window upper limit,3456 minimum(not included), default to "011101" offset 0x28 memory status register Read only For debugging purposes only offset 0x2c test control register R/W bit 5 '1' enables LED tests bit 4 '1' enables LRB link and memory tests bit 3-0 sets LRB test length offset 0x30 SDRAM page register R/W read: bit 31-7 always '0' bit 6-0 SDRAM page number write: write access is allowed only when run mode bit(bit 0 of register 0x4) is '0' If run bit is '1', write to 0x80 increments page number by one. bit 31-7 not used bit 6-0 SDRAM page number, each page is 64kbytes size offset 0x34 monitoring event word count Read only read: bit 31-13 always '0' bit 12-0 monitored event size in 32-bit word. In run mode, it returns '0' if there is no data avaiable offset 0x38 event number fifo pointers Read Only read: bit 31-30 always '0' bit 29-16 TTCrx fifo write pointer bit 15-14 always '0' bit 13-0 TTCrx fifo read pointer offset 0x3c Slink fifo pointers Read Only read: bit 31-25 always '0' bit 24-16 Slink fifo write pointer bit 15-9 always '0' bit 8-0 Slink fifo read pointer offset 0x100 control reg for HTR staus bit0 R/W bit 3-0 state to go bit 7-4 state transition threshold set this nibble to 0xf effectively disables it. offset 0x104 control reg for HTR staus bit1 R/W offset 0x108 control reg for HTR staus bit2 R/W offset 0x10c control reg for HTR staus bit3 R/W offset 0x110 control reg for HTR staus bit4 R/W offset 0x114 control reg for HTR staus bit5 R/W offset 0x118 control reg for HTR staus bit6 R/W offset 0x11c control reg for HTR staus bit7 R/W offset 0x120 control reg for HTR staus bit8 R/W offset 0x124 control reg for HTR staus bit9 R/W offset 0x128 control reg for HTR staus bit10 R/W offset 0x12c control reg for HTR staus bit11 R/W offset 0x130 control reg for HTR staus bit12 R/W offset 0x134 control reg for HTR staus bit13 R/W offset 0x138 controll reg for HTR staus bit14 R/W offset 0x140 event builder block counter Read Only offset 0x144 slink block counter Read Only offset 0x148 monitored event counter Read Only offset 0x14c L1accept counter Read Only offset 0x150 Calib Trigger counter Read Only offset 0x154 CT EvN mismatch counter Read Only offset 0x158 CT BcN mismatch counter Read Only offset 0x15c L1 EvN mismatch counter Read Only offset 0x160 L1 BcN mismatch counter Read Only offset 0x164 bcnt error counter Read Only offset 0x168 trigger rule violation counter Read Only offset 0x16c slink crc error counter Read Only offset 0x170 HTR crc error found in dsp chip Read Only offset 0x180 control reg for CT EvN mismatch R/W bit 3-0 state to go bit 7-4 state transition threshold offset 0x184 control reg for CT BCN mismatch R/W offset 0x188 control reg for L1 EvN mismatch R/W offset 0x18c control reg for L1 BCN mismatch R/W offset 0x190 control reg for bcnt error R/W offset 0x200 HTR0 mismatch counter low Read Only offset 0x204 HTR0 mismatch counter high Read Only offset 0x208 HTR1 mismatch counter low Read Only offset 0x20c HTR1 mismatch counter high Read Only offset 0x210 HTR2 mismatch counter low Read Only offset 0x214 HTR2 mismatch counter high Read Only offset 0x218 HTR3 mismatch counter low Read Only offset 0x20c HTR3 mismatch counter high Read Only offset 0x220 HTR4 mismatch counter low Read Only offset 0x224 HTR4 mismatch counter high Read Only offset 0x228 HTR5 mismatch counter low Read Only offset 0x22c HTR5 mismatch counter high Read Only offset 0x230 HTR6 mismatch counter low Read Only offset 0x234 HTR6 mismatch counter high Read Only offset 0x238 HTR7 mismatch counter low Read Only offset 0x23c HTR7 mismatch counter high Read Only offset 0x240 HTR8 mismatch counter low Read Only offset 0x244 HTR8 mismatch counter high Read Only offset 0x248 HTR9 mismatch counter low Read Only offset 0x24c HTR9 mismatch counter high Read Only offset 0x250 HTR10 mismatch counter low Read Only offset 0x254 HTR10 mismatch counter high Read Only offset 0x258 HTR11 mismatch counter low Read Only offset 0x25c HTR11 mismatch counter high Read Only offset 0x260 HTR12 mismatch counter low Read Only offset 0x264 HTR12 mismatch counter high Read Only offset 0x268 HTR13 mismatch counter low Read Only offset 0x26c HTR13 mismatch counter high Read Only offset 0x270 HTR14 mismatch counter low Read Only offset 0x274 HTR14 mismatch counter high Read Only offset 0x3a0 event builder word counter low Read Only offset 0x3a4 event builder word counter high Read Only offset 0x3a8 slink word counter low Read Only offset 0x3ac slink word counter high Read Only offset 0x3b0 TTCrx Single err counter low Read Only offset 0x3b4 TTCrx Single err counter high Read Only offset 0x3b8 TTCrx double err counter low Read Only offset 0x3bc TTCrx double err counter high Read Only offset 0x3c0 READY on time counter low Read Only offset 0x3c4 READY on time counter high Read Only offset 0x3c8 BUSY on time counter low Read Only offset 0x3cc BUSY on time counter high Read Only offset 0x3d0 OVFL on time counter low Read Only offset 0x3d4 OVFL on time counter high Read Only offset 0x3d8 SYNC lost on time counter low Read Only offset 0x3dc SYNC lost on time counter high Read Only offset 0x3e0 RUN on time counter low Read Only offset 0x3e4 RUN on time counter high Read Only offset 0x600 HTR0 evn mismatch counter Read Only offset 0x604 HTR1 evn mismatch counter Read Only offset 0x608 HTR2 evn mismatch counter Read Only offset 0x60C HTR3 evn mismatch counter Read Only offset 0x610 HTR4 evn mismatch counter Read Only offset 0x614 HTR5 evn mismatch counter Read Only offset 0x618 HTR6 evn mismatch counter Read Only offset 0x61C HTR7 evn mismatch counter Read Only offset 0x620 HTR8 evn mismatch counter Read Only offset 0x624 HTR9 evn mismatch counter Read Only offset 0x628 HTR10 evn mismatch counter Read Only offset 0x62C HTR11 evn mismatch counter Read Only offset 0x630 HTR12 evn mismatch counter Read Only offset 0x634 HTR13 evn mismatch counter Read Only offset 0x638 HTR14 evn mismatch counter Read Only offset 0x640 HTR0 bcn mismatch counter Read Only offset 0x644 HTR1 bcn mismatch counter Read Only offset 0x648 HTR2 bcn mismatch counter Read Only offset 0x64C HTR3 bcn mismatch counter Read Only offset 0x650 HTR4 bcn mismatch counter Read Only offset 0x654 HTR5 bcn mismatch counter Read Only offset 0x658 HTR6 bcn mismatch counter Read Only offset 0x65C HTR7 bcn mismatch counter Read Only offset 0x660 HTR8 bcn mismatch counter Read Only offset 0x664 HTR9 bcn mismatch counter Read Only offset 0x668 HTR10 bcn mismatch counter Read Only offset 0x66C HTR11 bcn mismatch counter Read Only offset 0x670 HTR12 bcn mismatch counter Read Only offset 0x674 HTR13 bcn mismatch counter Read Only offset 0x678 HTR14 bcn mismatch counter Read Only offset 0x680 HTR0 orn mismatch counter Read Only offset 0x684 HTR1 orn mismatch counter Read Only offset 0x688 HTR2 orn mismatch counter Read Only offset 0x68C HTR3 orn mismatch counter Read Only offset 0x690 HTR4 orn mismatch counter Read Only offset 0x694 HTR5 orn mismatch counter Read Only offset 0x698 HTR6 orn mismatch counter Read Only offset 0x69C HTR7 orn mismatch counter Read Only offset 0x6A0 HTR8 orn mismatch counter Read Only offset 0x6A4 HTR9 orn mismatch counter Read Only offset 0x6A8 HTR10 orn mismatch counter Read Only offset 0x6AC HTR11 orn mismatch counter Read Only offset 0x6B0 HTR12 orn mismatch counter Read Only offset 0x6B4 HTR13 orn mismatch counter Read Only offset 0x6B8 HTR14 orn mismatch counter Read Only offset 0x6C0 HTR0 skipped event counter Read Only offset 0x6C4 HTR1 skipped event counter Read Only offset 0x6C8 HTR2 skipped event counter Read Only offset 0x6CC HTR3 skipped event counter Read Only offset 0x6D0 HTR4 skipped event counter Read Only offset 0x6D4 HTR5 skipped event counter Read Only offset 0x6D8 HTR6 skipped event counter Read Only offset 0x6DC HTR7 skipped event counter Read Only offset 0x6E0 HTR8 skipped event counter Read Only offset 0x6E4 HTR9 skipped event counter Read Only offset 0x6E8 HTR10 skipped event counter Read Only offset 0x6EC HTR11 skipped event counter Read Only offset 0x6F0 HTR12 skipped event counter Read Only offset 0x6F4 HTR13 skipped event counter Read Only offset 0x6F8 HTR14 skipped event counter Read Only offset 0x7C0 HTR0 padded event counter Read Only offset 0x7C4 HTR1 padded event counter Read Only offset 0x7C8 HTR2 padded event counter Read Only offset 0x7CC HTR3 padded event counter Read Only offset 0x7D0 HTR4 padded event counter Read Only offset 0x7D4 HTR5 padded event counter Read Only offset 0x7D8 HTR6 padded event counter Read Only offset 0x7DC HTR7 padded event counter Read Only offset 0x7E0 HTR8 padded event counter Read Only offset 0x7E4 HTR9 padded event counter Read Only offset 0x7E8 HTR10 padded event counter Read Only offset 0x7EC HTR11 padded event counter Read Only offset 0x7F0 HTR12 padded event counter Read Only offset 0x7F4 HTR13 padded event counter Read Only offset 0x7F8 HTR14 padded event counter Read Only offset 0x800 HTR0 events with CERR counter Read Only offset 0x804 HTR0 events with UERR counter Read Only offset 0x808 HTR0 truncated events counter Read Only offset 0x80c HTR0 events with BADID counter Read Only offset 0x810 HTR0 events CRC error detected at LRB Read Only offset 0x814 HTR0 events shorter than 32 bytes Read Only offset 0x818 HTR0 events with structure error Read Only offset 0x81c HTR0 events with odd 16bit word counts Read Only offset 0x820 HTR0 CRC error at event building Read Only offset 0x824 HTR0 CRC error disagreement counts Read Only offset 0x828 HTR0 word counts low Read Only offset 0x82c HTR0 word counts high Read Only offset 0x830 HTR0 event counts low Read Only offset 0x834 HTR0 event counts high Read Only offset 0x840 HTR0 events with OW flag Read Only offset 0x844 HTR0 events with BZ flag Read Only offset 0x848 HTR0 events with EE flag Read Only offset 0x84c HTR0 events with RL flag Read Only offset 0x850 HTR0 events with LE flag Read Only offset 0x854 HTR0 events with LW flag Read Only offset 0x858 HTR0 events with OD flag Read Only offset 0x85c HTR0 events with CK flag Read Only offset 0x860 HTR0 events with BE flag Read Only offset 0x864 HTR0 events with HTR status bit 15 = 0 Read Only offset 0x868 HTR0 events with CT flag Read Only offset 0x86c HTR0 events with bit9 flag Read Only offset 0x870 HTR0 events with bit10 flag Read Only offset 0x874 HTR0 events with bit11 flag Read Only offset 0x878 HTR0 events with bit12 flag Read Only offset 0x87c HTR0 events with US flag Read Only offset 0x880 HTR1 events with CERR counter Read Only offset 0x884 HTR1 events with UERR counter Read Only offset 0x888 HTR1 truncated events counter Read Only offset 0x88c HTR1 events with BADID counter Read Only offset 0x890 HTR1 events CRC error detected at LRB Read Only offset 0x894 HTR1 events shorter than 32 bytes Read Only offset 0x898 HTR1 events with structure error Read Only offset 0x89c HTR1 events with odd 16bit word counts Read Only offset 0x8a0 HTR1 CRC error at event building Read Only offset 0x8a4 HTR1 CRC error disagreement counts Read Only offset 0x8a8 HTR1 word counts low Read Only offset 0x8ac HTR1 word counts high Read Only offset 0x8b0 HTR1 event counts low Read Only offset 0x8b4 HTR1 event counts high Read Only offset 0x8c0 HTR1 events with OW flag Read Only offset 0x8c4 HTR1 events with BZ flag Read Only offset 0x8c8 HTR1 events with EE flag Read Only offset 0x8cc HTR1 events with RL flag Read Only offset 0x8d0 HTR1 events with LE flag Read Only offset 0x8d4 HTR1 events with LW flag Read Only offset 0x8d8 HTR1 events with OD flag Read Only offset 0x8dc HTR1 events with CK flag Read Only offset 0x8e0 HTR1 events with BE flag Read Only offset 0x8e4 HTR1 events with HTR status bit 15 = 0 Read Only offset 0x8e8 HTR1 events with CT flag Read Only offset 0x8ec HTR1 events with bit9 flag Read Only offset 0x8f0 HTR1 events with bit10 flag Read Only offset 0x8f4 HTR1 events with bit11 flag Read Only offset 0x8f8 HTR1 events with bit12 flag Read Only offset 0x8fc HTR1 events with US flag Read Only offset 0x900 HTR2 events with CERR counter Read Only offset 0x904 HTR2 events with UERR counter Read Only offset 0x908 HTR2 truncated events counter Read Only offset 0x90c HTR2 events with BADID counter Read Only offset 0x910 HTR2 events CRC error detected at LRB Read Only offset 0x914 HTR2 events shorter than 32 bytes Read Only offset 0x918 HTR2 events with structure error Read Only offset 0x91c HTR2 events with odd 16bit word counts Read Only offset 0x920 HTR2 CRC error at event building Read Only offset 0x924 HTR2 CRC error disagreement counts Read Only offset 0x928 HTR2 word counts low Read Only offset 0x92c HTR2 word counts high Read Only offset 0x930 HTR2 event counts low Read Only offset 0x934 HTR2 event counts high Read Only offset 0x940 HTR2 events with OW flag Read Only offset 0x944 HTR2 events with BZ flag Read Only offset 0x948 HTR2 events with EE flag Read Only offset 0x94c HTR2 events with RL flag Read Only offset 0x950 HTR2 events with LE flag Read Only offset 0x954 HTR2 events with LW flag Read Only offset 0x958 HTR2 events with OD flag Read Only offset 0x95c HTR2 events with CK flag Read Only offset 0x960 HTR2 events with BE flag Read Only offset 0x964 HTR2 events with HTR status bit 15 = 0 Read Only offset 0x968 HTR2 events with CT flag Read Only offset 0x96c HTR2 events with bit9 flag Read Only offset 0x970 HTR2 events with bit10 flag Read Only offset 0x974 HTR2 events with bit11 flag Read Only offset 0x978 HTR2 events with bit12 flag Read Only offset 0x97c HTR2 events with US flag Read Only offset 0x980 HTR3 events with CERR counter Read Only offset 0x984 HTR3 events with UERR counter Read Only offset 0x988 HTR3 truncated events counter Read Only offset 0x98c HTR3 events with BADID counter Read Only offset 0x990 HTR3 events CRC error detected at LRB Read Only offset 0x994 HTR3 events shorter than 32 bytes Read Only offset 0x998 HTR3 events with structure error Read Only offset 0x99c HTR3 events with odd 16bit word counts Read Only offset 0x9a0 HTR3 CRC error at event building Read Only offset 0x9a4 HTR3 CRC error disagreement counts Read Only offset 0x9a8 HTR3 word counts low Read Only offset 0x9ac HTR3 word counts high Read Only offset 0x9b0 HTR3 event counts low Read Only offset 0x9b4 HTR3 event counts high Read Only offset 0x9c0 HTR3 events with OW flag Read Only offset 0x9c4 HTR3 events with BZ flag Read Only offset 0x9c8 HTR3 events with EE flag Read Only offset 0x9cc HTR3 events with RL flag Read Only offset 0x9d0 HTR3 events with LE flag Read Only offset 0x9d4 HTR3 events with LW flag Read Only offset 0x9d8 HTR3 events with OD flag Read Only offset 0x9dc HTR3 events with CK flag Read Only offset 0x9e0 HTR3 events with BE flag Read Only offset 0x9e4 HTR3 events with HTR status bit 15 = 0 Read Only offset 0x9e8 HTR3 events with CT flag Read Only offset 0x9ec HTR3 events with bit9 flag Read Only offset 0x9f0 HTR3 events with bit10 flag Read Only offset 0x9f4 HTR3 events with bit11 flag Read Only offset 0x9f8 HTR3 events with bit12 flag Read Only offset 0x9fc HTR3 events with US flag Read Only offset 0xa00 HTR4 events with CERR counter Read Only offset 0xa04 HTR4 events with UERR counter Read Only offset 0xa08 HTR4 truncated events counter Read Only offset 0xa0c HTR4 events with BADID counter Read Only offset 0xa10 HTR4 events CRC error detected at LRB Read Only offset 0xa14 HTR4 events shorter than 32 bytes Read Only offset 0xa18 HTR4 events with structure error Read Only offset 0xa1c HTR4 events with odd 16bit word counts Read Only offset 0xa20 HTR4 CRC error at event building Read Only offset 0xa24 HTR4 CRC error disagreement counts Read Only offset 0xa28 HTR4 word counts low Read Only offset 0xa2c HTR4 word counts high Read Only offset 0xa30 HTR4 event counts low Read Only offset 0xa34 HTR4 event counts high Read Only offset 0xa40 HTR4 events with OW flag Read Only offset 0xa44 HTR4 events with BZ flag Read Only offset 0xa48 HTR4 events with EE flag Read Only offset 0xa4c HTR4 events with RL flag Read Only offset 0xa50 HTR4 events with LE flag Read Only offset 0xa54 HTR4 events with LW flag Read Only offset 0xa58 HTR4 events with OD flag Read Only offset 0xa5c HTR4 events with CK flag Read Only offset 0xa60 HTR4 events with BE flag Read Only offset 0xa64 HTR4 events with HTR status bit 15 = 0 Read Only offset 0xa68 HTR4 events with CT flag Read Only offset 0xa6c HTR4 events with bit9 flag Read Only offset 0xa70 HTR4 events with bit10 flag Read Only offset 0xa74 HTR4 events with bit11 flag Read Only offset 0xa78 HTR4 events with bit12 flag Read Only offset 0xa7c HTR4 events with US flag Read Only offset 0xa80 HTR5 events with CERR counter Read Only offset 0xa84 HTR5 events with UERR counter Read Only offset 0xa88 HTR5 truncated events counter Read Only offset 0xa8c HTR5 events with BADID counter Read Only offset 0xa90 HTR5 events CRC error detected at LRB Read Only offset 0xa94 HTR5 events shorter than 32 bytes Read Only offset 0xa98 HTR5 events with structure error Read Only offset 0xa9c HTR5 events with odd 16bit word counts Read Only offset 0xaa0 HTR5 CRC error at event building Read Only offset 0xaa4 HTR5 CRC error disagreement counts Read Only offset 0xaa8 HTR5 word counts low Read Only offset 0xaac HTR5 word counts high Read Only offset 0xab0 HTR5 event counts low Read Only offset 0xab4 HTR5 event counts high Read Only offset 0xac0 HTR5 events with OW flag Read Only offset 0xac4 HTR5 events with BZ flag Read Only offset 0xac8 HTR5 events with EE flag Read Only offset 0xacc HTR5 events with RL flag Read Only offset 0xad0 HTR5 events with LE flag Read Only offset 0xad4 HTR5 events with LW flag Read Only offset 0xad8 HTR5 events with OD flag Read Only offset 0xadc HTR5 events with CK flag Read Only offset 0xae0 HTR5 events with BE flag Read Only offset 0xae4 HTR5 events with HTR status bit 15 = 0 Read Only offset 0xae8 HTR5 events with CT flag Read Only offset 0xaec HTR5 events with bit9 flag Read Only offset 0xaf0 HTR5 events with bit10 flag Read Only offset 0xaf4 HTR5 events with bit11 flag Read Only offset 0xaf8 HTR5 events with bit12 flag Read Only offset 0xafc HTR5 events with US flag Read Only offset 0xb00 HTR6 events with CERR counter Read Only offset 0xb04 HTR6 events with UERR counter Read Only offset 0xb08 HTR6 truncated events counter Read Only offset 0xb0c HTR6 events with BADID counter Read Only offset 0xb10 HTR6 events CRC error detected at LRB Read Only offset 0xb14 HTR6 events shorter than 32 bytes Read Only offset 0xb18 HTR6 events with structure error Read Only offset 0xb1c HTR6 events with odd 16bit word counts Read Only offset 0xb20 HTR6 CRC error at event building Read Only offset 0xb24 HTR6 CRC error disagreement counts Read Only offset 0xb28 HTR6 word counts low Read Only offset 0xb2c HTR6 word counts high Read Only offset 0xb30 HTR6 event counts low Read Only offset 0xb34 HTR6 event counts high Read Only offset 0xb40 HTR6 events with OW flag Read Only offset 0xb44 HTR6 events with BZ flag Read Only offset 0xb48 HTR6 events with EE flag Read Only offset 0xb4c HTR6 events with RL flag Read Only offset 0xb50 HTR6 events with LE flag Read Only offset 0xb54 HTR6 events with LW flag Read Only offset 0xb58 HTR6 events with OD flag Read Only offset 0xb5c HTR6 events with CK flag Read Only offset 0xb60 HTR6 events with BE flag Read Only offset 0xb64 HTR6 events with HTR status bit 15 = 0 Read Only offset 0xb68 HTR6 events with CT flag Read Only offset 0xb6c HTR6 events with bit9 flag Read Only offset 0xb70 HTR6 events with bit10 flag Read Only offset 0xb74 HTR6 events with bit11 flag Read Only offset 0xb78 HTR6 events with bit12 flag Read Only offset 0xb7c HTR6 events with US flag Read Only offset 0xb80 HTR7 events with CERR counter Read Only offset 0xb84 HTR7 events with UERR counter Read Only offset 0xb88 HTR7 truncated events counter Read Only offset 0xb8c HTR7 events with BADID counter Read Only offset 0xb90 HTR7 events CRC error detected at LRB Read Only offset 0xb94 HTR7 events shorter than 32 bytes Read Only offset 0xb98 HTR7 events with structure error Read Only offset 0xb9c HTR7 events with odd 16bit word counts Read Only offset 0xba0 HTR7 CRC error at event building Read Only offset 0xba4 HTR7 CRC error disagreement counts Read Only offset 0xba8 HTR7 word counts low Read Only offset 0xbac HTR7 word counts high Read Only offset 0xbb0 HTR7 event counts low Read Only offset 0xbb4 HTR7 event counts high Read Only offset 0xbc0 HTR7 events with OW flag Read Only offset 0xbc4 HTR7 events with BZ flag Read Only offset 0xbc8 HTR7 events with EE flag Read Only offset 0xbcc HTR7 events with RL flag Read Only offset 0xbd0 HTR7 events with LE flag Read Only offset 0xbd4 HTR7 events with LW flag Read Only offset 0xbd8 HTR7 events with OD flag Read Only offset 0xbdc HTR7 events with CK flag Read Only offset 0xbe0 HTR7 events with BE flag Read Only offset 0xbe4 HTR7 events with HTR status bit 15 = 0 Read Only offset 0xbe8 HTR7 events with CT flag Read Only offset 0xbec HTR7 events with bit9 flag Read Only offset 0xbf0 HTR7 events with bit10 flag Read Only offset 0xbf4 HTR7 events with bit11 flag Read Only offset 0xbf8 HTR7 events with bit12 flag Read Only offset 0xbfc HTR7 events with US flag Read Only offset 0xc00 HTR8 events with CERR counter Read Only offset 0xc04 HTR8 events with UERR counter Read Only offset 0xc08 HTR8 truncated events counter Read Only offset 0xc0c HTR8 events with BADID counter Read Only offset 0xc10 HTR8 events CRC error detected at LRB Read Only offset 0xc14 HTR8 events shorter than 32 bytes Read Only offset 0xc18 HTR8 events with structure error Read Only offset 0xc1c HTR8 events with odd 16bit word counts Read Only offset 0xc20 HTR8 CRC error at event building Read Only offset 0xc24 HTR8 CRC error disagreement counts Read Only offset 0xc28 HTR8 word counts low Read Only offset 0xc2c HTR8 word counts high Read Only offset 0xc30 HTR8 event counts low Read Only offset 0xc34 HTR8 event counts high Read Only offset 0xc40 HTR8 events with OW flag Read Only offset 0xc44 HTR8 events with BZ flag Read Only offset 0xc48 HTR8 events with EE flag Read Only offset 0xc4c HTR8 events with RL flag Read Only offset 0xc50 HTR8 events with LE flag Read Only offset 0xc54 HTR8 events with LW flag Read Only offset 0xc58 HTR8 events with OD flag Read Only offset 0xc5c HTR8 events with CK flag Read Only offset 0xc60 HTR8 events with BE flag Read Only offset 0xc64 HTR8 events with HTR status bit 15 = 0 Read Only offset 0xc68 HTR8 events with CT flag Read Only offset 0xc6c HTR8 events with bit9 flag Read Only offset 0xc70 HTR8 events with bit10 flag Read Only offset 0xc74 HTR8 events with bit11 flag Read Only offset 0xc78 HTR8 events with bit12 flag Read Only offset 0xc7c HTR8 events with US flag Read Only offset 0xc80 HTR9 events with CERR counter Read Only offset 0xc84 HTR9 events with UERR counter Read Only offset 0xc88 HTR9 truncated events counter Read Only offset 0xc8c HTR9 events with BADID counter Read Only offset 0xc90 HTR9 events CRC error detected at LRB Read Only offset 0xc94 HTR9 events shorter than 32 bytes Read Only offset 0xc98 HTR9 events with structure error Read Only offset 0xc9c HTR9 events with odd 16bit word counts Read Only offset 0xca0 HTR9 CRC error at event building Read Only offset 0xca4 HTR9 CRC error disagreement counts Read Only offset 0xca8 HTR9 word counts low Read Only offset 0xcac HTR9 word counts high Read Only offset 0xcb0 HTR9 event counts low Read Only offset 0xcb4 HTR9 event counts high Read Only offset 0xcc0 HTR9 events with OW flag Read Only offset 0xcc4 HTR9 events with BZ flag Read Only offset 0xcc8 HTR9 events with EE flag Read Only offset 0xccc HTR9 events with RL flag Read Only offset 0xcd0 HTR9 events with LE flag Read Only offset 0xcd4 HTR9 events with LW flag Read Only offset 0xcd8 HTR9 events with OD flag Read Only offset 0xcdc HTR9 events with CK flag Read Only offset 0xce0 HTR9 events with BE flag Read Only offset 0xce4 HTR9 events with HTR status bit 15 = 0 Read Only offset 0xce8 HTR9 events with CT flag Read Only offset 0xcec HTR9 events with bit9 flag Read Only offset 0xcf0 HTR9 events with bit10 flag Read Only offset 0xcf4 HTR9 events with bit11 flag Read Only offset 0xcf8 HTR9 events with bit12 flag Read Only offset 0xcfc HTR9 events with US flag Read Only offset 0xd00 HTR10 events with CERR counter Read Only offset 0xd04 HTR10 events with UERR counter Read Only offset 0xd08 HTR10 truncated events counter Read Only offset 0xd0c HTR10 events with BADID counter Read Only offset 0xd10 HTR10 events CRC error detected at LRB Read Only offset 0xd14 HTR10 events shorter than 32 bytes Read Only offset 0xd18 HTR10 events with structure error Read Only offset 0xd1c HTR10 events with odd 16bit word counts Read Only offset 0xd20 HTR10 CRC error at event building Read Only offset 0xd24 HTR10 CRC error disagreement counts Read Only offset 0xd28 HTR10 word counts low Read Only offset 0xd2c HTR10 word counts high Read Only offset 0xd30 HTR10 event counts low Read Only offset 0xd34 HTR10 event counts high Read Only offset 0xd40 HTR10 events with OW flag Read Only offset 0xd44 HTR10 events with BZ flag Read Only offset 0xd48 HTR10 events with EE flag Read Only offset 0xd4c HTR10 events with RL flag Read Only offset 0xd50 HTR10 events with LE flag Read Only offset 0xd54 HTR10 events with LW flag Read Only offset 0xd58 HTR10 events with OD flag Read Only offset 0xd5c HTR10 events with CK flag Read Only offset 0xd60 HTR10 events with BE flag Read Only offset 0xd64 HTR10 events with HTR status bit 15 = 0 Read Only offset 0xd68 HTR10 events with CT flag Read Only offset 0xd6c HTR10 events with bit9 flag Read Only offset 0xd70 HTR10 events with bit10 flag Read Only offset 0xd74 HTR10 events with bit11 flag Read Only offset 0xd78 HTR10 events with bit12 flag Read Only offset 0xd7c HTR10 events with US flag Read Only offset 0xd80 HTR11 events with CERR counter Read Only offset 0xd84 HTR11 events with UERR counter Read Only offset 0xd88 HTR11 truncated events counter Read Only offset 0xd8c HTR11 events with BADID counter Read Only offset 0xd90 HTR11 events CRC error detected at LRB Read Only offset 0xd94 HTR11 events shorter than 32 bytes Read Only offset 0xd98 HTR11 events with structure error Read Only offset 0xd9c HTR11 events with odd 16bit word counts Read Only offset 0xda0 HTR11 CRC error at event building Read Only offset 0xda4 HTR11 CRC error disagreement counts Read Only offset 0xda8 HTR11 word counts low Read Only offset 0xdac HTR11 word counts high Read Only offset 0xdb0 HTR11 event counts low Read Only offset 0xdb4 HTR11 event counts high Read Only offset 0xdc0 HTR11 events with OW flag Read Only offset 0xdc4 HTR11 events with BZ flag Read Only offset 0xdc8 HTR11 events with EE flag Read Only offset 0xdcc HTR11 events with RL flag Read Only offset 0xdd0 HTR11 events with LE flag Read Only offset 0xdd4 HTR11 events with LW flag Read Only offset 0xdd8 HTR11 events with OD flag Read Only offset 0xddc HTR11 events with CK flag Read Only offset 0xde0 HTR11 events with BE flag Read Only offset 0xde4 HTR11 events with HTR status bit 15 = 0 Read Only offset 0xde8 HTR11 events with CT flag Read Only offset 0xdec HTR11 events with bit9 flag Read Only offset 0xdf0 HTR11 events with bit10 flag Read Only offset 0xdf4 HTR11 events with bit11 flag Read Only offset 0xdf8 HTR11 events with bit12 flag Read Only offset 0xdfc HTR11 events with US flag Read Only offset 0xe00 HTR12 events with CERR counter Read Only offset 0xe04 HTR12 events with UERR counter Read Only offset 0xe08 HTR12 truncated events counter Read Only offset 0xe0c HTR12 events with BADID counter Read Only offset 0xe10 HTR12 events CRC error detected at LRB Read Only offset 0xe14 HTR12 events shorter than 32 bytes Read Only offset 0xe18 HTR12 events with structure error Read Only offset 0xe1c HTR12 events with odd 16bit word counts Read Only offset 0xe20 HTR12 CRC error at event building Read Only offset 0xe24 HTR12 CRC error disagreement counts Read Only offset 0xe28 HTR12 word counts low Read Only offset 0xe2c HTR12 word counts high Read Only offset 0xe30 HTR12 event counts low Read Only offset 0xe34 HTR12 event counts high Read Only offset 0xe40 HTR12 events with OW flag Read Only offset 0xe44 HTR12 events with BZ flag Read Only offset 0xe48 HTR12 events with EE flag Read Only offset 0xe4c HTR12 events with RL flag Read Only offset 0xe50 HTR12 events with LE flag Read Only offset 0xe54 HTR12 events with LW flag Read Only offset 0xe58 HTR12 events with OD flag Read Only offset 0xe5c HTR12 events with CK flag Read Only offset 0xe60 HTR12 events with BE flag Read Only offset 0xe64 HTR12 events with HTR status bit 15 = 0 Read Only offset 0xe68 HTR12 events with CT flag Read Only offset 0xe6c HTR12 events with bit9 flag Read Only offset 0xe70 HTR12 events with bit10 flag Read Only offset 0xe74 HTR12 events with bit11 flag Read Only offset 0xe78 HTR12 events with bit12 flag Read Only offset 0xe7c HTR12 events with US flag Read Only offset 0xe80 HTR13 events with CERR counter Read Only offset 0xe84 HTR13 events with UERR counter Read Only offset 0xe88 HTR13 truncated events counter Read Only offset 0xe8c HTR13 events with BADID counter Read Only offset 0xe90 HTR13 events CRC error detected at LRB Read Only offset 0xe94 HTR13 events shorter than 32 bytes Read Only offset 0xe98 HTR13 events with structure error Read Only offset 0xe9c HTR13 events with odd 16bit word counts Read Only offset 0xea0 HTR13 CRC error at event building Read Only offset 0xea4 HTR13 CRC error disagreement counts Read Only offset 0xea8 HTR13 word counts low Read Only offset 0xeac HTR13 word counts high Read Only offset 0xeb0 HTR13 event counts low Read Only offset 0xeb4 HTR13 event counts high Read Only offset 0xec0 HTR13 events with OW flag Read Only offset 0xec4 HTR13 events with BZ flag Read Only offset 0xec8 HTR13 events with EE flag Read Only offset 0xecc HTR13 events with RL flag Read Only offset 0xed0 HTR13 events with LE flag Read Only offset 0xed4 HTR13 events with LW flag Read Only offset 0xed8 HTR13 events with OD flag Read Only offset 0xedc HTR13 events with CK flag Read Only offset 0xee0 HTR13 events with BE flag Read Only offset 0xee4 HTR13 events with HTR status bit 15 = 0 Read Only offset 0xee8 HTR13 events with CT flag Read Only offset 0xeec HTR13 events with bit9 flag Read Only offset 0xef0 HTR13 events with bit10 flag Read Only offset 0xef4 HTR13 events with bit11 flag Read Only offset 0xef8 HTR13 events with bit12 flag Read Only offset 0xefc HTR13 events with US flag Read Only offset 0xf00 HTR14 events with CERR counter Read Only offset 0xf04 HTR14 events with UERR counter Read Only offset 0xf08 HTR14 truncated events counter Read Only offset 0xf0c HTR14 events with BADID counter Read Only offset 0xf10 HTR14 events CRC error detected at LRB Read Only offset 0xf14 HTR14 events shorter than 32 bytes Read Only offset 0xf18 HTR14 events with structure error Read Only offset 0xf1c HTR14 events with odd 16bit word counts Read Only offset 0xf20 HTR14 CRC error at event building Read Only offset 0xf24 HTR14 CRC error disagreement counts Read Only offset 0xf28 HTR14 word counts low Read Only offset 0xf2c HTR14 word counts high Read Only offset 0xf30 HTR14 event counts low Read Only offset 0xf34 HTR14 event counts high Read Only offset 0xf40 HTR14 events with OW flag Read Only offset 0xf44 HTR14 events with BZ flag Read Only offset 0xf48 HTR14 events with EE flag Read Only offset 0xf4c HTR14 events with RL flag Read Only offset 0xf50 HTR14 events with LE flag Read Only offset 0xf54 HTR14 events with LW flag Read Only offset 0xf58 HTR14 events with OD flag Read Only offset 0xf5c HTR14 events with CK flag Read Only offset 0xf60 HTR14 events with BE flag Read Only offset 0xf64 HTR14 events with HTR status bit 15 = 0 Read Only offset 0xf68 HTR14 events with CT flag Read Only offset 0xf6c HTR14 events with bit9 flag Read Only offset 0xf70 HTR14 events with bit10 flag Read Only offset 0xf74 HTR14 events with bit11 flag Read Only offset 0xf78 HTR14 events with bit12 flag Read Only offset 0xf7c HTR14 events with US flag Read Only offset 0x3000-37fc Slink fifo R/W (During write, LSB address bits are ignored) To read, slink must be disabled offset 0x4000-7ffc TCCrx event number fifo Read Only Each event occupies a set of four consecutive 32-bit words when address bit 3-0 = 0: bit 23-0 event number, when address bit 3-0 = 4: bit 31 faked event number, bit 27-24 GapLaser counter bit 23-20 TTS state bit 19-16 cal_ty as in output data bit 15 calibration trigger received bit 14 pedestal trigger received bit 13 trigger within calibration window bit 12 valid calibration trigger bit 11-0 bx number, when address bit 3-0 = 8: bit 31-0 orbit number, when address bit 3-0 = c: not used all zero To get to these data, first read register 0x38. 0x4010 + bit 13-0 of register 0x38 is the starting address of the last set of event number data accepted by DCC. increment the address by 0x10 goes one event further backward. When the address reaches 0x8000, wrap it back to 0x4000 Since FIFO contents never get cleared, do not read more events than counter 0xbc0 indicates offset 0x8000-fffc SDRAM memory window R/W, read only monitor event buffer in run mode offset 0x10000 LRB0 base address offset 0x11000 LRB1 base address offset 0x12000 LRB2 base address offset 0x13000 LRB3 base address offset 0x14000 LRB4 base address LRB address offset: offset 0x0 LRB firmware version register, read only bit31-23 always reads 0 bit 22 if set, input channel 2 enabled bit 21 if set, input channel 1 enabled bit 20 if set, input channel 0 enabled bit 19 if set, DCM not locked bit 18-16 LRB ID (0-4) bit 15-0 LRB formware version offset 0x4 LRB memory page register, r/w bit31-14 not used, always reads 0 bit 13-0 LRB memory page address offset 0x8 LVDS input0 status register, read only bit31-12 always reads 0 bit 11 if set, no LVDS input signal bit 10-0 hardware debugging info offset 0xc LVDS input1 status register, read only bit31-12 always reads 0 bit 11 if set, no LVDS input signal bit 10-0 hardware debugging info offset 0x10 LVDS input2 status register, read only bit31-12 always reads 0 bit 11 if set, no LVDS input signal bit 10-0 hardware debugging info offset 0x400 LVDS input 0 word counter, 48-bit long occupies 8 byte space offset 0x408 LVDS input 0 CERR counter, 48-bit long occupies 8 byte space offset 0x410 LVDS input 0 UERR counter, 48-bit long occupies 8 byte space offset 0x418 LVDS input 0 event counter, 48-bit long occupies 8 byte space offset 0x420 LVDS input 0 event with CERR counter, 48-bit long occupies 8 byte space offset 0x428 LVDS input 0 event with UERR counter, 48-bit long occupies 8 byte space offset 0x430 LVDS input 0 truncated event counter, 48-bit long occupies 8 byte space offset 0x438 LVDS input 0 BADID counter, 48-bit long occupies 8 byte space offset 0x440 LVDS input 0 CRC error counter, 48-bit long occupies 8 byte space offset 0x500 LVDS input 1 word counter, 48-bit long occupies 8 byte space offset 0x508 LVDS input 1 CERR counter, 48-bit long occupies 8 byte space offset 0x510 LVDS input 1 UERR counter, 48-bit long occupies 8 byte space offset 0x518 LVDS input 1 event counter, 48-bit long occupies 8 byte space offset 0x520 LVDS input 1 event with CERR counter, 48-bit long occupies 8 byte space offset 0x528 LVDS input 1 event with UERR counter, 48-bit long occupies 8 byte space offset 0x530 LVDS input 1 truncated event counter, 48-bit long occupies 8 byte space offset 0x538 LVDS input 1 BADID counter, 48-bit long occupies 8 byte space offset 0x540 LVDS input 1 CRC error counter, 48-bit long occupies 8 byte space offset 0x600 LVDS input 2 word counter, 48-bit long occupies 8 byte space offset 0x608 LVDS input 2 CERR counter, 48-bit long occupies 8 byte space offset 0x610 LVDS input 2 UERR counter, 48-bit long occupies 8 byte space offset 0x618 LVDS input 2 event counter, 48-bit long occupies 8 byte space offset 0x620 LVDS input 2 event with CERR counter, 48-bit long occupies 8 byte space offset 0x628 LVDS input 2 event with UERR counter, 48-bit long occupies 8 byte space offset 0x630 LVDS input 2 truncated event counter, 48-bit long occupies 8 byte space offset 0x638 LVDS input 2 BADID counter, 48-bit long occupies 8 byte space offset 0x640 LVDS input 2 CRC error counter, 48-bit long occupies 8 byte space offset 0x800-ffc LRB memory access window, occupies 800 byte space R/w front panel LED display Blinking at 1Hz means error detected. If error does not persist, blinking lasts 5 to 10 seconds. Standard initialization procedure: operation comments write 0xffff0000 to 0x4 clear configuration register write n to 0x8 set up monitoring event scale factor to n+1 write 0x????? to 0xc set up HTR enable register write I2C_ID to 0x10 set up I2C ID register write 0x4 to 0x0 reset TTCrx set up configuration register, but do not put into run mode write 0x3 to 0x0 reset all registers and slink write 0x3 to 0x4 set to run mode and enable slink write 0xb to 0x0 reset all registers and slink after run started When not in run mode, data written to the Slink fifo range will be output to Slink if the latter is enabled. In run mode, writes to Slink fifo are ignored. Readout from Slink fifo does not change the status of the fifo. It always contains the last 512 32-bit words sent to Slink. You can access all registers in any modes. To read the monitored event, first read 0x34. In run mode(bit 0 of 0x4 set), this register gives the word count of the event pointed by the page register, it returns 0 when no event is available. Writing anything to 0x30 moves to next buffer when 0x34 is non zero. If 0x34 is zreo, the write to 0x30 is ignored. *************************************************************************** resync algorithm *************************************************************************** if register 0x18 is set to all zero, DCC can resync HTR event data based on event numbers as described below: If DCC event number and HTR event number a. match or b. their four LSBs are the same and the four LSBs of HTR event number are consecutive, event is accepted. Otherwise, DCC event number is compared with that of the next HTR event, if next event and the DCC event is of different type(one is calibration and the other is normal data), current event will be accepted without further check. If the next HTR event number is a. equal or b. smaller and the the difference is less than 16 and the four LSBs of HTR event number are consecutive, DCC will skip the current HTR event. If the next HTR event number is bigger and the the difference is less than 16 and the four LSBs of HTR event number are consecutive, DCC will pad in an empty event. Otherwise, DCC will read the current HTR event. In whichever case, as long as the errors do not persist, DCC will eventually resync the HTR data. *************************************************************************** link and memory test *************************************************************************** This test consists of two parts: 1. test LRBs' SDRAMs and LRBs' links to DSP chip: write 0xffff0000 to register 0x4(A32) to clear it write 0x1 to register 0x0(A32) to reset the registers write 0x1f to register 0x2c(A32) to start test read register 0x2500(A32), this should keep counting read register 0x2504(A32), bits 28-24 should all be zero to stop the test, write 0 to 0x2c 2. test DSP chips SDRAM and its link to VME chip: write 0x4dcc2009 to register 0x294(A24) write 0x4 to register 0x10(A24) read register 0x1c(A24), it should keep counting read register 0x18(A24), it should be zero Note that these two tests can be overlapped: starting from part 1 and continue to part 2. After a predetermined amount of time, check 0x1c(A24) and 0x18(A24) to make sure the second part of test does not fail. write 0x4dcc2009 to register 0x294(A24) write 0x0 to register 0x10(A24) This exits the second part of test. check registers 0x2500(A32) and 0x2504(A32) to make sure the first part of test does not fail. write 0 to register 0x2c(A32) to exit the test *************************************************************************** LED test *************************************************************************** write 0x20 to register 0x2c(A32) to start test, LED should show a shifting pattern, one and only one ON at a time. *************************************************************************** TTCrx test *************************************************************************** write 0xffff0000 to register 0x4(A32) to clear it write 14-bit TTCrx ID to register 0x10(A32) write 0x4 to register 0x0(A32) to reset TTCrx read register 0x14(A32), make sure bit 15 is '0'(I2C ready) write 0x9000 to register 0x14(A32) to read ID lower byte read register 0x14(A32) until bit 15 is '0'. If bit 14 is '0', bits 7-0 is the ID bits 7-0 write 0x9100 to register 0x14(A32) to read ID MSBs read register 0x14(A32) until bit 15 is '0'. If bit 14 is '0', bits 5-0 is the ID bits 13-8 *************************************************************************** ETHERNET chip access *************************************************************************** ethernet IP address is 192.168.1.SN, TCP port number is 23 where SN is DCC2 serial number bit7-0, for old DCC2, add 0x70 to it Only TCP mode is implemented. command sent to DCC2 is always eight bytes long 1. write command: first byte = 0xa0, second byte = 0x0, third byte = address bits 15-8, fourth word = address bits 7-0, fifth byte = data bits 31-24, and so forth 2. read command: first byte = 0x5, second byte = 0x0, third byte = address bits 15-8, fourth word = address bits 7-0, fifth byte = length bits 15-8, sixth byte = length bits 7-0, last two bytes = 0 length specifies number of 32-bit word data to be read The readout data are always in units of 4-bytes, with MSB first. The data always come with ascending address. *************************************************************************** backpalne connector test *************************************************************************** Data written to bits 11-0 of register 0x2718(A32) should be correctly readback from it, if the transmission signals are looped back to corresponding receiving signals. *************************************************************************** TTCrx commands *************************************************************************** Last command received can be read from bits 31-28 of register 0x14(A32) bit 31-24 correspond to TTCrx brcst 7-0 TTCrx brcst bits 4 and 2-0 are not used by DCC, and always reads back as '0' *************************************************************************** TTS test *************************************************************************** To test TTS, first write 0x1000 to register 0x4(A32) Now TTS outputs are controlled by bits 11 thru 8. To change TTS setting, first write 0xf000000 to register 0x4(A32) to reset bits 11-8, and then write desired value to these bits. bit11 => READY bit10 => BUSY bit9 => OUT_OF_SYNC bit8 => OVERFLOW ************************************************************************************* Instructions on how to recover project from zip files starting 14OCT2010 ************************************************************************************* 1. These projects require ISE12.3 to be installed on a Windows PC machine 2. add an enviroment variable "XIL_?PAR_?SKIPAUTOCLOCKPLACEMENT 1" 3. Create folders c:\iseproj\vme_dcc\dspISE12, c:\iseproj\vme_dcc\lrb400aISE12 and c:\iseproj\vme_dcc\vme400ISE12 4. unzip dspISE12.zip, lrb400aISE12.zip and vme400ISE12.zip to their corresponding folders. 5. start ISE12.3 and open the project to be processed. 6. click "Generate Programming File" to start compiling 7. expand "Configure Target Device" and click "Gnenerate Target PROM/ACE File" 8. Copy mcs file generated from the project folder to destination 9. repeat steps 5 thru 8 until all three mcs files are generated.