library IEEE; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; package vtx_pack is --constant vcc: std_logic := '1'; --constant gnd: std_logic := '0'; constant gnd1: std_logic_vector(0 downto 0) := "0"; constant gnd2: std_logic_vector(1 downto 0) := "00"; constant gnd3: std_logic_vector(2 downto 0) := "000"; constant gnd4: std_logic_vector(3 downto 0) := "0000"; constant gnd5: std_logic_vector(4 downto 0) := "00000"; constant gnd6: std_logic_vector(5 downto 0) := "000000"; constant gnd7: std_logic_vector(6 downto 0) := "0000000"; constant gnd8: std_logic_vector(7 downto 0) := x"00"; constant gnd16: std_logic_vector(15 downto 0) := x"0000"; constant gnd32: std_logic_vector(31 downto 0) := x"00000000"; function conv_v2u(arg: std_logic_vector) return unsigned; function conv_u2v(arg: unsigned) return std_logic_vector; -- this file contains: -- ipad, opad, iopad, ibuf, obuf, obuft, ipin, opin, iopin -- ibufg, bufg, i_reg, o_reg, io_reg, srle_n, delayN, l_ud_cntr, ram16XNd -- ramb16_s9_s36,ramb16_s18_s18, ramb16_s9_s18,ramb16_s36_s36, srl16e, DCM, CLKDLL, FDDRRSE --------------------------------------------------------------------------------------- component ipad port ( pad: out std_logic); end component; --------------------------------------------------------------------------------------- component opad port ( pad: in std_logic); end component; --------------------------------------------------------------------------------------- component iopad port ( iopad: inout std_logic); end component; --------------------------------------------------------------------------------------- component lut1 generic (INIT: bit_vector := x"1"); port ( I0: in std_logic; O: out std_logic); end component; --------------------------------------------------------------------------------------- component ibuf port ( o : out std_logic; i : in std_logic); end component; --------------------------------------------------------------------------------------- component iobuf port ( o : out std_logic; io : inout std_logic; t : in std_logic; i : in std_logic); end component; --------------------------------------------------------------------------------------- component ibufg port ( o : out std_logic; i : in std_logic); end component; --------------------------------------------------------------------------------------- -------------------------------- component bufg port ( o : out std_logic; i : in std_logic); end component; --------------------------------------------------------------------------------------- component FD port ( D: in std_logic; C: in std_logic; Q: out std_logic); end component; --------------------------------------------------------------------------------------- component FD_1 port ( D: in std_logic; C: in std_logic; Q: out std_logic); end component; --------------------------------------------------------------------------------------- component IFD port ( D: in std_logic; C: in std_logic; Q: out std_logic); end component; --------------------------------------------------------------------------------------- component IFD_1 port ( D: in std_logic; C: in std_logic; Q: out std_logic); end component; --------------------------------------------------------------------------------------- component OFD port ( D: in std_logic; C: in std_logic; Q: out std_logic); end component; --------------------------------------------------------------------------------------- component IFDX port ( D: in std_logic; CE: in std_logic; C: in std_logic; Q: out std_logic); end component; --------------------------------------------------------------------------------------- component OFDX port ( D: in std_logic; CE: in std_logic; C: in std_logic; Q: out std_logic); end component; --------------------------------------------------------------------------------------- component obuft port ( o : out std_logic; t : in std_logic; i : in std_logic); end component; --------------------------------------------------------------------------------------- component obuf port ( o : out std_logic; i : in std_logic); end component; -------------------------------- component ipin port ( i: out std_logic ); end component; --------------------------------------------------------------------------------------- -------------------------------- component opin port ( o: in std_logic; t: in std_logic ); end component; --------------------------------------------------------------------------------------- -------------------------------- component iopin port ( i: out std_logic; o: in std_logic; t: in std_logic ); end component; --------------------------------------------------------------------------------------- -- input with register component i_reg port ( iq: out STD_LOGIC; ice: in STD_LOGIC; c: in STD_LOGIC); end component; --------------------------------------------------------------------------------------- -- output with registers component o_reg port ( oq: in STD_LOGIC; tq: in STD_LOGIC; oce: in STD_LOGIC; tce: in STD_LOGIC; c: in STD_LOGIC ); end component; --------------------------------------------------------------------------------------- -- input/output with registers component io_reg port ( bdir: inout STD_LOGIC; iq: out STD_LOGIC; oq: in STD_LOGIC; tq: in STD_LOGIC; ice: in STD_LOGIC; oce: in STD_LOGIC; tce: in STD_LOGIC; c: in STD_LOGIC ); end component; ------------------------------------------------------------------------------------- -- muxcy -------- component muxcy port (S,DI,CI: in std_logic; O: out std_logic); end component; --------- component muxcy_d port (S,DI,CI: in std_logic; LO: out std_logic; O: out std_logic); end component; -- mult_and ----------- component mult_and port (I0,I1: in std_logic; LO: out std_logic); end component; -- xorcy -------- component xorcy port (LI,CI: in std_logic; O: out std_logic); end component; -- orcy -------- component orcy port (I,CI: in std_logic; O: out std_logic); end component; -- fdrse -------- component fdrse port (D,CE,C,R,S: in std_logic; Q: out std_logic); end component; ----------------------- component LDE port ( D: in std_logic; GE: in std_logic; G: in std_logic; Q: out std_logic); end component; ----------------------- component FDC port ( D: in std_logic; CLR: in std_logic; C: in std_logic; Q: out std_logic); end component; ----------------------- component FDP port ( D: in std_logic; PRE: in std_logic; C: in std_logic; Q: out std_logic); end component; ----------------------- component FDE port ( D: in std_logic; CE: in std_logic; C: in std_logic; Q: out std_logic); end component; ----------------------- component FDR port ( D: in std_logic; R: in std_logic; C: in std_logic; Q: out std_logic); end component; ----------------------- component FDS port ( D: in std_logic; S: in std_logic; C: in std_logic; Q: out std_logic); end component; ------------------------------------------------------------------------------------- -- this is a N bit wide LUT shift registers component srle_N generic (N: positive := 16); port ( d: in STD_LOGIC_VECTOR (N-1 downto 0); a: in STD_LOGIC_VECTOR (3 downto 0); ce: in STD_LOGIC; clk: in STD_LOGIC; q: out STD_LOGIC_VECTOR (N-1 downto 0) ); end component; ------------------------------------------------------------------------------------- -- delay d from 2 to 17 clocks with ce = '1' component delayN generic (N: positive := 2; INIT : bit_vector := x"0000"); port ( c: in STD_LOGIC; d: in STD_LOGIC; ce: in STD_LOGIC; q: out STD_LOGIC ); end component; ------------------------------------------------------------------------------------- component adsuN generic (N: positive := 8); port ( a: in std_logic_vector (N-1 downto 0); b: in std_logic_vector (N-1 downto 0); add: in std_logic; ci: in std_logic; s: out std_logic_vector (N-1 downto 0); co: out std_logic; ovfl: out std_logic ); end component; ------------------------------------------------------------------------------------- component addN generic (N: positive := 8); port ( a: in std_logic_vector (N-1 downto 0); b: in std_logic_vector (N-1 downto 0); rst_n: in std_logic; ci: in std_logic; s: out std_logic_vector (N-1 downto 0); co: out std_logic; ovfl: out std_logic ); end component; ------------------------------------------------------------------------------------- -- this is a loadable, up/down counter with set, reset and clock enable inputs component l_ud_cntr generic (N: positive := 8); port ( d: in std_logic_vector (N-1 downto 0); load_n: in std_logic; up: in std_logic; reset: in std_logic; set: in std_logic; ec: in std_logic; en_cnt: in std_logic; clk: in std_logic; q: out std_logic_vector (N-1 downto 0); carry: out std_logic ); end component; ------------------------------------------------------------------------------------- -- this is a loadable up counter with set, reset and clock enable inputs component l_cntr generic (N: positive := 8; ld_plus_one : boolean := false ); port ( d: in std_logic_vector (N-1 downto 0); load: in std_logic; reset: in std_logic; set: in std_logic; ec: in std_logic; en_cnt: in std_logic; clk: in std_logic; q: out std_logic_vector (N-1 downto 0); carry: out std_logic ); end component; ------------------------------------------------------------------------------------- -- this is a loadable up counter with set, reset and clock enable inputs component l_d_cntr generic (N: positive := 8; ld_minus_one : boolean := false ); port ( d: in std_logic_vector (N-1 downto 0); load: in std_logic; reset: in std_logic; set: in std_logic; ec: in std_logic; en_cnt: in std_logic; clk: in std_logic; q: out std_logic_vector (N-1 downto 0); carry: out std_logic ); end component; ------------------------------ component ldenaddsub generic (N: integer := 8); -- define input and output ports port ( -- a and b are the input numbers to be added a: in std_logic_vector (N-1 downto 0); b: in std_logic_vector (N-1 downto 0); -- carrylsb is the value of ci(0). -- For the normal funtionality => ci(0) must be assigned to subtract. carry_i: in std_logic; -- subtract signal determins if a and b are added or subtracted subtract: in std_logic; -- load is active high, when aserted, a is forced to zero load: in std_logic; -- reset resets the counter register value to all zeros reset: in std_logic; -- set will set the counter to all ones set: in std_logic; -- ec enables the registers' clock enable ec: in std_logic; -- clk is the clock signal used to drive the counter registers clk: in std_logic; -- sum is the output value sum: out std_logic_vector (N-1 downto 0); -- sumr is the output value registered sumr: out std_logic_vector (N-1 downto 0); -- carry out carry_o: out std_logic ); end component; ------------------------------ component ldenaddsubs generic (N: integer := 8); -- define input and output ports port ( -- a and b are the input numbers to be added a: in std_logic_vector (N-1 downto 0); b: in std_logic_vector (N-1 downto 0); -- carrylsb is the value of ci(0). -- For the normal funtionality => ci(0) must be assigned to subtract. carry_i: in std_logic; -- subtract signal determins if a and b are added or subtracted subtract: in std_logic; -- load is active high, when aserted, a is forced to zero load: in std_logic; -- reset resets the counter register value to all zeros reset: in std_logic; -- set will set the counter to all ones set: in std_logic; -- ec enables the registers' clock enable ec: in std_logic; -- clk is the clock signal used to drive the counter registers clk: in std_logic; -- sum is the output value sum: out std_logic_vector (N-1 downto 0); -- sumr is the output value registered sumr: out std_logic_vector (N-1 downto 0); -- carry out carry_o: out std_logic ); end component; ---------------------------------------------------------------------------------------- -- declare lut dpram component ram16XNd generic ( N: positive := 16); port ( clk: in STD_LOGIC; we: in STD_LOGIC; d: in STD_LOGIC_VECTOR (N-1 downto 0); a: in STD_LOGIC_VECTOR (3 downto 0); dpra: in STD_LOGIC_VECTOR (3 downto 0); spo: out STD_LOGIC_VECTOR (N-1 downto 0); dpo: out STD_LOGIC_VECTOR (N-1 downto 0) ); end component; component ram32XNd generic ( N: positive := 16); port ( clk: in STD_LOGIC; we: in STD_LOGIC; d: in STD_LOGIC_VECTOR (N-1 downto 0); a: in STD_LOGIC_VECTOR (4 downto 0); dpra: in STD_LOGIC_VECTOR (4 downto 0); spo: out STD_LOGIC_VECTOR (N-1 downto 0); dpo: out STD_LOGIC_VECTOR (N-1 downto 0) ); end component; -- single component ram32XNs generic ( N: positive := 16); port ( clk: in STD_LOGIC; we: in STD_LOGIC; d: in STD_LOGIC_VECTOR (N-1 downto 0); a: in STD_LOGIC_VECTOR (4 downto 0); o: out STD_LOGIC_VECTOR (N-1 downto 0) ); end component; component ram16XNs generic (N: positive := 16); port ( clk: in STD_LOGIC; we: in STD_LOGIC; d: in STD_LOGIC_VECTOR (N-1 downto 0); a: in STD_LOGIC_VECTOR (3 downto 0); o: out STD_LOGIC_VECTOR (N-1 downto 0)); end component; --------------------------------------------------------------------- component RAMB16_S1 -- generic ( WRITE_MODE : string := "WRITE_FIRST"; INIT : bit_vector := "0"; SRVAL : bit_vector := "0"; INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000" ); -- port (DI : in STD_LOGIC_VECTOR (0 downto 0); EN : in STD_logic; WE : in STD_logic; SSR : in STD_logic; CLK : in STD_logic; ADDR : in STD_LOGIC_VECTOR (13 downto 0); DO : out STD_LOGIC_VECTOR (0 downto 0) ); end component; --------------------------------------------------------------------- component RAMB16_S2 -- generic ( WRITE_MODE : string := "WRITE_FIRST"; INIT : bit_vector := X"0"; SRVAL : bit_vector := X"0"; INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000" ); -- port (DI : in STD_LOGIC_VECTOR (1 downto 0); EN : in STD_logic; WE : in STD_logic; SSR : in STD_logic; CLK : in STD_logic; ADDR : in STD_LOGIC_VECTOR (12 downto 0); DO : out STD_LOGIC_VECTOR (1 downto 0) ); end component; ----------------------------------------------------------------------- component RAMB16_S9 -- generic ( WRITE_MODE : string := "NO_CHANGE"; INIT : bit_vector := X"000"; SRVAL : bit_vector := X"000"; INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000" ); -- port (DI : in STD_LOGIC_VECTOR (7 downto 0); DIP : in STD_LOGIC_VECTOR (0 downto 0); EN : in STD_logic; WE : in STD_logic; SSR : in STD_logic; CLK : in STD_logic; ADDR : in STD_LOGIC_VECTOR (10 downto 0); DO : out STD_LOGIC_VECTOR (7 downto 0); DOP : out STD_LOGIC_VECTOR (0 downto 0) ); end component; ---------------------------------------------------------------------------------------- component RAMB16_S1_S1 generic( SIM_COLLISION_CHECK : string := "NONE"; write_mode_a: string := "NO_CHANGE"; -- write_first(default)/read_first/no_change init_b: bit_vector(0 downto 0) := "0"; srval_b: bit_vector(0 downto 0) := "0"; write_mode_b: string := "NO_CHANGE"; -- write_first(default)/read_first/no_change init_a: bit_vector(0 downto 0) := "0"; srval_a: bit_vector(0 downto 0) := "0"; INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"); port( dia: in std_logic_vector(0 downto 0); addra: in std_logic_vector(13 downto 0); clka: in std_logic; ssra: in std_logic; ena: in std_logic; wea: in std_logic; doa: out std_logic_vector(0 downto 0); dib: in std_logic_vector(0 downto 0); addrb: in std_logic_vector(13 downto 0); clkb: in std_logic; ssrb: in std_logic; enb: in std_logic; web: in std_logic; dob: out std_logic_vector(0 downto 0)); end component; ----- Component RAMB16_S4_S4 ----- component RAMB16_S4_S4 -- generic ( SIM_COLLISION_CHECK : string := "NONE"; WRITE_MODE_A : string := "WRITE_FIRST"; WRITE_MODE_B : string := "WRITE_FIRST"; INIT_A : bit_vector := X"0"; SRVAL_A : bit_vector := X"0"; INIT_B : bit_vector := X"0"; SRVAL_B : bit_vector := X"0"; INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0a : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0b : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0c : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0d : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0e : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0f : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1a : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1b : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1c : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1d : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1e : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1f : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2a : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2b : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2c : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2d : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2e : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2f : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3a : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3b : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3c : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3d : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3e : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3f : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000" ); -- port (DIA : in STD_LOGIC_VECTOR (3 downto 0); DIB : in STD_LOGIC_VECTOR (3 downto 0); ENA : in STD_logic; ENB : in STD_logic; WEA : in STD_logic; WEB : in STD_logic; SSRA : in STD_logic; SSRB : in STD_logic; CLKA : in STD_logic; CLKB : in STD_logic; ADDRA : in STD_LOGIC_VECTOR (11 downto 0); ADDRB : in STD_LOGIC_VECTOR (11 downto 0); DOA : out STD_LOGIC_VECTOR (3 downto 0); DOB : out STD_LOGIC_VECTOR (3 downto 0) ); end component; ----- Component RAMB16_S2_S2 ----- component RAMB16_S2_S2 -- generic ( SIM_COLLISION_CHECK : string := "NONE"; WRITE_MODE_A : string := "WRITE_FIRST"; WRITE_MODE_B : string := "WRITE_FIRST"; INIT_A : bit_vector := "00"; SRVAL_A : bit_vector := "00"; INIT_B : bit_vector := "00"; SRVAL_B : bit_vector := "00"; INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0a : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0b : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0c : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0d : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0e : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0f : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1a : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1b : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1c : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1d : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1e : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1f : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2a : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2b : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2c : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2d : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2e : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2f : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3a : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3b : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3c : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3d : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3e : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3f : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000" ); -- port (DIA : in STD_LOGIC_VECTOR (1 downto 0); DIB : in STD_LOGIC_VECTOR (1 downto 0); ENA : in STD_logic; ENB : in STD_logic; WEA : in STD_logic; WEB : in STD_logic; SSRA : in STD_logic; SSRB : in STD_logic; CLKA : in STD_logic; CLKB : in STD_logic; ADDRA : in STD_LOGIC_VECTOR (12 downto 0); ADDRB : in STD_LOGIC_VECTOR (12 downto 0); DOA : out STD_LOGIC_VECTOR (1 downto 0); DOB : out STD_LOGIC_VECTOR (1 downto 0) ); end component; ----- Component RAMB16_S4_S36 ----- component RAMB16_S4_S36 -- generic ( SIM_COLLISION_CHECK : string := "NONE"; WRITE_MODE_A : string := "WRITE_FIRST"; WRITE_MODE_B : string := "WRITE_FIRST"; INIT_A : bit_vector := X"0"; SRVAL_A : bit_vector := X"0"; INIT_B : bit_vector := X"000000000"; SRVAL_B : bit_vector := X"000000000"; INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000" ); -- port (DIA : in STD_LOGIC_VECTOR (3 downto 0); DIB : in STD_LOGIC_VECTOR (31 downto 0); DIPB : in STD_LOGIC_VECTOR (3 downto 0); ENA : in STD_logic; ENB : in STD_logic; WEA : in STD_logic; WEB : in STD_logic; SSRA : in STD_logic; SSRB : in STD_logic; CLKA : in STD_logic; CLKB : in STD_logic; ADDRA : in STD_LOGIC_VECTOR (11 downto 0); ADDRB : in STD_LOGIC_VECTOR (8 downto 0); DOA : out STD_LOGIC_VECTOR (3 downto 0); DOB : out STD_LOGIC_VECTOR (31 downto 0); DOPB : out STD_LOGIC_VECTOR (3 downto 0) ); end component; ----- Component RAMB16_S4 ----- component RAMB16_S4 -- generic ( WRITE_MODE : string := "WRITE_FIRST"; INIT : bit_vector := X"0"; SRVAL : bit_vector := X"0"; INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0a : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0b : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0c : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0d : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0e : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0f : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1a : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1b : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1c : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1d : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1e : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1f : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2a : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2b : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2c : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2d : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2e : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2f : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3a : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3b : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3c : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3d : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3e : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3f : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000" ); -- port (DI : in STD_LOGIC_VECTOR (3 downto 0); EN : in STD_logic; WE : in STD_logic; SSR : in STD_logic; CLK : in STD_logic; ADDR : in STD_LOGIC_VECTOR (11 downto 0); DO : out STD_LOGIC_VECTOR (3 downto 0) ); end component; ---------------------------------------------------------------------------------------- component RAMB16_S1_S18 -- generic ( SIM_COLLISION_CHECK : string := "NONE"; WRITE_MODE_A : string := "NO_CHANGE"; -- write_first(default)/read_first/no_change WRITE_MODE_B : string := "NO_CHANGE"; -- write_first(default)/read_first/no_change INIT_A : bit_vector := X"0"; SRVAL_A : bit_vector := X"0"; INIT_B : bit_vector := X"00000"; SRVAL_B : bit_vector := X"00000" ); -- port (DIA : in STD_LOGIC_VECTOR (0 downto 0); DIB : in STD_LOGIC_VECTOR (15 downto 0); DIPB : in STD_LOGIC_VECTOR (1 downto 0); ENA : in STD_logic; ENB : in STD_logic; WEA : in STD_logic; WEB : in STD_logic; SSRA : in STD_logic; SSRB : in STD_logic; CLKA : in STD_logic; CLKB : in STD_logic; ADDRA : in STD_LOGIC_VECTOR (13 downto 0); ADDRB : in STD_LOGIC_VECTOR (9 downto 0); DOA : out STD_LOGIC_VECTOR (0 downto 0); DOB : out STD_LOGIC_VECTOR (15 downto 0); DOPB : out STD_LOGIC_VECTOR (1 downto 0) ); end component; --------------------------------------------------------------------------- --------------------------------------------------------------------------- component RAMB16_S1_S9 generic( SIM_COLLISION_CHECK : string := "NONE"; write_mode_a: string := "NO_CHANGE"; -- write_first(default)/read_first/no_change init_a: bit_vector(0 downto 0) := "0"; srval_a: bit_vector(0 downto 0) := "0"; write_mode_b: string := "NO_CHANGE"; -- write_first(default)/read_first/no_change init_b: bit_vector := x"000"; srval_b: bit_vector := x"000"; INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0a : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0b : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0c : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0d : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0e : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0f : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1a : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1b : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1c : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1d : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1e : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1f : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2a : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2b : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2c : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2d : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2e : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2f : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3a : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3b : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3c : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3d : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3e : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3f : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000" ); port( dia: in std_logic_vector(0 downto 0); addra: in std_logic_vector(13 downto 0); clka: in std_logic; ssra: in std_logic; ena: in std_logic; wea: in std_logic; doa: out std_logic_vector(0 downto 0); dib: in std_logic_vector(7 downto 0); dipb: in std_logic_vector(0 downto 0); addrb: in std_logic_vector(10 downto 0); clkb: in std_logic; ssrb: in std_logic; enb: in std_logic; web: in std_logic; dob: out std_logic_vector(7 downto 0); dopb: out std_logic_vector(0 downto 0)); end component; --------------------------------------------------------------------------- component RAMB16_S9_S9 generic( SIM_COLLISION_CHECK : string := "NONE"; write_mode_a: string := "NO_CHANGE"; -- write_first(default)/read_first/no_change init_b: bit_vector := x"000"; srval_b: bit_vector := x"000"; write_mode_b: string := "NO_CHANGE"; -- write_first(default)/read_first/no_change init_a: bit_vector := x"000"; srval_a: bit_vector := x"000"; INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0a : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0b : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0c : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0d : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0e : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0f : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1a : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1b : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1c : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1d : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1e : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1f : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2a : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2b : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2c : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2d : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2e : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2f : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3a : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3b : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3c : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3d : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3e : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3f : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000" ); port( dia: in std_logic_vector(7 downto 0); dipa: in std_logic_vector(0 downto 0); addra: in std_logic_vector(10 downto 0); clka: in std_logic; ssra: in std_logic; ena: in std_logic; wea: in std_logic; doa: out std_logic_vector(7 downto 0); dopa: out std_logic_vector(0 downto 0); dib: in std_logic_vector(7 downto 0); dipb: in std_logic_vector(0 downto 0); addrb: in std_logic_vector(10 downto 0); clkb: in std_logic; ssrb: in std_logic; enb: in std_logic; web: in std_logic; dob: out std_logic_vector(7 downto 0); dopb: out std_logic_vector(0 downto 0)); end component; --------------------------------------------------------------------------- component RAMB16_S9_S18 generic( SIM_COLLISION_CHECK : string := "NONE"; write_mode_a: string := "NO_CHANGE"; -- write_first(default)/read_first/no_change init_b: bit_vector(17 downto 0) := "000000000000000000"; srval_b: bit_vector(17 downto 0) := "000000000000000000"; write_mode_b: string := "NO_CHANGE"; -- write_first(default)/read_first/no_change init_a: bit_vector(8 downto 0) := "000000000"; srval_a: bit_vector(8 downto 0) := "000000000"); port( dia: in std_logic_vector(7 downto 0); dipa: in std_logic_vector(0 downto 0); addra: in std_logic_vector(10 downto 0); clka: in std_logic; ssra: in std_logic; ena: in std_logic; wea: in std_logic; doa: out std_logic_vector(7 downto 0); dopa: out std_logic_vector(0 downto 0); dib: in std_logic_vector(15 downto 0); dipb: in std_logic_vector(1 downto 0); addrb: in std_logic_vector(9 downto 0); clkb: in std_logic; ssrb: in std_logic; enb: in std_logic; web: in std_logic; dob: out std_logic_vector(15 downto 0); dopb: out std_logic_vector(1 downto 0)); end component; ---------------------------------------------------------------------------------------- component RAMB16_S9_S36 generic( SIM_COLLISION_CHECK : string := "NONE"; write_mode_a: string := "NO_CHANGE"; -- write_first(default)/read_first/no_change init_a: bit_vector(8 downto 0) := "000000000"; srval_a: bit_vector(8 downto 0) := "000000000"; write_mode_b: string := "NO_CHANGE"; -- write_first(default)/read_first/no_change init_b: bit_vector(35 downto 0) := x"000000000"; srval_b: bit_vector(35 downto 0) := x"000000000"); port( dia: in std_logic_vector(7 downto 0); dipa: in std_logic_vector(0 downto 0); addra: in std_logic_vector(10 downto 0); clka: in std_logic; ssra: in std_logic; ena: in std_logic; wea: in std_logic; doa: out std_logic_vector(7 downto 0); dopa: out std_logic_vector(0 downto 0); dib: in std_logic_vector(31 downto 0); dipb: in std_logic_vector(3 downto 0); addrb: in std_logic_vector(8 downto 0); clkb: in std_logic; ssrb: in std_logic; enb: in std_logic; web: in std_logic; dob: out std_logic_vector(31 downto 0); dopb: out std_logic_vector(3 downto 0)); end component; ---------------------------------------------------------------------------------------- component RAMB16_S18_S18 generic( SIM_COLLISION_CHECK : string := "NONE"; write_mode_a: string := "NO_CHANGE"; -- write_first(default)/read_first/no_change init_a: bit_vector := x"00000"; srval_a: bit_vector := x"00000"; write_mode_b: string := "NO_CHANGE"; -- write_first(default)/read_first/no_change init_b: bit_vector := x"00000"; srval_b: bit_vector := x"00000"; INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0a : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0b : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0c : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0d : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0e : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0f : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1a : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1b : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1c : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1d : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1e : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1f : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2a : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2b : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2c : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2d : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2e : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2f : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3a : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3b : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3c : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3d : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3e : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3f : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000" ); port( dia: in std_logic_vector(15 downto 0); dipa: in std_logic_vector(1 downto 0); addra: in std_logic_vector(9 downto 0); clka: in std_logic; ssra: in std_logic; ena: in std_logic; wea: in std_logic; doa: out std_logic_vector(15 downto 0); dopa: out std_logic_vector(1 downto 0); dib: in std_logic_vector(15 downto 0); dipb: in std_logic_vector(1 downto 0); addrb: in std_logic_vector(9 downto 0); clkb: in std_logic; ssrb: in std_logic; enb: in std_logic; web: in std_logic; dob: out std_logic_vector(15 downto 0); dopb: out std_logic_vector(1 downto 0)); end component; ---------------------------------------------------------------------------------------- component RAMB16_S18_S36 generic( SIM_COLLISION_CHECK : string := "NONE"; write_mode_a: string := "NO_CHANGE"; -- write_first(default)/read_first/no_change init_a: bit_vector := x"00000"; srval_a: bit_vector := x"00000"; write_mode_b: string := "NO_CHANGE"; -- write_first(default)/read_first/no_change init_b: bit_vector := x"000000000"; srval_b: bit_vector := x"000000000"); port( dia: in std_logic_vector(15 downto 0); dipa: in std_logic_vector(1 downto 0); addra: in std_logic_vector(9 downto 0); clka: in std_logic; ssra: in std_logic; ena: in std_logic; wea: in std_logic; doa: out std_logic_vector(15 downto 0); dopa: out std_logic_vector(1 downto 0); dib: in std_logic_vector(31 downto 0); dipb: in std_logic_vector(3 downto 0); addrb: in std_logic_vector(8 downto 0); clkb: in std_logic; ssrb: in std_logic; enb: in std_logic; web: in std_logic; dob: out std_logic_vector(31 downto 0); dopb: out std_logic_vector(3 downto 0)); end component; ---------------------------------------------------------------------------------------- component RAMB16_S36_S36 generic( SIM_COLLISION_CHECK : string := "NONE"; write_mode_a: string := "NO_CHANGE"; -- write_first(default)/read_first/no_change init_a: bit_vector(35 downto 0) := x"000000000"; srval_a: bit_vector(35 downto 0) := x"000000000"; write_mode_b: string := "NO_CHANGE"; -- write_first(default)/read_first/no_change init_b: bit_vector(35 downto 0) := x"000000000"; srval_b: bit_vector(35 downto 0) := x"000000000"; INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0a : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0b : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0c : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0d : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0e : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0f : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1a : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1b : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1c : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1d : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1e : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_1f : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2a : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2b : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2c : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2d : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2e : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_2f : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3a : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3b : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3c : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3d : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3e : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_3f : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000" ); port( dia: in std_logic_vector(31 downto 0); dipa: in std_logic_vector(3 downto 0); addra: in std_logic_vector(8 downto 0); clka: in std_logic; ssra: in std_logic; ena: in std_logic; wea: in std_logic; doa: out std_logic_vector(31 downto 0); dopa: out std_logic_vector(3 downto 0); dib: in std_logic_vector(31 downto 0); dipb: in std_logic_vector(3 downto 0); addrb: in std_logic_vector(8 downto 0); clkb: in std_logic; ssrb: in std_logic; enb: in std_logic; web: in std_logic; dob: out std_logic_vector(31 downto 0); dopb: out std_logic_vector(3 downto 0)); end component; ---------------------------------------------------------------------------------------- ----- Component RAMB4_S16 ----- component RAMB4_S16 generic ( INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"); port (DI : in STD_LOGIC_VECTOR (15 downto 0); EN : in STD_logic; WE : in STD_logic; RST : in STD_logic; CLK : in STD_logic; ADDR : in STD_LOGIC_VECTOR (7 downto 0); DO : out STD_LOGIC_VECTOR (15 downto 0)); end component; ---------------------------------------------------------------------------------------- -- declare ramb4_s16_s16 component ramb4_s16_s16 generic ( INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"); port (DIA : in STD_LOGIC_VECTOR (15 downto 0); DIB : in STD_LOGIC_VECTOR (15 downto 0); RSTA : in STD_LOGIC; RSTB : in STD_LOGIC; ENA : in STD_LOGIC; ENB : in STD_LOGIC; WEA : in STD_LOGIC; WEB : in STD_LOGIC; CLKA : in STD_LOGIC; CLKB : in STD_LOGIC; ADDRA : in STD_LOGIC_VECTOR (7 downto 0); ADDRB : in STD_LOGIC_VECTOR (7 downto 0); DOA : out STD_LOGIC_VECTOR (15 downto 0); DOB : out STD_LOGIC_VECTOR (15 downto 0) ); end component; -- declare ramb4_s8_s16 component ramb4_s8_s16 generic ( INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"); port (DIA : in STD_LOGIC_VECTOR (7 downto 0); DIB : in STD_LOGIC_VECTOR (15 downto 0); RSTA : in STD_LOGIC; RSTB : in STD_LOGIC; ENA : in STD_LOGIC; ENB : in STD_LOGIC; WEA : in STD_LOGIC; WEB : in STD_LOGIC; CLKA : in STD_LOGIC; CLKB : in STD_LOGIC; ADDRA : in STD_LOGIC_VECTOR (8 downto 0); ADDRB : in STD_LOGIC_VECTOR (7 downto 0); DOA : out STD_LOGIC_VECTOR (7 downto 0); DOB : out STD_LOGIC_VECTOR (15 downto 0) ); end component; -- declare ramb4_s1_s16 component ramb4_s1_s16 generic ( INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"); port (DIA : in STD_LOGIC_VECTOR (0 downto 0); DIB : in STD_LOGIC_VECTOR (15 downto 0); ENA : in STD_logic; ENB : in STD_logic; WEA : in STD_logic; WEB : in STD_logic; RSTA : in STD_logic; RSTB : in STD_logic; CLKA : in STD_logic; CLKB : in STD_logic; ADDRA : in STD_LOGIC_VECTOR (11 downto 0); ADDRB : in STD_LOGIC_VECTOR (7 downto 0); DOA : out STD_LOGIC_VECTOR (0 downto 0); DOB : out STD_LOGIC_VECTOR (15 downto 0)); end component; ----- Component RAMB4_S1_S8 ----- component RAMB4_S1_S8 -- generic ( INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"); -- port (DIA : in STD_LOGIC_VECTOR (0 downto 0); DIB : in STD_LOGIC_VECTOR (7 downto 0); ENA : in STD_logic; ENB : in STD_logic; WEA : in STD_logic; WEB : in STD_logic; RSTA : in STD_logic; RSTB : in STD_logic; CLKA : in STD_logic; CLKB : in STD_logic; ADDRA : in STD_LOGIC_VECTOR (11 downto 0); ADDRB : in STD_LOGIC_VECTOR (8 downto 0); DOA : out STD_LOGIC_VECTOR (0 downto 0); DOB : out STD_LOGIC_VECTOR (7 downto 0)); end component; -- declare ramb4_s8_s8 component ramb4_s8_s8 generic ( INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"); port (DIA : in STD_LOGIC_VECTOR (7 downto 0); DIB : in STD_LOGIC_VECTOR (7 downto 0); RSTA : in STD_LOGIC; RSTB : in STD_LOGIC; ENA : in STD_LOGIC; ENB : in STD_LOGIC; WEA : in STD_LOGIC; WEB : in STD_LOGIC; CLKA : in STD_LOGIC; CLKB : in STD_LOGIC; ADDRA : in STD_LOGIC_VECTOR (8 downto 0); ADDRB : in STD_LOGIC_VECTOR (8 downto 0); DOA : out STD_LOGIC_VECTOR (7 downto 0); DOB : out STD_LOGIC_VECTOR (7 downto 0) ); end component; -- declare ramb4_s4_s8 component ramb4_s4_s8 generic ( INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"); port (DIA : in STD_LOGIC_VECTOR (3 downto 0); DIB : in STD_LOGIC_VECTOR (7 downto 0); RSTA : in STD_LOGIC; RSTB : in STD_LOGIC; ENA : in STD_LOGIC; ENB : in STD_LOGIC; WEA : in STD_LOGIC; WEB : in STD_LOGIC; CLKA : in STD_LOGIC; CLKB : in STD_LOGIC; ADDRA : in STD_LOGIC_VECTOR (9 downto 0); ADDRB : in STD_LOGIC_VECTOR (8 downto 0); DOA : out STD_LOGIC_VECTOR (3 downto 0); DOB : out STD_LOGIC_VECTOR (7 downto 0) ); end component; -- declare ramb4_s4_s4 component ramb4_s4_s4 generic ( INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"); port (DIA : in STD_LOGIC_VECTOR (3 downto 0); DIB : in STD_LOGIC_VECTOR (3 downto 0); RSTA : in STD_LOGIC; RSTB : in STD_LOGIC; ENA : in STD_LOGIC; ENB : in STD_LOGIC; WEA : in STD_LOGIC; WEB : in STD_LOGIC; CLKA : in STD_LOGIC; CLKB : in STD_LOGIC; ADDRA : in STD_LOGIC_VECTOR (9 downto 0); ADDRB : in STD_LOGIC_VECTOR (9 downto 0); DOA : out STD_LOGIC_VECTOR (3 downto 0); DOB : out STD_LOGIC_VECTOR (3 downto 0) ); end component; -- declare ramb4_s2_s4 component ramb4_s2_s4 generic ( INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"); port (DIA : in STD_LOGIC_VECTOR (1 downto 0); DIB : in STD_LOGIC_VECTOR (3 downto 0); RSTA : in STD_LOGIC; RSTB : in STD_LOGIC; ENA : in STD_LOGIC; ENB : in STD_LOGIC; WEA : in STD_LOGIC; WEB : in STD_LOGIC; CLKA : in STD_LOGIC; CLKB : in STD_LOGIC; ADDRA : in STD_LOGIC_VECTOR (10 downto 0); ADDRB : in STD_LOGIC_VECTOR (9 downto 0); DOA : out STD_LOGIC_VECTOR (1 downto 0); DOB : out STD_LOGIC_VECTOR (3 downto 0) ); end component; -- declare ramb4_s2_s2 component ramb4_s2_s2 generic ( INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"); port (DIA : in STD_LOGIC_VECTOR (1 downto 0); DIB : in STD_LOGIC_VECTOR (1 downto 0); RSTA : in STD_LOGIC; RSTB : in STD_LOGIC; ENA : in STD_LOGIC; ENB : in STD_LOGIC; WEA : in STD_LOGIC; WEB : in STD_LOGIC; CLKA : in STD_LOGIC; CLKB : in STD_LOGIC; ADDRA : in STD_LOGIC_VECTOR (10 downto 0); ADDRB : in STD_LOGIC_VECTOR (10 downto 0); DOA : out STD_LOGIC_VECTOR (1 downto 0); DOB : out STD_LOGIC_VECTOR (1 downto 0) ); end component; -- declare ramb4_s1_s1 component ramb4_s1_s1 generic ( INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"); port (DIA : in STD_LOGIC; DIB : in STD_LOGIC; RSTA : in STD_LOGIC; RSTB : in STD_LOGIC; ENA : in STD_LOGIC; ENB : in STD_LOGIC; WEA : in STD_LOGIC; WEB : in STD_LOGIC; CLKA : in STD_LOGIC; CLKB : in STD_LOGIC; ADDRA : in STD_LOGIC_VECTOR (11 downto 0); ADDRB : in STD_LOGIC_VECTOR (11 downto 0); DOA : out STD_LOGIC; DOB : out STD_LOGIC ); end component; ---------------------------------------------------------------------------------------- component srl16e generic(INIT : bit_vector := x"0000"); port ( d: in std_logic; ce: in std_logic; clk: in std_logic; a0: in std_logic; a1: in std_logic; a2: in std_logic; a3: in std_logic; q: out std_logic); end component; ------------------------------------------------------------------------------------- component DCM generic ( CLK_FEEDBACK : string := "1X"; CLKDV_DIVIDE : real := 2.0; CLKFX_DIVIDE : integer := 1; CLKFX_MULTIPLY : integer := 4; CLKIN_DIVIDE_BY_2 : boolean := FALSE; CLKIN_PERIOD : real := 0.0; CLKOUT_PHASE_SHIFT : string := "NONE"; DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS"; DFS_FREQUENCY_MODE : string := "LOW"; DLL_FREQUENCY_MODE : string := "LOW"; DSS_MODE : string := "NONE"; DUTY_CYCLE_CORRECTION : boolean := TRUE; PHASE_SHIFT : integer := 0; STARTUP_WAIT : boolean := FALSE); port ( CLKIN : in std_logic ; CLKFB : in std_logic ; RST : in std_logic ; DSSEN : in std_logic ; PSINCDEC: in std_logic ; PSEN : in std_logic ; PSCLK : in std_logic ; CLK0 : out std_logic ; CLK90 : out std_logic ; CLK180 : out std_logic ; CLK270 : out std_logic ; CLK2X : out std_logic ; CLK2X180: out std_logic ; CLKDV : out std_logic ; CLKFX : out std_logic ; CLKFX180: out std_logic ; LOCKED : out std_logic ; STATUS : out std_logic_vector(7 downto 0); PSDONE : out std_logic ); end component; ------------------------------------------------------------------------------------- component CLKDLL port ( CLKIN : in std_logic ; CLKFB : in std_logic ; RST : in std_logic ; CLK0 : out std_logic ; CLK90 : out std_logic ; CLK180 : out std_logic ; CLK270 : out std_logic ; CLK2X : out std_logic ; CLKDV : out std_logic ; LOCKED : out std_logic ); end component; ------------------------------------------------------------------------------------- component FDDRRSE port ( d0 : in std_logic; d1 : in std_logic; c0 : in std_logic; c1 : in std_logic; ce : in std_logic; r : in std_logic; s : in std_logic; q : out std_logic); end component; --------------------------------------------------------------------------------- -- COMPMCN: --------- component compMCN generic (N : integer); port ( a: in STD_LOGIC_VECTOR (N-1 downto 0); b: in STD_LOGIC_VECTOR (N-1 downto 0); ge: out STD_LOGIC ); end component; ------------------------------------------------------------------------------------- -- window comparator. default less than upper limit and greater eqaul than lower limit component compWN generic (N : integer := 12; ul_include : std_logic := '0'; ll_include : std_logic := '1'); port ( d: in STD_LOGIC_VECTOR (N-1 downto 0); u_limit: in STD_LOGIC_VECTOR (N-1 downto 0); l_limit: in STD_LOGIC_VECTOR (N-1 downto 0); n_good: out STD_LOGIC ); end component; -------------------------------------------------------------------------------------- component srl_fifo generic (N: integer := 16; full_cnt: integer := 11); port ( rst: in STD_LOGIC; din: in STD_LOGIC_VECTOR (N-1 downto 0); write: in STD_LOGIC; clk: in STD_LOGIC; read: in STD_LOGIC; dout: out STD_LOGIC_VECTOR (N-1 downto 0); wc: out STD_LOGIC_VECTOR (3 downto 0); full: out std_logic; re: out STD_LOGIC ); end component; --------------------------------------------------------------------------------------- component srl_fiforeg is generic (N: integer := 16; full_cnt: integer := 11); port ( rst: in STD_LOGIC; din: in STD_LOGIC_VECTOR (N-1 downto 0); write: in STD_LOGIC; clk: in STD_LOGIC; read: in STD_LOGIC; dout: out STD_LOGIC_VECTOR (N-1 downto 0); wc: out STD_LOGIC_VECTOR (3 downto 0); full: out std_logic; empty: out STD_LOGIC); end component; ----------------------------------------------------------------------- component add_oneN generic ( N: integer := 24); port ( d: in STD_LOGIC_VECTOR (N-1 downto 0); rst: in STD_LOGIC; sum: out STD_LOGIC_VECTOR (N-1 downto 0); carry: out STD_LOGIC); end component; --------------------------------------------------------------------------------- component ROM16X1 generic ( INIT : bit_vector); port ( A0: IN std_logic; A1: IN std_logic; A2: IN std_logic; A3: IN std_logic; O: OUT std_logic); end component; --------------------------------------------------------------------------------- component ram16x1s port( we: in std_logic; wclk: in std_logic; d: in std_logic; a0: in std_logic; a1: in std_logic; a2: in std_logic; a3: in std_logic; o: out std_logic); end component; --------------------------------------------------------------------------------- component ram16x1d port( we: in std_logic; wclk: in std_logic; d: in std_logic; a0: in std_logic; a1: in std_logic; a2: in std_logic; a3: in std_logic; dpra0: in std_logic; dpra1: in std_logic; dpra2: in std_logic; dpra3: in std_logic; spo: out std_logic; dpo: out std_logic); end component; --------------------------------------------------------------------------------- component ram32x1s port( we: in std_logic; wclk: in std_logic; d: in std_logic; a0: in std_logic; a1: in std_logic; a2: in std_logic; a3: in std_logic; a4: in std_logic; o: out std_logic); end component; ------------------------------------- component rom32x1 generic(INIT : bit_vector := x"12"); port( a0: in std_logic; a1: in std_logic; a2: in std_logic; a3: in std_logic; a4: in std_logic; o: out std_logic); end component; --------------------------------------------------------------------------------- component ram32x1d port( we: in std_logic; wclk: in std_logic; d: in std_logic; a0: in std_logic; a1: in std_logic; a2: in std_logic; a3: in std_logic; a4: in std_logic; dpra0: in std_logic; dpra1: in std_logic; dpra2: in std_logic; dpra3: in std_logic; dpra4: in std_logic; spo: out std_logic; dpo: out std_logic); end component; --------------------------------------------------------------------------------- component delayt_N generic ( T: positive := 2; -- Minimum value! N: positive := 16); port ( clk: in STD_LOGIC; d: in STD_LOGIC_vector(N-1 downto 0); ce: in STD_LOGIC; q: out STD_LOGIC_vector(N-1 downto 0) ); end component; --------------------------------------------------------------------------------- component muxf5_N generic ( N: positive := 16); port ( I0: in STD_LOGIC_vector(N-1 downto 0); I1: in STD_LOGIC_vector(N-1 downto 0); S: in STD_LOGIC; O: out STD_LOGIC_vector(N-1 downto 0) ); end component; --------------------------------------------------------------------------------- COMPONENT updown_cntr generic (N: integer := 4); port ( rst: in STD_LOGIC; set: in STD_LOGIC; ce: in STD_LOGIC; up: in STD_LOGIC; down: in STD_LOGIC; clk: in STD_LOGIC; q: out STD_LOGIC_VECTOR (N-1 downto 0); carry: out STD_LOGIC ); END COMPONENT; --------------------------------------------------------------------------------- component buft port ( t: in STD_LOGIC; i: in STD_LOGIC; o: out STD_LOGIC ); end component; --------------------------------------------------------------------------------- component bufe port ( e: in STD_LOGIC; i: in STD_LOGIC; o: out STD_LOGIC ); end component; --------------------------------------------------------------------------------- component tbuf generic (N: integer := 8); port ( t: in STD_LOGIC; i: in STD_LOGIC_VECTOR (N-1 downto 0); o: out STD_LOGIC_VECTOR (N-1 downto 0) ); end component; --------------------------------------------------------------------------------- component tbufy8v2 port ( t: in STD_LOGIC; i: in STD_LOGIC_VECTOR (7 downto 0); o: out STD_LOGIC_VECTOR (7 downto 0) ); end component; --------------------------------------------------------------------------------- component tbufy8 port ( t: in STD_LOGIC; i: in STD_LOGIC_VECTOR (7 downto 0); o: out STD_LOGIC_VECTOR (7 downto 0) ); end component; --------------------------------------------------------------------------------- component tbufy16 port ( t: in STD_LOGIC; i: in STD_LOGIC_VECTOR (15 downto 0); o: out STD_LOGIC_VECTOR (15 downto 0) ); end component; --------------------------------------------------------------------------------- component tbufy16v2 port ( t: in STD_LOGIC; i: in STD_LOGIC_VECTOR (15 downto 0); o: out STD_LOGIC_VECTOR (15 downto 0) ); end component; --------------------------------------------------------------------------------- component tbufy11v2 port ( t: in STD_LOGIC; i: in STD_LOGIC_VECTOR (10 downto 0); o: out STD_LOGIC_VECTOR (10 downto 0) ); end component; --------------------------------------------------------------------------------- component ebufy32v2 port ( e: in STD_LOGIC; i: in STD_LOGIC_VECTOR (31 downto 0); o: out STD_LOGIC_VECTOR (31 downto 0) ); end component; --------------------------------------------------------------------------------- component tbufy17 port ( t: in STD_LOGIC; i: in STD_LOGIC_VECTOR (16 downto 0); o: out STD_LOGIC_VECTOR (16 downto 0) ); end component; --------------------------------------------------------------------------------- component tbufy26 port ( t: in STD_LOGIC; i: in STD_LOGIC_VECTOR (25 downto 0); o: out STD_LOGIC_VECTOR (25 downto 0) ); end component; --------------------------------------------------------------------------------- component tbufy32 port ( t: in STD_LOGIC; i: in STD_LOGIC_VECTOR (31 downto 0); o: out STD_LOGIC_VECTOR (31 downto 0) ); end component; --------------------------------------------------------------------------------- component tbufy33 port ( t: in STD_LOGIC; i: in STD_LOGIC_VECTOR (32 downto 0); o: out STD_LOGIC_VECTOR (32 downto 0) ); end component; --------------------------------------------------------------------------------- component gray4 port( clk: in std_logic; ec: in std_logic; clr: in std_logic; q: out std_logic_vector(3 downto 0)); end component; --------------------------------------------------------------------------------- component gray4_1 port( clk: in std_logic; ec: in std_logic; clr: in std_logic; q: out std_logic_vector(3 downto 0)); end component; ----- Component MULT18X18 ----- component MULT18X18 port (A : in STD_LOGIC_VECTOR (17 downto 0); B : in STD_LOGIC_VECTOR (17 downto 0); P : out STD_LOGIC_VECTOR (35 downto 0) ); end component; --------------------------------------------------------------------------------- component ddr_io port ( clk: in STD_LOGIC; clkn: in STD_LOGIC; pad: inout std_logic; t: in STD_LOGIC; d0: in STD_LOGIC; d1: in STD_LOGIC; iclk: in STD_LOGIC; iclkn: in STD_LOGIC; q0: out std_logic; -- rising edge q1: out std_logic -- falling edge ); end component; --------------------------------------------------------------------------------- component ddr_in port ( clk: in STD_LOGIC; pad: in std_logic; q0: out std_logic; -- rising edge q1: out std_logic -- falling edge ); end component; ---------------------------------------------------------------------- component multNx2 generic(N : positive := 8; roundup : boolean := false); Port ( a : in std_logic_vector(N-1 downto 0); b : in std_logic_vector(1 downto 0); o : out std_logic_vector(N+1 downto 0)); end component; ---------------------------------------------------------------------- component compCN -- N must be even generic (N : integer := 36); port ( a: in STD_LOGIC_VECTOR (N-1 downto 0); b: in STD_LOGIC_VECTOR (N-1 downto 0); en: in STD_LOGIC; equal: out STD_LOGIC ); end component; ---------------------------------------------------------------------- ---------------------------------------------------------------------- ---------------------------------------------------------------------- ---------------------------------------------------------------------- end vtx_pack; package body vtx_pack is function conv_v2u(arg: std_logic_vector) return unsigned is variable u: unsigned(arg'length -1 downto 0); begin for i in 0 to arg'length-1 loop u(i) := arg(i + arg'right); end loop; return u; end conv_v2u; function conv_u2v(arg: unsigned) return std_logic_vector is variable v: std_logic_vector(arg'length -1 downto 0); begin for i in 0 to arg'length-1 loop v(i) := arg(i + arg'right); end loop; return v; end conv_u2v; end vtx_pack;