-- this file contains:
-- i_reg, o_reg, io_reg, srle_n, delayN, l_ud_cntr
-- input without register
library IEEE,mylib;
use IEEE.std_logic_1164.all;
use mylib.vtx_pack.all;
library UNISIM;
use UNISIM.VComponents.all;

entity ipin is
    port (
        i: out STD_LOGIC);
end ipin;

architecture ipin_arch of ipin is
signal input: std_logic;
begin
ipd: ipad
   port map( pad => input);
ibf: ibuf
   port map( i => input,
             o => i);
end ipin_arch;
-- output without register
library IEEE,mylib;
use IEEE.std_logic_1164.all;
use mylib.vtx_pack.all;
library UNISIM;
use UNISIM.VComponents.all;

entity opin is
    port (
        t: in STD_LOGIC;
        o: in STD_LOGIC);
end opin;

architecture opin_arch of opin is
signal output: std_logic;
begin
opd: opad
   port map( pad => output);
obf: obuft
   port map( i => o,
             t => t,
             o => output);
end opin_arch;
-- inout without register
library IEEE,mylib;
use IEEE.std_logic_1164.all;
use mylib.vtx_pack.all;
library UNISIM;
use UNISIM.VComponents.all;

entity iopin is
    port (
        i: out std_logic;
        t: in STD_LOGIC;
        o: in STD_LOGIC);
end iopin;

architecture iopin_arch of iopin is
signal bidir: std_logic;
begin
iopd: iopad
   port map( iopad => bidir);
ibf: ibuf
   port map( i => bidir,
             o => i);
obf: obuft
   port map( i => o,
             t => t,
             o => bidir);
end iopin_arch;
-- input with register
library IEEE,mylib;
use IEEE.std_logic_1164.all;
use mylib.vtx_pack.all;
library UNISIM;
use UNISIM.VComponents.all;

entity i_reg is
    port (
        iq: out STD_LOGIC;
        ice: in STD_LOGIC;
        c: in STD_LOGIC);
end i_reg;

architecture i_reg_arch of i_reg is
signal input,ib: std_logic;
attribute IOB: string;
attribute IOB of ifd: label is "TRUE";
begin
ifd: FDE
   port map(
            d  => ib,
            ce => ice,
            c  => c,
            q  => iq);
ipd: ipad
   port map( pad => input);
ibf: ibuf
   port map( i => input,
             o => ib);
end i_reg_arch;
---------------------------------------------------------------------------------------
-- output with registers
library IEEE,mylib;
use IEEE.std_logic_1164.all;
use mylib.vtx_pack.all;
library UNISIM;
use UNISIM.VComponents.all;

entity o_reg is
    port (
        oq: in STD_LOGIC;
        tq: in STD_LOGIC;
        oce: in STD_LOGIC;
        tce: in STD_LOGIC;
        c: in STD_LOGIC
    );
end o_reg;

architecture o_reg_arch of o_reg is
signal o,off,tff: std_logic;
attribute IOB: string;
attribute IOB of ofd,tfd: label is "TRUE";
begin
ofd: FDE
   port map(
            d  => oq,
            ce => oce,
            c  => c,
            q  => off);
tfd: FDE
   port map(
            d  => tq,
            ce => tce,
            c  => c,
            q  => tff);
ob: obuft
   port map(
            i => off,
            t => tff,
            o => o);
op: opad
   port map ( pad => o );
end o_reg_arch;
---------------------------------------------------------------------------------------
-- input/output with registers 
library IEEE,mylib;
use IEEE.std_logic_1164.all;
use mylib.vtx_pack.all;
library UNISIM;
use UNISIM.VComponents.all;

entity io_reg is
    port (
        bdir: inout STD_LOGIC;
        iq: out STD_LOGIC;
        oq: in STD_LOGIC;
        tq: in STD_LOGIC;
        ice: in STD_LOGIC;
        oce: in STD_LOGIC;
        tce: in STD_LOGIC;
        c: in STD_LOGIC
    );
end io_reg;

architecture io_reg_arch of io_reg is

signal off,tff: std_logic;
signal ib: std_logic;
attribute IOB: string;
attribute IOB of ifd,ofd,tfd: label is "TRUE";
begin
buf: ibuf
  port map( i => bdir,
            o => ib);
buft: obuft
  port map( i => off,
            t => tff,
            o => bdir);
ifd: FDE
   port map(
            d  => ib,
            ce => ice,
            c  => c,
            q  => iq);
ofd: FDE
   port map(
            d  => oq,
            ce => oce,
            c  => c,
            q  => off);
tfd: FDE
   port map(
            d  => tq,
            ce => tce,
            c  => c,
            q  => tff);
end io_reg_arch;
-------------------------------------------------------------------------------------
-- this is a N bit wide LUT shift registers

library IEEE,mylib;
use IEEE.std_logic_1164.all;
use mylib.vtx_pack.all;
library UNISIM;
use UNISIM.VComponents.all;

entity srle_N is 
generic (N: positive := 16);
    port (
        d: in STD_LOGIC_VECTOR (N-1 downto 0);
        a: in STD_LOGIC_VECTOR (3 downto 0);
        ce: in STD_LOGIC;
        clk: in STD_LOGIC;
        q: out STD_LOGIC_VECTOR (N-1 downto 0)
    );
end srle_N;

architecture srle_N_arch of srle_N is
begin
g1: for i in d'range generate
  srle: srl16e port map(
                             d => d(i),
                             ce => ce,
                             clk => clk,
                             a0 => a(0),
                             a1 => a(1),
                             a2 => a(2),
                             a3 => a(3),
                             q  => q(i));
end generate;
end srle_N_arch;
-----------------------------------------------------------------------------------
-- delay d from 2 to 17 clocks with ce = '1'
library IEEE,mylib;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use mylib.vtx_pack.all;
library UNISIM;
use UNISIM.VComponents.all;

entity delayN is
    generic (N: positive := 2;
	          INIT : bit_vector := x"0000");
    port (
        c: in STD_LOGIC;
        d: in STD_LOGIC;
        ce: in STD_LOGIC;
        q: out STD_LOGIC
    );
end delayN;
architecture delayN_arch of delayN is
signal a: std_logic_vector(4 downto 0);
signal dl: std_logic;
begin
a <= conv_std_logic_vector(N-2,5);
delay: srl16e
    generic map(INIT => INIT)
    port map(
           d => d,
           ce => ce,
           clk => c,
           a0 => a(0),
           a1 => a(1),
           a2 => a(2),
           a3 => a(3),
           q => dl);
process(c)
begin
  if(c'event and c = '1')then
    if(ce = '1')then
      q <= dl;
    end if;
  end if;
end process;
end delayN_arch;
---------------------------------------------------------------------------------------------------
-- LUT SINGLE RAM:
---------------------------------------------------------------------------------------------------
library IEEE,mylib;
use IEEE.std_logic_1164.all;
use mylib.vtx_pack.all;
library UNISIM;
use UNISIM.VComponents.all;
entity ram16XNs is
    generic ( N: positive := 16);
    port (
        clk: in STD_LOGIC;
        we: in STD_LOGIC;
        d: in STD_LOGIC_VECTOR (N-1 downto 0);
        a: in STD_LOGIC_VECTOR (3 downto 0);
        o: out STD_LOGIC_VECTOR (N-1 downto 0)
    );
end ram16XNs;

architecture ram16XNs_arch of ram16XNs is
begin
g0: for i in d'range generate
ram: ram16x1s
    port map(
             we => we,
             wclk => clk,
             d => d(i),
             a0 => a(0),
             a1 => a(1),
             a2 => a(2),
             a3 => a(3),
             o => o(i));
end generate;
end ram16XNs_arch; 
-------------------------------------------------------------------------------------
library IEEE,mylib;
use IEEE.std_logic_1164.all;
use mylib.vtx_pack.all;
library UNISIM;
use UNISIM.VComponents.all;
entity ram16XNd is
    generic ( N: positive := 16);
    port (
        clk: in STD_LOGIC;
        we: in STD_LOGIC;
        d: in STD_LOGIC_VECTOR (N-1 downto 0);
        a: in STD_LOGIC_VECTOR (3 downto 0);
        dpra: in STD_LOGIC_VECTOR (3 downto 0);
        spo: out STD_LOGIC_VECTOR (N-1 downto 0);
        dpo: out STD_LOGIC_VECTOR (N-1 downto 0)
    );
end ram16XNd;
architecture my_arch of ram16XNd is
begin
g0: for i in d'range generate
ram: ram16x1d
    port map(
             we => we,
             wclk => clk,
             d => d(i),
             a0 => a(0),
             a1 => a(1),
             a2 => a(2),
             a3 => a(3),
             dpra0 => dpra(0),
             dpra1 => dpra(1),
             dpra2 => dpra(2),
             dpra3 => dpra(3),
             spo => spo(i),
             dpo => dpo(i));
end generate;
end my_arch;
-------------------------------------------------------------------------------------
library IEEE,mylib;
use IEEE.std_logic_1164.all;
use mylib.vtx_pack.all;
library UNISIM;
use UNISIM.VComponents.all;
entity ram32XNd is
    generic ( N: positive := 16);
    port (
        clk: in STD_LOGIC;
        we: in STD_LOGIC;
        d: in STD_LOGIC_VECTOR (N-1 downto 0);
        a: in STD_LOGIC_VECTOR (4 downto 0);
        dpra: in STD_LOGIC_VECTOR (4 downto 0);
        spo: out STD_LOGIC_VECTOR (N-1 downto 0);
        dpo: out STD_LOGIC_VECTOR (N-1 downto 0)
    );
end ram32XNd;
architecture my_arch of ram32XNd is
begin
g0: for i in d'range generate
ram: ram32x1d
    port map(
             we => we,
             wclk => clk,
             d => d(i),
             a0 => a(0),
             a1 => a(1),
             a2 => a(2),
             a3 => a(3),
             a4 => a(4),
             dpra0 => dpra(0),
             dpra1 => dpra(1),
             dpra2 => dpra(2),
             dpra3 => dpra(3),
             dpra4 => dpra(4),
             spo => spo(i),
             dpo => dpo(i));
end generate;
end my_arch;
-------------------------------------------------------------------------------------
library IEEE,mylib;
use IEEE.std_logic_1164.all;
use mylib.vtx_pack.all;
library UNISIM;
use UNISIM.VComponents.all;
entity ram32XNs is
    generic ( N: positive := 16);
    port (
        clk: in STD_LOGIC;
        we: in STD_LOGIC;
        d: in STD_LOGIC_VECTOR (N-1 downto 0);
        a: in STD_LOGIC_VECTOR (4 downto 0);
        o: out STD_LOGIC_VECTOR (N-1 downto 0)
    );
end ram32XNs;
architecture my_arch of ram32XNs is
begin
g0: for i in d'range generate
ram: ram32x1s
    port map(
             we => we,
             wclk => clk,
             d => d(i),
             a0 => a(0),
             a1 => a(1),
             a2 => a(2),
             a3 => a(3),
             a4 => a(4),
             o => o(i));
end generate;
end my_arch;
-------------------------------------------------------------------------------------
-- this is a loadable, up/down counter with set, reset and clock enable inputs 
library IEEE,mylib;
use IEEE.std_logic_1164.all;
use mylib.vtx_pack.all;
library UNISIM;
use UNISIM.VComponents.all;
entity l_ud_cntr is
generic (N: positive := 8);
  port (
    d: in std_logic_vector (N-1 downto 0);
-- load_n = '0' and ec = '1' loads d into q
    load_n: in std_logic;
-- up = '1' counts up
    up: in std_logic;
-- reset resets the counter to all zeros, reset overrides set and ec
    reset: in std_logic;
-- set will set the counter to all ones
    set: in std_logic;
-- ec = '1' is needed to load or count 
    ec: in std_logic;
-- en_cnt = '1' is needed to count 
    en_cnt: in std_logic;
-- clock input
    clk: in std_logic;
-- q is the counter output
    q: out std_logic_vector (N-1 downto 0);
-- carry out
    carry: out std_logic
  );
end l_ud_cntr;

architecture my_arch of l_ud_cntr is
signal	qi,di,s,dq:	std_logic_vector(N-1 downto 0);
signal	ci:	std_logic_vector(N downto 0);
begin
q <= qi;
carry <= ci(N);
ci(0) <= (up xnor en_cnt) and load_n;
G1: for I in q'range generate
  s(I) <= (not up and load_n) xor (d(I) and not load_n) xor (qi(I) and load_n);
  mxcy: muxcy    port map (S => s(I), DI => di(I), CI => ci(I), O => ci(I+1));
  multand: mult_and port map ( I0 => qi(I), I1 => load_n, LO => di(I));
  xocy: xorcy       port map ( LI => s(I), CI => ci(I), O => dq(I));
  ff: fdrse    port map ( C => clk, D => dq(I), CE => ec, S => set, R => reset, Q => qi(I));
end generate G1;
end my_arch;
-------------------------------------------------------------------------------------
-- this is a loadable up counter with set, reset and clock enable inputs 
library IEEE,mylib;
use IEEE.std_logic_1164.all;
use mylib.vtx_pack.all;
library UNISIM;
use UNISIM.VComponents.all;
entity l_cntr is
generic (N: positive := 8; ld_plus_one : boolean := false );
  port (
    d: in std_logic_vector (N-1 downto 0);
-- load = '1' and ec = '1' loads d into q
    load: in std_logic;
-- reset resets the counter to all zeros, reset overrides set and ec
    reset: in std_logic;
-- set will set the counter to all ones
    set: in std_logic;
-- ec = '1' is needed to load or count 
    ec: in std_logic;
-- en_cnt = '1' is needed to count. If load with en_cnt = '1',
-- d + 1 is loaded. 
    en_cnt: in std_logic;
-- clock input
    clk: in std_logic;
-- q is the counter output
    q: out std_logic_vector (N-1 downto 0);
-- carry out
    carry: out std_logic
  );
end l_cntr;

architecture my_arch of l_cntr is
signal	qi,s,dq:	std_logic_vector(N-1 downto 0) := (others => '0');
signal	ci:	std_logic_vector(N downto 0) := (others => '0');
begin
q <= qi;
carry <= ci(N);
ci(0) <= en_cnt or load when ld_plus_one else en_cnt and not load;
G1: for I in q'range generate
  s(I) <= (d(I) and load) or (qi(I) and not load);
  mxcy: muxcy    port map (S => s(I), DI => '0', CI => ci(I), O => ci(I+1));
  xocy: xorcy       port map ( LI => s(I), CI => ci(I), O => dq(I));
  ff: fdrse    port map ( C => clk, D => dq(I), CE => ec, S => set, R => reset, Q => qi(I));
end generate G1;
end my_arch;
-------------------------------------------------------------------------------------
-- this is a loadable down counter with set, reset and clock enable inputs 
library IEEE,mylib;
use IEEE.std_logic_1164.all;
use mylib.vtx_pack.all;
library UNISIM;
use UNISIM.VComponents.all;
entity l_d_cntr is
generic (N: positive := 8; ld_minus_one : boolean := false );
  port (
    d: in std_logic_vector (N-1 downto 0);
-- load = '1' and ec = '1' loads d into q
    load: in std_logic;
-- reset resets the counter to all zeros, reset overrides set and ec
    reset: in std_logic;
-- set will set the counter to all ones
    set: in std_logic;
-- ec = '1' is needed to load or count 
    ec: in std_logic;
-- en_cnt = '1' is needed to count. If load with en_cnt = '1',
-- d - 1 is loaded. 
    en_cnt: in std_logic;
-- clock input
    clk: in std_logic;
-- q is the counter output
    q: out std_logic_vector (N-1 downto 0);
-- carry out
    carry: out std_logic
  );
end l_d_cntr;

architecture my_arch of l_d_cntr is
signal	qi,s,dq:	std_logic_vector(N-1 downto 0);
signal	ci:	std_logic_vector(N downto 0);
begin
q <= qi;
carry <= ci(N);
ci(0) <= not en_cnt and not load when ld_minus_one else not en_cnt or load;
G1: for I in q'range generate
  s(I) <= (not d(I) and load) or (not qi(I) and not load);
  mxcy: muxcy    port map (S => s(I), DI => '1', CI => ci(I), O => ci(I+1));
  xocy: xorcy       port map ( LI => s(I), CI => ci(I), O => dq(I));
  ff: fdrse    port map ( C => clk, D => dq(I), CE => ec, S => set, R => reset, Q => qi(I));
end generate G1;
end my_arch;
---------------------------------------------------------------------------------------------------
-- ADDER SUBTRACTOR
---------------------------------------------------------------------------------------------------
-- This is an adder-subtractor VHDL module.
-- The module is a parallel loadable, synchronous
-- set/reset, clock enabled adder-subtractor.
-- this code implements a simple and compact 
-- adder-subtractor.
--
-- Input(s): a, b, subtract, load, reset, set, ec, clk
-- Output(s): sum, carry
-- a,b,sum all unsigned
-- truth table
-- reset	set	ec	load	subtract	sum
-- 1		x	x	x	x		others => '0'
-- 0		1	x	x	x		others => '1'
-- 0		0	0	x	x		no change
-- 0		0	1	1	0		b
-- 0		0	1	1	1		-b
-- 0		0	1	0	0		a + b
-- 0		0	1	0	1		a - b
-- subtract	carry	meaning
-- 0		0	no carry out
-- 0		1	carry out
-- 1		0	borrow out
-- 1		1	no borrow out
-- include these three standard IEEE libraries.
-- they include arithmetic operations and conversion functions
-- necessary for mathematical operations.
-- bugs found and corrected Alex and Shouxiang 03/02/01

library IEEE,mylib;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use mylib.vtx_pack.all;
library UNISIM;
use UNISIM.VComponents.all;

entity ldenaddsub is
generic (N: integer := 8);
-- define input and output ports 
  port (
    -- a and b are the input numbers to be added
    a: 			in std_logic_vector (N-1 downto 0);
    b: 			in std_logic_vector (N-1 downto 0);
    -- carrylsb is the value of ci(0).
    -- For the normal funtionality => ci(0) must be assigned to subtract. 
    carry_i: 		in std_logic;
    -- subtract signal determins if a and b are added or subtracted
    subtract: 		in std_logic;
    -- load is active high, when aserted, a is forced to zero 
    load: 		in std_logic;
    -- reset resets the counter register value to all zeros
    reset: 		in std_logic;
    -- set will set the counter to all ones
    set: 		in std_logic;
    -- ec enables the registers' clock enable 
    ec: 		in std_logic;
    -- clk is the clock signal used to drive the counter registers
    clk: 		in std_logic;
    -- sum is the output value 
    sum:		 out std_logic_vector (N-1 downto 0);
    -- sumr is the output value registered 
    sumr: 		out std_logic_vector (N-1 downto 0);
    -- carry out
    carry_o: 		out std_logic
   );
end ldenaddsub;

architecture my_arch of ldenaddsub is
signal di,s,d:	std_logic_vector(N-1 downto 0);
signal ci:	   std_logic_vector(N downto 0);
signal load_n:	std_logic;

begin

load_n <= not(load);
ci(0) <= carry_i;--subtract;
carry_o <= ci(N);
sum <= d;
G1: for I in 0 to N-1 generate
  s(I) <= subtract xor b(I) xor (a(I) and load_n);
  mxcy: muxcy	    port map (S => s(I),
                            DI => di(I),
                            CI => ci(I),
                             O => ci(I+1));
  multand: mult_and port map ( I0 => a(I),
  		               I1 => load_n,
  		               LO => di(I));
  xocy: xorcy       port map ( LI => s(I),
  		               CI => ci(I),
  		                O => d(I));
  ff: fdrse    port map ( C => clk,
  		          D => d(I),
  		         CE => ec,
  		          S => set,
  		          R => reset,
  		          Q => sumr(I));
end generate G1;
end my_arch;
---------------------------------------------------------------------------------------------------
-- ADDER SUBTRACTOR special
---------------------------------------------------------------------------------------------------
-- This is an adder-subtractor VHDL module.
-- The module is a parallel loadable, synchronous
-- set/reset, clock enabled adder-subtractor.
-- this code implements a simple and compact 
-- adder-subtractor.
--
-- Input(s): a, b, subtract, load, reset, set, ec, clk
-- Output(s): sum, carry
-- a,b,sum all unsigned
-- truth table
-- reset	set	ec	load	subtract	sum
-- 1		x	x	x	x		others => '0'
-- 0		1	x	x	x		others => '1'
-- 0		0	0	x	x		no change
-- 0		0	1	1	0		a
-- 0		0	1	1	1		-a
-- 0		0	1	0	0		a + b
-- 0		0	1	0	1		a - b
-- subtract	carry	meaning
-- 0		0	no carry out
-- 0		1	carry out
-- 1		0	borrow out
-- 1		1	no borrow out
-- include these three standard IEEE libraries.
-- they include arithmetic operations and conversion functions
-- necessary for mathematical operations.
-- bugs found and corrected Alex and Shouxiang 03/02/01

library IEEE,mylib;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use mylib.vtx_pack.all;
library UNISIM;
use UNISIM.VComponents.all;

entity ldenaddsubs is
generic (N: integer := 8);
-- define input and output ports 
  port (
    -- a and b are the input numbers to be added
    a: 			in std_logic_vector (N-1 downto 0);
    b: 			in std_logic_vector (N-1 downto 0);
    -- carrylsb is the value of ci(0).
    -- For the normal funtionality => ci(0) must be assigned to subtract. 
    carry_i: 		in std_logic;
    -- subtract signal determins if a and b are added or subtracted
    subtract: 		in std_logic;
    -- load is active high, when aserted, a is forced to zero 
    load: 		in std_logic;
    -- reset resets the counter register value to all zeros
    reset: 		in std_logic;
    -- set will set the counter to all ones
    set: 		in std_logic;
    -- ec enables the registers' clock enable 
    ec: 		in std_logic;
    -- clk is the clock signal used to drive the counter registers
    clk: 		in std_logic;
    -- sum is the output value 
    sum:		 out std_logic_vector (N-1 downto 0);
    -- sumr is the output value registered 
    sumr: 		out std_logic_vector (N-1 downto 0);
    -- carry out
    carry_o: 		out std_logic
   );
end ldenaddsubs;

architecture my_arch of ldenaddsubs is
signal di,s,d:	std_logic_vector(N-1 downto 0);
signal ci:	   std_logic_vector(N downto 0);
signal load_n:	std_logic;

begin

load_n <= not(load);
ci(0) <= carry_i;--subtract;
carry_o <= ci(N);
sum <= d;
G1: for I in 0 to N-1 generate
  s(I) <= subtract xor a(I) xor (b(I) and load_n);
  mxcy: muxcy	    port map (S => s(I),
                            DI => di(I),
                            CI => ci(I),
                             O => ci(I+1));
  multand: mult_and port map ( I0 => a(I),
  		               I1 => load_n,
  		               LO => di(I));
  xocy: xorcy       port map ( LI => s(I),
  		               CI => ci(I),
  		                O => d(I));
  ff: fdrse    port map ( C => clk,
  		          D => d(I),
  		         CE => ec,
  		          S => set,
  		          R => reset,
  		          Q => sumr(I));
end generate G1;
end my_arch;
-------------------------------------------------------------------------------------
-- this is a N-bit adder/subtractor
library IEEE,mylib;
use IEEE.std_logic_1164.all;
use mylib.vtx_pack.all;
library UNISIM;
use UNISIM.VComponents.all;
entity adsuN is
generic (N: positive := 8);
  port (
    a: in std_logic_vector (N-1 downto 0);
    b: in std_logic_vector (N-1 downto 0);
    add: in std_logic;
    ci: in std_logic;
    s: out std_logic_vector (N-1 downto 0);
    co: out std_logic;
    ovfl: out std_logic
  );
end adsuN;

architecture my_arch of adsuN is
signal	i,o:	std_logic_vector(N-1 downto 0);
signal	c:	std_logic_vector(N downto 0);
begin
co <= c(N);
ovfl <= c(N) xor o(N-2);
c(0) <= ci;
G1: for j in a'range generate
  i(j) <= not add xor a(j) xor b(j);
  mxcy: muxcy_d    port map (S => i(j), DI => a(j), CI => c(j), LO => c(j+1), O => o(j));
  xocy: xorcy       port map ( LI => i(j), CI => c(j), O => s(j));
end generate G1;
end my_arch;
-------------------------------------------------------------------------------------
-- this is a N-bit adder/subtractor
library IEEE,mylib;
use IEEE.std_logic_1164.all;
use mylib.vtx_pack.all;
library UNISIM;
use UNISIM.VComponents.all;
entity addN is
generic (N: positive := 8);
  port (
    a: in std_logic_vector (N-1 downto 0);
    b: in std_logic_vector (N-1 downto 0);
    rst_n: in std_logic;
    ci: in std_logic;
    s: out std_logic_vector (N-1 downto 0);
    co: out std_logic;
    ovfl: out std_logic
  );
end addN;

architecture my_arch of addN is
signal	i,o,di:	std_logic_vector(N-1 downto 0);
signal	c:	std_logic_vector(N downto 0);
begin
co <= c(N);
ovfl <= c(N) xor o(N-2);
c(0) <= ci;
G1: for j in a'range generate
  i(j) <= rst_n and (a(j) xor b(j));
  mxcy: muxcy_d    port map (S => i(j), DI => di(j), CI => c(j), LO => c(j+1), O => o(j));
  multand: mult_and       port map ( I0 => b(j), I1 => rst_n, LO => di(j));
  xocy: xorcy       port map ( LI => i(j), CI => c(j), O => s(j));
end generate G1;
end my_arch;
---------------------------------------------------------------------------------------------------
-- this is a n-bit comparator.
-- This is implemeting a carry chain.

library IEEE,mylib;
use IEEE.std_logic_1164.all;
use mylib.vtx_pack.all;
library UNISIM;
use UNISIM.VComponents.all;

entity compCN is
-- N must be even
    generic (N : integer := 36);
    port (
        a: in STD_LOGIC_VECTOR (N-1 downto 0);
        b: in STD_LOGIC_VECTOR (N-1 downto 0);
		  en: in STD_LOGIC;
        equal: out STD_LOGIC
    );
end compCN;

architecture my_arch of compCN is
signal	s:	std_logic_vector((N-1)/2 downto 0);
signal	ci:	std_logic_vector(N/2 downto 0);
begin
ci(0) <= en;
equal <= ci(N/2);
G1: for j in 0 to (N/2)-1 generate
  s(j) <= (a(2*j) xnor b(2*j)) and (a(2*j+1) xnor b(2*j+1));
  mxcy: muxcy    port map (S => s(j), DI => '0', CI => ci(j), O => ci(j+1));
end generate G1;
end my_arch;
---------------------------------------------------------------------------------------------------
-- COMPMCN:
---------------------------------------------------------------------------------------------------
-- this is a n-bit comparator.
-- This is implemeting a carry chain.

library IEEE,mylib;
use IEEE.std_logic_1164.all;
use mylib.vtx_pack.all;
library UNISIM;
use UNISIM.VComponents.all;

entity compMCN is
    generic (N : integer := 8);
    port (
        a: in STD_LOGIC_VECTOR (N-1 downto 0);
        b: in STD_LOGIC_VECTOR (N-1 downto 0);
        ge: out STD_LOGIC
    );
end compMCN;

architecture my_arch of compMCN is
signal	s:	std_logic_vector(N-1 downto 0);
signal	c:	std_logic_vector(N downto 0);
begin
c(0) <= '1';
ge <= c(N);
G1: for j in a'range generate
  s(j) <= not a(j) xor b(j);
  mxcy: muxcy    port map (S => s(j), DI => a(j), CI => c(j), O => c(j+1));
end generate G1;
end my_arch;
-------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- this is a n-bit window comparator for virtex2.
-- This is implemeting a carry chain.

library IEEE,mylib;
use IEEE.std_logic_1164.all;
use mylib.vtx_pack.all;
library UNISIM;
use UNISIM.VComponents.all;

entity compWN is
    generic (N : integer := 12;
	          ul_include : std_logic := '0';
				 ll_include : std_logic := '1');
    port (
        d: in STD_LOGIC_VECTOR (N-1 downto 0);
        u_limit: in STD_LOGIC_VECTOR (N-1 downto 0);
        l_limit: in STD_LOGIC_VECTOR (N-1 downto 0);
        n_good: out STD_LOGIC
    );
end compWN;

architecture my_arch of compWN is
signal	s_u:	std_logic_vector(N-1 downto 0);
signal	c_u:	std_logic_vector(N downto 0);
signal	s_l:	std_logic_vector(N-1 downto 0);
signal	c_l:	std_logic_vector(N downto 0);
signal   u_bad: std_logic;
begin
c_u(0) <= not ul_include;
c_l(0) <= not ll_include;
G1: for j in d'range generate
  s_u(j) <= not d(j) xor u_limit(j);
  mxcy: muxcy    port map (S => s_u(j), DI => d(j), CI => c_u(j), O => c_u(j+1));
end generate G1;
G2: for j in d'range generate
  s_l(j) <= not d(j) xor l_limit(j);
  mxcy: muxcy    port map (S => s_l(j), DI => l_limit(j), CI => c_l(j), O => c_l(j+1));
end generate G2;
i_orcy_u: orcy port map(i => '0', ci => c_u(N), o => u_bad);
i_orcy_l: orcy port map(i => u_bad, ci => c_l(N), o => n_good);
end my_arch;
-------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- this is a N bit fifo constructed from LUT shift registers
-- it can hold up to 2^(cntr_length)-1 words
-- when "write" is high, "din" is written to fifo.
-- when "re" is high, fifo has at least one data word in it.
-- when "read" is high, valid data appears one clock later at dout
-- even if "re" goes low after a "read" signal, dout remains valid.
-- when cntr_lenght is set to 2, full goes one when there words are stored in the fifo
-- when cntr_lenght is set to 3, full goes one when five words are stored in the fifo
-- when cntr_lenght is set to 4, full goes one when nine words are stored in the fifo

library IEEE,mylib;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use mylib.vtx_pack.all;
library UNISIM;
use UNISIM.VComponents.all;

entity srl_fifo is 
generic (N: integer := 16;
         full_cnt: integer := 11);
    port (
        rst: 	in STD_LOGIC;
        din: 	in STD_LOGIC_VECTOR (N-1 downto 0);
        write: in STD_LOGIC;
        clk: 	in STD_LOGIC;
        read: 	in STD_LOGIC;
        dout: 	out STD_LOGIC_VECTOR (N-1 downto 0);
        wc: 	out STD_LOGIC_VECTOR (3 downto 0);
        full:	out std_logic;
        re: out STD_LOGIC
    );
end srl_fifo;

architecture srl_fifo_arch of srl_fifo is
signal dout_i:			std_logic_vector(N-1 downto 0);
signal count:			std_logic_vector(3 downto 0);
signal full_count:	std_logic_vector(4 downto 0);
signal srl_re:			std_logic; 
signal empty_i:		std_logic; 
signal read_srl:		std_logic;
signal di,s,dq:		std_logic_vector(3 downto 0);
signal ci:				std_logic_vector(4 downto 0);
begin
wc <= count;
full_count <= CONV_STD_LOGIC_VECTOR(full_cnt-3,5);
I_srle_N: srle_N
    generic map( N => N)
    port map(
        d => din,
        a => count,
        ce => write,
        clk => clk,
        q => dout_i);
re <= srl_re;
read_srl <= read and srl_re;
ci(0) <= write;
G1: for I in count'range generate
  s(I) <= (read and srl_re) xor count(I);
  mxcy: muxcy    port map (S => s(I), DI => count(I), CI => ci(I), O => ci(I+1));
  xocy: xorcy       port map ( LI => s(I), CI => ci(I), O => dq(I));
end generate G1;
process(clk)
begin
  if(clk'event and clk = '1')then
    if(rst = '1')then
	   count <= (others => '1');
	 else
	   count <= dq;
	 end if;
  end if;
end process; 
process(clk)
begin
  if(clk'event and clk = '1')then
    if(rst = '1')then
	   srl_re <= '0';
    elsif(write = '1')then
	   srl_re <= '1';
	 elsif(read = '1' and count = "0000")then
      srl_re <= '0';
 	 end if;
    if(read_srl = '1')then
      dout <= dout_i;
    end if;
	 if(rst = '1')then
		full <= '0';
	 elsif(count = full_count(3 downto 0))then
      full <= write;
	 end if;
  end if;
end process; 
end srl_fifo_arch;
---------------------------------------------------------------------------------------------------
-- LUT FIFO REGISTERED:
---------------------------------------------------------------------------------------------------
-- this is a N bit fifo constructed from LUT shift registers
-- it can hold up to 2^(cntr_length)-1 words
-- it takes two clocks to drop through the fifo when fifo is empty
-- when "write" is high, "din" is written to fifo.
-- when "empty" is low, dout has valid data.
-- when "read" is high, the next valid data appears one clock later at dout if
-- there are still any in the fifo. Otherwise, the last valid data stays until
-- two clocks after the next write.
-- "read" has no effect when "empty" is high
library IEEE,mylib;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use mylib.vtx_pack.all;
library UNISIM;
use UNISIM.VComponents.all;

entity srl_fiforeg is 
generic (N: integer := 16;
         full_cnt: integer := 11);
    port (
        rst: 	in STD_LOGIC;
        din: 	in STD_LOGIC_VECTOR (N-1 downto 0);
        write: in STD_LOGIC;
        clk: 	in STD_LOGIC;
        read: 	in STD_LOGIC;
        dout: 	out STD_LOGIC_VECTOR (N-1 downto 0);
        wc: 	out STD_LOGIC_VECTOR (3 downto 0);
        full:	out std_logic;
        empty: out STD_LOGIC
    );
end srl_fiforeg;

architecture srl_fiforeg_arch of srl_fiforeg is
signal dout_i:			std_logic_vector(N-1 downto 0);
signal count:			std_logic_vector(3 downto 0);
signal full_count:	std_logic_vector(4 downto 0);
signal srl_re:			std_logic; 
signal empty_i:		std_logic; 
signal read_srl:		std_logic;
signal di,s,dq:		std_logic_vector(3 downto 0);
signal ci:				std_logic_vector(4 downto 0);
begin
wc <= count;
full_count <= CONV_STD_LOGIC_VECTOR(full_cnt-3,5);
I_srle_N: srle_N
    generic map( N => N)
    port map(
        d => din,
        a => count,
        ce => write,
        clk => clk,
        q => dout_i);
empty <= empty_i;
read_srl <= (empty_i or read) and srl_re;
ci(0) <= write;
G1: for I in count'range generate
  s(I) <= ((empty_i or read) and srl_re) xor count(I);
  mxcy: muxcy    port map (S => s(I), DI => count(I), CI => ci(I), O => ci(I+1));
  xocy: xorcy       port map ( LI => s(I), CI => ci(I), O => dq(I));
end generate G1;
process(clk)
begin
  if(clk'event and clk = '1')then
    if(rst = '1')then
	   count <= (others => '1');
	 else
	   count <= dq;
	 end if;
  end if;
end process; 
process(clk)
begin
  if(clk'event and clk = '1')then
    if(rst = '1')then
	   srl_re <= '0';
    elsif(write = '1')then
	   srl_re <= '1';
	 elsif(read_srl = '1' and count = "0000")then
      srl_re <= '0';
 	 end if;
    if(rst= '1')then
	   empty_i <= '1';
	 else
	   empty_i <= not srl_re and (empty_i or read);
	 end if;
    if(read_srl = '1')then
      dout <= dout_i;
    end if;
	 if(rst = '1')then
		full <= '0';
	 elsif(count = full_count(3 downto 0))then
      full <= write;
	 end if;
  end if;
end process; 
end srl_fiforeg_arch;
---------------------------------------------------------------------------------------------------
-- ADD one N:
---------------------------------------------------------------------------------------------------
-- this adder implements a carry chain.

library IEEE,mylib;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use mylib.vtx_pack.all;
library UNISIM;
use UNISIM.VComponents.all;
entity add_oneN is
    generic ( N: integer := 24);
    port (
        d: in STD_LOGIC_VECTOR (N-1 downto 0);
        rst: in STD_LOGIC;
        sum: out STD_LOGIC_VECTOR (N-1 downto 0);
		  carry: out STD_LOGIC
    );
end add_oneN;
architecture add_oneN_arch of add_oneN is
signal	ci:	std_logic_vector(N downto 0);
signal	di,s:	std_logic_vector(N-1 downto 0);

begin
ci(0) <= '1';
carry <= ci(N);
G1: for I in 0 to N-1 generate
  s(I) <= rst or d(I);
  mxcy: muxcy    port map (S => s(I),
                           DI => '0',
                           CI => ci(I),
                           O => ci(I+1));
  xocy: xorcy    port map (LI => s(I),
  		           CI => ci(I),
  		           O => sum(I));
end generate G1;     

end add_oneN_arch;

---------------------------------------------------------------------------------------------------
-- DELAY T for N-bit word
---------------------------------------------------------------------------------------------------
-- delay T from 2 to 17 clocks with ce = '1'
-- N => for N-bit word
  
library IEEE,mylib;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use mylib.vtx_pack.all;
library UNISIM;
use UNISIM.VComponents.all;

entity delayt_N is
  generic ( T: positive := 2; -- Minimum value!
   	    N: positive := 16);
    port (
        clk: in STD_LOGIC;
        d: in STD_LOGIC_vector(N-1 downto 0);
        ce: in STD_LOGIC;
        q: out STD_LOGIC_vector(N-1 downto 0)
         );
end delayt_N;

architecture delayt_N_arch of delayt_N is
signal a: std_logic_vector(4 downto 0);
signal dl: std_logic_vector(N-1 downto 0);
begin
a <= conv_std_logic_vector(T-2,5);
gt: for i in d'range generate
delay: srl16e
    port map(
           d => d(I),
           ce => ce,
           clk => clk,
           a0 => a(0),
           a1 => a(1),
           a2 => a(2),
           a3 => a(3),
           q => dl(I));
end generate;      
    
process(clk)
begin
  if(clk'event and clk = '1')then
    if(ce = '1')then
      q <= dl;
    end if;
  end if;
end process;
end delayt_N_arch;
---------------------------------------------------------------------------------------------------
-- 2-1 mux using mux_f5
---------------------------------------------------------------------------------------------------
-- N => for N-bit word
  
library IEEE,mylib;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use mylib.vtx_pack.all;
library UNISIM;
use UNISIM.VComponents.all;

entity muxf5_N is
  generic ( N: positive := 16);
    port (
        I0: in STD_LOGIC_vector(N-1 downto 0);
        I1: in STD_LOGIC_vector(N-1 downto 0);
        S: in STD_LOGIC;
        O: out STD_LOGIC_vector(N-1 downto 0)
         );
end muxf5_N;

architecture muxf5_N_arch of muxf5_N is
component muxf5
          port ( i0,i1,s: in std_logic;
			        o: out std_logic);
end component;
begin
g_mux: for i in O'range generate
  i_muxf5: muxf5
    port map(
	          i0 => I0(i),
				 i1 => I1(i),
				 s  => S,
				 o  => O(i));
end generate;
end muxf5_N_arch;
------------------------------------
library IEEE,mylib;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use mylib.vtx_pack.all;
library UNISIM;
use UNISIM.VComponents.all;

entity updown_cntr is 
generic (N: integer := 4);
    port (
        rst: in STD_LOGIC;
        set: in STD_LOGIC;
        ce: in STD_LOGIC;
        up: in STD_LOGIC;
        down: in STD_LOGIC;
        clk: in STD_LOGIC;
        q: out STD_LOGIC_VECTOR (N-1 downto 0);
        carry: out STD_LOGIC
    );
end updown_cntr;

architecture updown_cntr_arch of updown_cntr is
signal q_i:				std_logic_vector(N-1 downto 0);
signal di,s,dq:		std_logic_vector(N-1 downto 0);
signal ci:				std_logic_vector(N downto 0);
begin
q <= q_i;
carry <= ci(N);
ci(0) <= up;
G1: for I in q_i'range generate
  s(I) <= down xor q_i(I);
  mxcy: muxcy    port map (S => s(I), DI => q_i(I), CI => ci(I), O => ci(I+1));
  xocy: xorcy       port map ( LI => s(I), CI => ci(I), O => dq(I));
  ff: fdrse    port map ( C => clk, D => dq(I), CE => ce, r => rst, S => set, Q => q_i(I));
end generate G1;
end updown_cntr_arch;
------------------------------------
-- tbuf array
library IEEE,mylib;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use mylib.vtx_pack.all;
library UNISIM;
use UNISIM.VComponents.all;

entity tbuf is 
generic (N: integer := 8);
    port (
        t: in STD_LOGIC;
        i: in STD_LOGIC_VECTOR (N-1 downto 0);
        o: out STD_LOGIC_VECTOR (N-1 downto 0)
    );
end tbuf;

architecture tbuf_arch of tbuf is
begin
G1: for j in i'range generate
  tb: buft port map(t => t, i => i(j), o => o(j));
end generate G1;
end tbuf_arch;
--------------------------------------
library IEEE,mylib;
USE ieee.std_logic_1164.all;
entity gray4 is
  port( clk: in std_logic;
         ec: in std_logic;
        clr: in std_logic;
          q: out std_logic_vector(3 downto 0));
end gray4;
architecture gray4_arch of gray4 is
signal q_i: std_logic_vector(3 downto 0);
begin
q <= q_i;
process(clk,clr)
begin
  if(clr = '1')then
    q_i <= "0000";
  elsif(clk'event and clk = '1')then
    if(ec = '1')then
      q_i(3) <= (q_i(3) and (q_i(1) or q_i(0))) or (q_i(2) and not q_i(1) and not q_i(0));
      q_i(2) <= (q_i(2) and (not q_i(1) or q_i(0))) or (not q_i(3) and q_i(1) and not q_i(0));
      q_i(1) <= (q_i(1) and not q_i(0)) or ((q_i(3) xnor q_i(2)) and q_i(0));
      q_i(0) <= not(q_i(3) xor q_i(2) xor q_i(1));
    end if;
  end if;
end process;
end gray4_arch;
--------------------------------------
library IEEE,mylib;
USE ieee.std_logic_1164.all;
entity gray4_1 is
  port( clk: in std_logic;
         ec: in std_logic;
        clr: in std_logic;
          q: out std_logic_vector(3 downto 0));
end gray4_1;
architecture gray4_1_arch of gray4_1 is
signal q_i: std_logic_vector(3 downto 0);
begin
q <= q_i;
process(clk,clr)
begin
  if(clr = '1')then
    q_i <= "0000";
  elsif(clk'event and clk = '1')then
    if(ec = '1')then
      q_i(3) <= (q_i(3) and (q_i(1) or q_i(0))) or (q_i(2) and not q_i(1) and not q_i(0));
      q_i(2) <= (q_i(2) and (not q_i(1) or q_i(0))) or (not q_i(3) and q_i(1) and not q_i(0));
      q_i(1) <= (q_i(1) and not q_i(0)) or ((q_i(3) xnor q_i(2)) and q_i(0));
      q_i(0) <= not(q_i(3) xor q_i(2) xor q_i(1));
    end if;
  end if;
end process;
end gray4_1_arch;
------------------------------------------------------------------
library IEEE,mylib;
use IEEE.STD_LOGIC_1164.ALL;
use mylib.vtx_pack.all;
library UNISIM;
use UNISIM.VComponents.all;
entity tbufy16v2 is
    Port ( t : in std_logic;
           i : in std_logic_vector(15 downto 0);
           o : out std_logic_vector(15 downto 0));
end tbufy16v2;

architecture myarch of tbufy16v2 is
attribute RLOC : string;
attribute RLOC of i_tbuf15 : label is "x0y15";
attribute RLOC of i_tbuf14 : label is "x0y14";
attribute RLOC of i_tbuf13 : label is "x0y13";
attribute RLOC of i_tbuf12 : label is "x0y12";
attribute RLOC of i_tbuf11 : label is "x0y11";
attribute RLOC of i_tbuf10 : label is "x0y10";
attribute RLOC of i_tbuf9 : label is "x0y9";
attribute RLOC of i_tbuf8 : label is "x0y8";
attribute RLOC of i_tbuf7 : label is "x0y7";
attribute RLOC of i_tbuf6 : label is "x0y6";
attribute RLOC of i_tbuf5 : label is "x0y5";
attribute RLOC of i_tbuf4 : label is "x0y4";
attribute RLOC of i_tbuf3 : label is "x0y3";
attribute RLOC of i_tbuf2 : label is "x0y2";
attribute RLOC of i_tbuf1 : label is "x0y1";
attribute RLOC of i_tbuf0 : label is "x0y0";
begin
i_tbuf0: buft port map(t => t, i => i(0), o => o(0));
i_tbuf1: buft port map(t => t, i => i(1), o => o(1));
i_tbuf2: buft port map(t => t, i => i(2), o => o(2));
i_tbuf3: buft port map(t => t, i => i(3), o => o(3));
i_tbuf4: buft port map(t => t, i => i(4), o => o(4));
i_tbuf5: buft port map(t => t, i => i(5), o => o(5));
i_tbuf6: buft port map(t => t, i => i(6), o => o(6));
i_tbuf7: buft port map(t => t, i => i(7), o => o(7));
i_tbuf8: buft port map(t => t, i => i(8), o => o(8));
i_tbuf9: buft port map(t => t, i => i(9), o => o(9));
i_tbuf10: buft port map(t => t, i => i(10), o => o(10));
i_tbuf11: buft port map(t => t, i => i(11), o => o(11));
i_tbuf12: buft port map(t => t, i => i(12), o => o(12));
i_tbuf13: buft port map(t => t, i => i(13), o => o(13));
i_tbuf14: buft port map(t => t, i => i(14), o => o(14));
i_tbuf15: buft port map(t => t, i => i(15), o => o(15));
end myarch;
------------------------------------------------------------------
library IEEE,mylib;
use IEEE.STD_LOGIC_1164.ALL;
use mylib.vtx_pack.all;
library UNISIM;
use UNISIM.VComponents.all;
entity tbufy8v2 is
    Port ( t : in std_logic;
           i : in std_logic_vector(7 downto 0);
           o : out std_logic_vector(7 downto 0));
end tbufy8v2;

architecture myarch of tbufy8v2 is
attribute RLOC : string;
attribute RLOC of i_tbuf7 : label is "x0y7";
attribute RLOC of i_tbuf6 : label is "x0y6";
attribute RLOC of i_tbuf5 : label is "x0y5";
attribute RLOC of i_tbuf4 : label is "x0y4";
attribute RLOC of i_tbuf3 : label is "x0y3";
attribute RLOC of i_tbuf2 : label is "x0y2";
attribute RLOC of i_tbuf1 : label is "x0y1";
attribute RLOC of i_tbuf0 : label is "x0y0";
begin
i_tbuf0: buft port map(t => t, i => i(0), o => o(0));
i_tbuf1: buft port map(t => t, i => i(1), o => o(1));
i_tbuf2: buft port map(t => t, i => i(2), o => o(2));
i_tbuf3: buft port map(t => t, i => i(3), o => o(3));
i_tbuf4: buft port map(t => t, i => i(4), o => o(4));
i_tbuf5: buft port map(t => t, i => i(5), o => o(5));
i_tbuf6: buft port map(t => t, i => i(6), o => o(6));
i_tbuf7: buft port map(t => t, i => i(7), o => o(7));
end myarch;
------------------------------------------------------------------
library IEEE,mylib;
use IEEE.STD_LOGIC_1164.ALL;
use mylib.vtx_pack.all;
library UNISIM;
use UNISIM.VComponents.all;
entity tbufy11v2 is
    Port ( t : in std_logic;
           i : in std_logic_vector(10 downto 0);
           o : out std_logic_vector(10 downto 0));
end tbufy11v2;

architecture myarch of tbufy11v2 is
attribute RLOC : string;
attribute RLOC of i_tbuf10 : label is "x0y10";
attribute RLOC of i_tbuf9 : label is "x0y9";
attribute RLOC of i_tbuf8 : label is "x0y8";
attribute RLOC of i_tbuf7 : label is "x0y7";
attribute RLOC of i_tbuf6 : label is "x0y6";
attribute RLOC of i_tbuf5 : label is "x0y5";
attribute RLOC of i_tbuf4 : label is "x0y4";
attribute RLOC of i_tbuf3 : label is "x0y3";
attribute RLOC of i_tbuf2 : label is "x0y2";
attribute RLOC of i_tbuf1 : label is "x0y1";
attribute RLOC of i_tbuf0 : label is "x0y0";
begin
i_tbuf0: buft port map(t => t, i => i(0), o => o(0));
i_tbuf1: buft port map(t => t, i => i(1), o => o(1));
i_tbuf2: buft port map(t => t, i => i(2), o => o(2));
i_tbuf3: buft port map(t => t, i => i(3), o => o(3));
i_tbuf4: buft port map(t => t, i => i(4), o => o(4));
i_tbuf5: buft port map(t => t, i => i(5), o => o(5));
i_tbuf6: buft port map(t => t, i => i(6), o => o(6));
i_tbuf7: buft port map(t => t, i => i(7), o => o(7));
i_tbuf8: buft port map(t => t, i => i(8), o => o(8));
i_tbuf9: buft port map(t => t, i => i(9), o => o(9));
i_tbuf10: buft port map(t => t, i => i(10), o => o(10));
end myarch;
------------------------------------------------------------------
library IEEE,mylib;
use IEEE.STD_LOGIC_1164.ALL;
use mylib.vtx_pack.all;
library UNISIM;
use UNISIM.VComponents.all;
entity ebufy32v2 is
    Port ( e : in std_logic;
           i : in std_logic_vector(31 downto 0);
           o : out std_logic_vector(31 downto 0));
end ebufy32v2;

architecture myarch of ebufy32v2 is
attribute RLOC : string;
attribute RLOC of i_ebuf31 : label is "x0y31";
attribute RLOC of i_ebuf30 : label is "x0y30";
attribute RLOC of i_ebuf29 : label is "x0y29";
attribute RLOC of i_ebuf28 : label is "x0y28";
attribute RLOC of i_ebuf27 : label is "x0y27";
attribute RLOC of i_ebuf26 : label is "x0y26";
attribute RLOC of i_ebuf25 : label is "x0y25";
attribute RLOC of i_ebuf24 : label is "x0y24";
attribute RLOC of i_ebuf23 : label is "x0y23";
attribute RLOC of i_ebuf22 : label is "x0y22";
attribute RLOC of i_ebuf21 : label is "x0y21";
attribute RLOC of i_ebuf20 : label is "x0y20";
attribute RLOC of i_ebuf19 : label is "x0y19";
attribute RLOC of i_ebuf18 : label is "x0y18";
attribute RLOC of i_ebuf17 : label is "x0y17";
attribute RLOC of i_ebuf16 : label is "x0y16";
attribute RLOC of i_ebuf15 : label is "x0y15";
attribute RLOC of i_ebuf14 : label is "x0y14";
attribute RLOC of i_ebuf13 : label is "x0y13";
attribute RLOC of i_ebuf12 : label is "x0y12";
attribute RLOC of i_ebuf11 : label is "x0y11";
attribute RLOC of i_ebuf10 : label is "x0y10";
attribute RLOC of i_ebuf9 : label is "x0y9";
attribute RLOC of i_ebuf8 : label is "x0y8";
attribute RLOC of i_ebuf7 : label is "x0y7";
attribute RLOC of i_ebuf6 : label is "x0y6";
attribute RLOC of i_ebuf5 : label is "x0y5";
attribute RLOC of i_ebuf4 : label is "x0y4";
attribute RLOC of i_ebuf3 : label is "x0y3";
attribute RLOC of i_ebuf2 : label is "x0y2";
attribute RLOC of i_ebuf1 : label is "x0y1";
attribute RLOC of i_ebuf0 : label is "x0y0";
begin
i_ebuf0: bufe port map(e => e, i => i(0), o => o(0));
i_ebuf1: bufe port map(e => e, i => i(1), o => o(1));
i_ebuf2: bufe port map(e => e, i => i(2), o => o(2));
i_ebuf3: bufe port map(e => e, i => i(3), o => o(3));
i_ebuf4: bufe port map(e => e, i => i(4), o => o(4));
i_ebuf5: bufe port map(e => e, i => i(5), o => o(5));
i_ebuf6: bufe port map(e => e, i => i(6), o => o(6));
i_ebuf7: bufe port map(e => e, i => i(7), o => o(7));
i_ebuf8: bufe port map(e => e, i => i(8), o => o(8));
i_ebuf9: bufe port map(e => e, i => i(9), o => o(9));
i_ebuf10: bufe port map(e => e, i => i(10), o => o(10));
i_ebuf11: bufe port map(e => e, i => i(11), o => o(11));
i_ebuf12: bufe port map(e => e, i => i(12), o => o(12));
i_ebuf13: bufe port map(e => e, i => i(13), o => o(13));
i_ebuf14: bufe port map(e => e, i => i(14), o => o(14));
i_ebuf15: bufe port map(e => e, i => i(15), o => o(15));
i_ebuf16: bufe port map(e => e, i => i(16), o => o(16));
i_ebuf17: bufe port map(e => e, i => i(17), o => o(17));
i_ebuf18: bufe port map(e => e, i => i(18), o => o(18));
i_ebuf19: bufe port map(e => e, i => i(19), o => o(19));
i_ebuf20: bufe port map(e => e, i => i(20), o => o(20));
i_ebuf21: bufe port map(e => e, i => i(21), o => o(21));
i_ebuf22: bufe port map(e => e, i => i(22), o => o(22));
i_ebuf23: bufe port map(e => e, i => i(23), o => o(23));
i_ebuf24: bufe port map(e => e, i => i(24), o => o(24));
i_ebuf25: bufe port map(e => e, i => i(25), o => o(25));
i_ebuf26: bufe port map(e => e, i => i(26), o => o(26));
i_ebuf27: bufe port map(e => e, i => i(27), o => o(27));
i_ebuf28: bufe port map(e => e, i => i(28), o => o(28));
i_ebuf29: bufe port map(e => e, i => i(29), o => o(29));
i_ebuf30: bufe port map(e => e, i => i(30), o => o(30));
i_ebuf31: bufe port map(e => e, i => i(31), o => o(31));
end myarch;
------------------------------------------------------------------
library IEEE,mylib;
use IEEE.STD_LOGIC_1164.ALL;
use mylib.vtx_pack.all;
library UNISIM;
use UNISIM.VComponents.all;
entity tbufy16 is
    Port ( t : in std_logic;
           i : in std_logic_vector(15 downto 0);
           o : out std_logic_vector(15 downto 0));
end tbufy16;

architecture myarch of tbufy16 is
attribute RLOC : string;
attribute RLOC of i_tbuf15 : label is "R0C0.0";
attribute RLOC of i_tbuf14 : label is "R0C0.1";
attribute RLOC of i_tbuf13 : label is "R1C0.0";
attribute RLOC of i_tbuf12 : label is "R1C0.1";
attribute RLOC of i_tbuf11 : label is "R2C0.0";
attribute RLOC of i_tbuf10 : label is "R2C0.1";
attribute RLOC of i_tbuf9 : label is "R3C0.0";
attribute RLOC of i_tbuf8 : label is "R3C0.1";
attribute RLOC of i_tbuf7 : label is "R4C0.0";
attribute RLOC of i_tbuf6 : label is "R4C0.1";
attribute RLOC of i_tbuf5 : label is "R5C0.0";
attribute RLOC of i_tbuf4 : label is "R5C0.1";
attribute RLOC of i_tbuf3 : label is "R6C0.0";
attribute RLOC of i_tbuf2 : label is "R6C0.1";
attribute RLOC of i_tbuf1 : label is "R7C0.0";
attribute RLOC of i_tbuf0 : label is "R7C0.1";
begin
i_tbuf0: buft port map(t => t, i => i(0), o => o(0));
i_tbuf1: buft port map(t => t, i => i(1), o => o(1));
i_tbuf2: buft port map(t => t, i => i(2), o => o(2));
i_tbuf3: buft port map(t => t, i => i(3), o => o(3));
i_tbuf4: buft port map(t => t, i => i(4), o => o(4));
i_tbuf5: buft port map(t => t, i => i(5), o => o(5));
i_tbuf6: buft port map(t => t, i => i(6), o => o(6));
i_tbuf7: buft port map(t => t, i => i(7), o => o(7));
i_tbuf8: buft port map(t => t, i => i(8), o => o(8));
i_tbuf9: buft port map(t => t, i => i(9), o => o(9));
i_tbuf10: buft port map(t => t, i => i(10), o => o(10));
i_tbuf11: buft port map(t => t, i => i(11), o => o(11));
i_tbuf12: buft port map(t => t, i => i(12), o => o(12));
i_tbuf13: buft port map(t => t, i => i(13), o => o(13));
i_tbuf14: buft port map(t => t, i => i(14), o => o(14));
i_tbuf15: buft port map(t => t, i => i(15), o => o(15));
end myarch;
------------------------------------------------------------------
library IEEE,mylib;
use IEEE.STD_LOGIC_1164.ALL;
use mylib.vtx_pack.all;
library UNISIM;
use UNISIM.VComponents.all;
entity tbufy8 is
    Port ( t : in std_logic;
           i : in std_logic_vector(7 downto 0);
           o : out std_logic_vector(7 downto 0));
end tbufy8;

architecture myarch of tbufy8 is
attribute RLOC : string;
attribute RLOC of i_tbuf7 : label is "R0C0.0";
attribute RLOC of i_tbuf6 : label is "R0C0.1";
attribute RLOC of i_tbuf5 : label is "R1C0.0";
attribute RLOC of i_tbuf4 : label is "R1C0.1";
attribute RLOC of i_tbuf3 : label is "R2C0.0";
attribute RLOC of i_tbuf2 : label is "R2C0.1";
attribute RLOC of i_tbuf1 : label is "R3C0.0";
attribute RLOC of i_tbuf0 : label is "R3C0.1";
begin
i_tbuf0: buft port map(t => t, i => i(0), o => o(0));
i_tbuf1: buft port map(t => t, i => i(1), o => o(1));
i_tbuf2: buft port map(t => t, i => i(2), o => o(2));
i_tbuf3: buft port map(t => t, i => i(3), o => o(3));
i_tbuf4: buft port map(t => t, i => i(4), o => o(4));
i_tbuf5: buft port map(t => t, i => i(5), o => o(5));
i_tbuf6: buft port map(t => t, i => i(6), o => o(6));
i_tbuf7: buft port map(t => t, i => i(7), o => o(7));
end myarch;
----------------------------------------------------------
library IEEE,mylib;
use IEEE.STD_LOGIC_1164.ALL;
use mylib.vtx_pack.all;
library UNISIM;
use UNISIM.VComponents.all;
entity tbufy26 is
    Port ( t : in std_logic;
           i : in std_logic_vector(25 downto 0);
           o : out std_logic_vector(25 downto 0));
end tbufy26;

architecture myarch of tbufy26 is
attribute RLOC : string;
attribute RLOC of i_tbuf25 : label is "R0C0.0";
attribute RLOC of i_tbuf24 : label is "R0C0.1";
attribute RLOC of i_tbuf23 : label is "R1C0.0";
attribute RLOC of i_tbuf22 : label is "R1C0.1";
attribute RLOC of i_tbuf21 : label is "R2C0.0";
attribute RLOC of i_tbuf20 : label is "R2C0.1";
attribute RLOC of i_tbuf19 : label is "R3C0.0";
attribute RLOC of i_tbuf18 : label is "R3C0.1";
attribute RLOC of i_tbuf17 : label is "R4C0.0";
attribute RLOC of i_tbuf16 : label is "R4C0.1";
attribute RLOC of i_tbuf15 : label is "R5C0.0";
attribute RLOC of i_tbuf14 : label is "R5C0.1";
attribute RLOC of i_tbuf13 : label is "R6C0.0";
attribute RLOC of i_tbuf12 : label is "R6C0.1";
attribute RLOC of i_tbuf11 : label is "R7C0.0";
attribute RLOC of i_tbuf10 : label is "R7C0.1";
attribute RLOC of i_tbuf9 : label is "R8C0.0";
attribute RLOC of i_tbuf8 : label is "R8C0.1";
attribute RLOC of i_tbuf7 : label is "R9C0.0";
attribute RLOC of i_tbuf6 : label is "R9C0.1";
attribute RLOC of i_tbuf5 : label is "R10C0.0";
attribute RLOC of i_tbuf4 : label is "R10C0.1";
attribute RLOC of i_tbuf3 : label is "R11C0.0";
attribute RLOC of i_tbuf2 : label is "R11C0.1";
attribute RLOC of i_tbuf1 : label is "R12C0.0";
attribute RLOC of i_tbuf0 : label is "R12C0.1";
begin
i_tbuf0: buft port map(t => t, i => i(0), o => o(0));
i_tbuf1: buft port map(t => t, i => i(1), o => o(1));
i_tbuf2: buft port map(t => t, i => i(2), o => o(2));
i_tbuf3: buft port map(t => t, i => i(3), o => o(3));
i_tbuf4: buft port map(t => t, i => i(4), o => o(4));
i_tbuf5: buft port map(t => t, i => i(5), o => o(5));
i_tbuf6: buft port map(t => t, i => i(6), o => o(6));
i_tbuf7: buft port map(t => t, i => i(7), o => o(7));
i_tbuf8: buft port map(t => t, i => i(8), o => o(8));
i_tbuf9: buft port map(t => t, i => i(9), o => o(9));
i_tbuf10: buft port map(t => t, i => i(10), o => o(10));
i_tbuf11: buft port map(t => t, i => i(11), o => o(11));
i_tbuf12: buft port map(t => t, i => i(12), o => o(12));
i_tbuf13: buft port map(t => t, i => i(13), o => o(13));
i_tbuf14: buft port map(t => t, i => i(14), o => o(14));
i_tbuf15: buft port map(t => t, i => i(15), o => o(15));
i_tbuf16: buft port map(t => t, i => i(16), o => o(16));
i_tbuf17: buft port map(t => t, i => i(17), o => o(17));
i_tbuf18: buft port map(t => t, i => i(18), o => o(18));
i_tbuf19: buft port map(t => t, i => i(19), o => o(19));
i_tbuf20: buft port map(t => t, i => i(20), o => o(20));
i_tbuf21: buft port map(t => t, i => i(21), o => o(21));
i_tbuf22: buft port map(t => t, i => i(22), o => o(22));
i_tbuf23: buft port map(t => t, i => i(23), o => o(23));
i_tbuf24: buft port map(t => t, i => i(24), o => o(24));
i_tbuf25: buft port map(t => t, i => i(25), o => o(25));
end myarch;
----------------------------------------------------------
library IEEE,mylib;
use IEEE.STD_LOGIC_1164.ALL;
use mylib.vtx_pack.all;
library UNISIM;
use UNISIM.VComponents.all;
entity tbufy32 is
    Port ( t : in std_logic;
           i : in std_logic_vector(31 downto 0);
           o : out std_logic_vector(31 downto 0));
end tbufy32;

architecture myarch of tbufy32 is
attribute RLOC : string;
attribute RLOC of i_tbuf31 : label is "R0C0.0";
attribute RLOC of i_tbuf30 : label is "R0C0.1";
attribute RLOC of i_tbuf29 : label is "R1C0.0";
attribute RLOC of i_tbuf28 : label is "R1C0.1";
attribute RLOC of i_tbuf27 : label is "R2C0.0";
attribute RLOC of i_tbuf26 : label is "R2C0.1";
attribute RLOC of i_tbuf25 : label is "R3C0.0";
attribute RLOC of i_tbuf24 : label is "R3C0.1";
attribute RLOC of i_tbuf23 : label is "R4C0.0";
attribute RLOC of i_tbuf22 : label is "R4C0.1";
attribute RLOC of i_tbuf21 : label is "R5C0.0";
attribute RLOC of i_tbuf20 : label is "R5C0.1";
attribute RLOC of i_tbuf19 : label is "R6C0.0";
attribute RLOC of i_tbuf18 : label is "R6C0.1";
attribute RLOC of i_tbuf17 : label is "R7C0.0";
attribute RLOC of i_tbuf16 : label is "R7C0.1";
attribute RLOC of i_tbuf15 : label is "R8C0.0";
attribute RLOC of i_tbuf14 : label is "R8C0.1";
attribute RLOC of i_tbuf13 : label is "R9C0.0";
attribute RLOC of i_tbuf12 : label is "R9C0.1";
attribute RLOC of i_tbuf11 : label is "R10C0.0";
attribute RLOC of i_tbuf10 : label is "R10C0.1";
attribute RLOC of i_tbuf9 : label is "R11C0.0";
attribute RLOC of i_tbuf8 : label is "R11C0.1";
attribute RLOC of i_tbuf7 : label is "R12C0.0";
attribute RLOC of i_tbuf6 : label is "R12C0.1";
attribute RLOC of i_tbuf5 : label is "R13C0.0";
attribute RLOC of i_tbuf4 : label is "R13C0.1";
attribute RLOC of i_tbuf3 : label is "R14C0.0";
attribute RLOC of i_tbuf2 : label is "R14C0.1";
attribute RLOC of i_tbuf1 : label is "R15C0.0";
attribute RLOC of i_tbuf0 : label is "R15C0.1";
begin
i_tbuf0: buft port map(t => t, i => i(0), o => o(0));
i_tbuf1: buft port map(t => t, i => i(1), o => o(1));
i_tbuf2: buft port map(t => t, i => i(2), o => o(2));
i_tbuf3: buft port map(t => t, i => i(3), o => o(3));
i_tbuf4: buft port map(t => t, i => i(4), o => o(4));
i_tbuf5: buft port map(t => t, i => i(5), o => o(5));
i_tbuf6: buft port map(t => t, i => i(6), o => o(6));
i_tbuf7: buft port map(t => t, i => i(7), o => o(7));
i_tbuf8: buft port map(t => t, i => i(8), o => o(8));
i_tbuf9: buft port map(t => t, i => i(9), o => o(9));
i_tbuf10: buft port map(t => t, i => i(10), o => o(10));
i_tbuf11: buft port map(t => t, i => i(11), o => o(11));
i_tbuf12: buft port map(t => t, i => i(12), o => o(12));
i_tbuf13: buft port map(t => t, i => i(13), o => o(13));
i_tbuf14: buft port map(t => t, i => i(14), o => o(14));
i_tbuf15: buft port map(t => t, i => i(15), o => o(15));
i_tbuf16: buft port map(t => t, i => i(16), o => o(16));
i_tbuf17: buft port map(t => t, i => i(17), o => o(17));
i_tbuf18: buft port map(t => t, i => i(18), o => o(18));
i_tbuf19: buft port map(t => t, i => i(19), o => o(19));
i_tbuf20: buft port map(t => t, i => i(20), o => o(20));
i_tbuf21: buft port map(t => t, i => i(21), o => o(21));
i_tbuf22: buft port map(t => t, i => i(22), o => o(22));
i_tbuf23: buft port map(t => t, i => i(23), o => o(23));
i_tbuf24: buft port map(t => t, i => i(24), o => o(24));
i_tbuf25: buft port map(t => t, i => i(25), o => o(25));
i_tbuf26: buft port map(t => t, i => i(26), o => o(26));
i_tbuf27: buft port map(t => t, i => i(27), o => o(27));
i_tbuf28: buft port map(t => t, i => i(28), o => o(28));
i_tbuf29: buft port map(t => t, i => i(29), o => o(29));
i_tbuf30: buft port map(t => t, i => i(30), o => o(30));
i_tbuf31: buft port map(t => t, i => i(31), o => o(31));
end myarch;
----------------------------------------------------------
library IEEE,mylib;
use IEEE.STD_LOGIC_1164.ALL;
use mylib.vtx_pack.all;
library UNISIM;
use UNISIM.VComponents.all;
entity tbufy33 is
    Port ( t : in std_logic;
           i : in std_logic_vector(32 downto 0);
           o : out std_logic_vector(32 downto 0));
end tbufy33;

architecture myarch of tbufy33 is
attribute RLOC : string;
attribute RLOC of i_tbuf32 : label is "R0C0.1";
attribute RLOC of i_tbuf31 : label is "R0C0.0";
attribute RLOC of i_tbuf30 : label is "R1C0.1";
attribute RLOC of i_tbuf29 : label is "R1C0.0";
attribute RLOC of i_tbuf28 : label is "R2C0.1";
attribute RLOC of i_tbuf27 : label is "R2C0.0";
attribute RLOC of i_tbuf26 : label is "R3C0.1";
attribute RLOC of i_tbuf25 : label is "R3C0.0";
attribute RLOC of i_tbuf24 : label is "R4C0.1";
attribute RLOC of i_tbuf23 : label is "R4C0.0";
attribute RLOC of i_tbuf22 : label is "R5C0.1";
attribute RLOC of i_tbuf21 : label is "R5C0.0";
attribute RLOC of i_tbuf20 : label is "R6C0.1";
attribute RLOC of i_tbuf19 : label is "R6C0.0";
attribute RLOC of i_tbuf18 : label is "R7C0.1";
attribute RLOC of i_tbuf17 : label is "R7C0.0";
attribute RLOC of i_tbuf16 : label is "R8C0.1";
attribute RLOC of i_tbuf15 : label is "R8C0.0";
attribute RLOC of i_tbuf14 : label is "R9C0.1";
attribute RLOC of i_tbuf13 : label is "R9C0.0";
attribute RLOC of i_tbuf12 : label is "R10C0.1";
attribute RLOC of i_tbuf11 : label is "R10C0.0";
attribute RLOC of i_tbuf10 : label is "R11C0.1";
attribute RLOC of i_tbuf9 : label is "R11C0.0";
attribute RLOC of i_tbuf8 : label is "R12C0.1";
attribute RLOC of i_tbuf7 : label is "R12C0.0";
attribute RLOC of i_tbuf6 : label is "R13C0.1";
attribute RLOC of i_tbuf5 : label is "R13C0.0";
attribute RLOC of i_tbuf4 : label is "R14C0.1";
attribute RLOC of i_tbuf3 : label is "R14C0.0";
attribute RLOC of i_tbuf2 : label is "R15C0.1";
attribute RLOC of i_tbuf1 : label is "R15C0.0";
attribute RLOC of i_tbuf0 : label is "R16C0.1";
begin
i_tbuf0: buft port map(t => t, i => i(0), o => o(0));
i_tbuf1: buft port map(t => t, i => i(1), o => o(1));
i_tbuf2: buft port map(t => t, i => i(2), o => o(2));
i_tbuf3: buft port map(t => t, i => i(3), o => o(3));
i_tbuf4: buft port map(t => t, i => i(4), o => o(4));
i_tbuf5: buft port map(t => t, i => i(5), o => o(5));
i_tbuf6: buft port map(t => t, i => i(6), o => o(6));
i_tbuf7: buft port map(t => t, i => i(7), o => o(7));
i_tbuf8: buft port map(t => t, i => i(8), o => o(8));
i_tbuf9: buft port map(t => t, i => i(9), o => o(9));
i_tbuf10: buft port map(t => t, i => i(10), o => o(10));
i_tbuf11: buft port map(t => t, i => i(11), o => o(11));
i_tbuf12: buft port map(t => t, i => i(12), o => o(12));
i_tbuf13: buft port map(t => t, i => i(13), o => o(13));
i_tbuf14: buft port map(t => t, i => i(14), o => o(14));
i_tbuf15: buft port map(t => t, i => i(15), o => o(15));
i_tbuf16: buft port map(t => t, i => i(16), o => o(16));
i_tbuf17: buft port map(t => t, i => i(17), o => o(17));
i_tbuf18: buft port map(t => t, i => i(18), o => o(18));
i_tbuf19: buft port map(t => t, i => i(19), o => o(19));
i_tbuf20: buft port map(t => t, i => i(20), o => o(20));
i_tbuf21: buft port map(t => t, i => i(21), o => o(21));
i_tbuf22: buft port map(t => t, i => i(22), o => o(22));
i_tbuf23: buft port map(t => t, i => i(23), o => o(23));
i_tbuf24: buft port map(t => t, i => i(24), o => o(24));
i_tbuf25: buft port map(t => t, i => i(25), o => o(25));
i_tbuf26: buft port map(t => t, i => i(26), o => o(26));
i_tbuf27: buft port map(t => t, i => i(27), o => o(27));
i_tbuf28: buft port map(t => t, i => i(28), o => o(28));
i_tbuf29: buft port map(t => t, i => i(29), o => o(29));
i_tbuf30: buft port map(t => t, i => i(30), o => o(30));
i_tbuf31: buft port map(t => t, i => i(31), o => o(31));
i_tbuf32: buft port map(t => t, i => i(32), o => o(32));
end myarch;
----------------------------------------------------------
library IEEE,mylib;
use IEEE.STD_LOGIC_1164.ALL;
use mylib.vtx_pack.all;
library UNISIM;
use UNISIM.VComponents.all;
entity tbufy17 is
    Port ( t : in std_logic;
           i : in std_logic_vector(16 downto 0);
           o : out std_logic_vector(16 downto 0));
end tbufy17;

architecture myarch of tbufy17 is
attribute RLOC : string;
attribute RLOC of i_tbuf16 : label is "R0C0.1";
attribute RLOC of i_tbuf15 : label is "R1C0.0";
attribute RLOC of i_tbuf14 : label is "R1C0.1";
attribute RLOC of i_tbuf13 : label is "R2C0.0";
attribute RLOC of i_tbuf12 : label is "R2C0.1";
attribute RLOC of i_tbuf11 : label is "R3C0.0";
attribute RLOC of i_tbuf10 : label is "R3C0.1";
attribute RLOC of i_tbuf9 : label is "R4C0.0";
attribute RLOC of i_tbuf8 : label is "R4C0.1";
attribute RLOC of i_tbuf7 : label is "R5C0.0";
attribute RLOC of i_tbuf6 : label is "R5C0.1";
attribute RLOC of i_tbuf5 : label is "R6C0.0";
attribute RLOC of i_tbuf4 : label is "R6C0.1";
attribute RLOC of i_tbuf3 : label is "R7C0.0";
attribute RLOC of i_tbuf2 : label is "R7C0.1";
attribute RLOC of i_tbuf1 : label is "R8C0.0";
attribute RLOC of i_tbuf0 : label is "R8C0.1";
begin
i_tbuf0: buft port map(t => t, i => i(0), o => o(0));
i_tbuf1: buft port map(t => t, i => i(1), o => o(1));
i_tbuf2: buft port map(t => t, i => i(2), o => o(2));
i_tbuf3: buft port map(t => t, i => i(3), o => o(3));
i_tbuf4: buft port map(t => t, i => i(4), o => o(4));
i_tbuf5: buft port map(t => t, i => i(5), o => o(5));
i_tbuf6: buft port map(t => t, i => i(6), o => o(6));
i_tbuf7: buft port map(t => t, i => i(7), o => o(7));
i_tbuf8: buft port map(t => t, i => i(8), o => o(8));
i_tbuf9: buft port map(t => t, i => i(9), o => o(9));
i_tbuf10: buft port map(t => t, i => i(10), o => o(10));
i_tbuf11: buft port map(t => t, i => i(11), o => o(11));
i_tbuf12: buft port map(t => t, i => i(12), o => o(12));
i_tbuf13: buft port map(t => t, i => i(13), o => o(13));
i_tbuf14: buft port map(t => t, i => i(14), o => o(14));
i_tbuf15: buft port map(t => t, i => i(15), o => o(15));
i_tbuf16: buft port map(t => t, i => i(16), o => o(16));
end myarch;
----------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library UNISIM;
use UNISIM.VComponents.all;

entity ddr_io is
    port (
        clk: in STD_LOGIC;
        clkn: in STD_LOGIC;
        pad: inout std_logic;
        t: in STD_LOGIC;
        d0: in STD_LOGIC;
        d1: in STD_LOGIC;
        iclk: in STD_LOGIC;
        iclkn: in STD_LOGIC;
        q0: out std_logic; -- rising edge       
        q1: out std_logic  -- falling edge    
    );
end ddr_io;

architecture ddr_io_arch of ddr_io is
signal din, oq, tq: std_logic;
attribute IOB : string;
attribute IOB of q0_reg,q1_reg,tq_reg: label is "TRUE";
begin
ib: ibuf port map(i => pad, o => din);
q0_reg: fd port map(d => din, c=> iclk, q => q0);
q1_reg: fd port map(d => din, c=> iclkn, q => q1);
oq_reg:  fddrrse
    port map(
          d0 => d0,
          d1 => d1,
          c0 => clk,
          c1 => clkn,
          ce => '1',
          r  => '0',
          s  => '0',
          q  => oq);
tq_reg:  fd
    port map(
          d => t,
          c => clk,
          q  => tq);
ob: obuft port map( i => oq, o => pad, t => tq);
end ddr_io_arch;
----------------------------------------------------------
library IEEE,mylib;
use IEEE.std_logic_1164.all;
use mylib.vtx_pack.all;
library UNISIM;
use UNISIM.VComponents.all;

entity ddr_in is
    port (
        clk: in STD_LOGIC;
        pad: in std_logic;
        q0: out std_logic; -- rising edge       
        q1: out std_logic  -- falling edge    
    );
end ddr_in;

architecture ddr_in_arch of ddr_in is
signal clkn, din: std_logic;
attribute IOB : string;
attribute IOB of q0_reg,q1_reg: label is "TRUE";
begin
clkn <= not clk;
ib: ibuf port map(i => pad, o => din);
q0_reg: fd port map(d => din, c=> clk, q => q0);
q1_reg: fd port map(d => din, c=> clkn, q => q1);
end ddr_in_arch;
----------------------------------
library IEEE,mylib;
use IEEE.STD_LOGIC_1164.ALL;
use mylib.vtx_pack.all;
library UNISIM;
use UNISIM.VComponents.all;

entity multNx2 is
-- if roundup is true, 1/2 LSB of the input a is added to the output
-- this result in the roundup of the output to the same length as
-- input a
    generic(N : positive := 8; roundup : boolean := false);
    Port ( a : in std_logic_vector(N-1 downto 0);
           b : in std_logic_vector(1 downto 0);
           o : out std_logic_vector(N+1 downto 0));
end multNX2;

architecture my_arch of multNX2 is
signal di:		std_logic_vector(N-2 downto 0);
signal s:		std_logic_vector(N-1 downto 0);
signal ci:	   std_logic_vector(N-1 downto 0);
begin
o(0) <= a(0) and b(0);
ci(0) <= '1' when roundup else '0';
g: for i in 0 to N-2 generate
  s(i) <= (a(i+1) and b(0)) xor (a(i) and b(1));
  mxcy: muxcy	    port map (S => s(i),
                            DI => di(i),
                            CI => ci(i),
                             O => ci(i+1));
  multand: mult_and port map ( I0 => a(i),
  		               I1 => b(1),
  		               LO => di(i));
  xocy: xorcy       port map ( LI => s(i),
  		               CI => ci(i),
  		                O => o(i+1));
end generate;
s(N-1) <= a(N-1) and b(1);
mxcy_N: muxcy	    port map (S => s(N-1),
                            DI => '0',
                            CI => ci(N-1),
                             O => o(N+1));
xocy_N: xorcy       port map ( LI => s(N-1),
  		               CI => ci(N-1),
  		                O => o(N));
end my_arch;