A special version of pci1 interface has been built for STT debugging purposes.
It has the following features:
1. PCIID as 0x10070 version number is 0xb

2. bar0 size is 0x10 bytes
 offset 0x0
   bit (31-16) should be set to mip2 memoffs(31-16), bit 16 is always '0'.
   (!!!! LRB must be on mip2 site !!!!
    FRC input must be on channel 0.
    HIT input must be on channel 1.
    If bit(5) is set, channel 2 is used as the HIT input of the second STC unit)
   bit(5) enables HIT output comparison between the two STC units.
   bit(4) enables stopping on LRB error of all used channels.
   bit(3) enables stopping on L1CTT checksum errors
   bit(2) enables stopping on FRC data BX mismatches (between header,l1ctt data and trailer)
   bit(1) enables stopping on FRC data word count mismatches
   bit(0) enables stopping on FRC data length less than 8 or greater than 56
   bit(15-6) are read only bits, resetting to zeros when '1' is written to offset 0x2800c
             of log3 bar0 (STC_RESET)
   bit(15) is set if hit data length != hit_count + 2
   bit(14) is set if hit data header(31-28) != "1100" or  trailer(31-28) != "1111" or
           BX mismatches the corresponding FRC BX taken from the header word.
   bit(13) is set if bit(5) is set and difference found.
   bit(12-8) correspond to errors defined by bit(4-0)
   bit(7-6) is the difference between N_FRC and N_HIT, defined as N_DIF

 offset 0x4 is read only and counts the number of FRC data block read, defined as N_FRC.
              the number of HIT data block read, N_HIT = N_FRC - N_DIF 

3. bar1 size is 0x1000
   0x0 - 0x3ff => FRC test data memory  
   0x400 - 0x4ff => stores FRC data of Nth block, N = 4*int((N_FRC-1)/4)+1   
   0x500 - 0x5ff => stores FRC data of Nth block, N = 4*int((N_FRC-2)/4)+2   
   0x600 - 0x6ff => stores FRC data of Nth block, N = 4*int((N_FRC-3)/4)+3   
   0x700 - 0x7ff => stores FRC data of Nth block, N = 4*int(N_FRC/4)   
   0x800 - 0xbff => stores the last HIT data block read from channel 1
   0xc00 - 0xfff not used  

4. Once N_DIF reaches 3, no more FRC data will be read from channel 0. If HIT block
   does not come, it must be reset by STC_RESET

5. if bit(15-13) of bar0 are not all zero, no more data will be read from the LRB.
   This must be reset by STC_RESET

6. if nth bit in the range of 12-8 of bar0 and its corresponding n-8th bit are both set, 
   no more FRC data will be read from channel 0. This must be reset by STC_RESET