Design Name | oslb_cpld |
Fitting Status | Successful |
Software Version | J.40 |
Device Used | XC95144XL-10-TQ100 |
Date | 1-30-2008, 4:41PM |
Macrocells Used | Pterms Used | Registers Used | Pins Used | Function Block Inputs Used |
---|---|---|---|---|
106/144 (74%) | 494/720 (69%) | 72/144 (50%) | 68/81 (84%) | 303/432 (71%) |
|
|
Signal mapped onto global clock net (GCK1) | cclk |
Signal mapped onto global clock net (GCK3) | loc_cs |
Macrocells in high performance mode (MCHP) | 0 |
Macrocells in low power mode (MCLP) | 106 |
Total macrocells used (MC) | 106 |