********** Mapped Logic ********** |
Mxor_crc_10_xor0000__xor0000/Mxor_crc_10_xor0000__xor0000_D <= NOT (crc(16)
XOR Mxor_crc_10_xor0000__xor0000/Mxor_crc_10_xor0000__xor0000_D <= NOT (((crc(20) AND crc(2)) OR (NOT crc(20) AND NOT crc(2)))); |
Mxor_crc_23_xor0000__xor0000/Mxor_crc_23_xor0000__xor0000_D <= NOT (crc(19)
XOR Mxor_crc_23_xor0000__xor0000/Mxor_crc_23_xor0000__xor0000_D <= NOT (((crc(20) AND crc(15)) OR (NOT crc(20) AND NOT crc(15)))); |
Mxor_crc_5_xor0000__xor0000/Mxor_crc_5_xor0000__xor0000_D <= NOT (crc(19)
XOR Mxor_crc_5_xor0000__xor0000/Mxor_crc_5_xor0000__xor0000_D <= NOT (((crc(23) AND mdata(5).PIN) OR (NOT crc(23) AND NOT mdata(5).PIN))); |
cclk_fbp <= ring_os(2); |
cclkp <= NOT (((EXP12_.EXP)
OR (cfg_done AND NOT ctrl_in(0)) OR (NOT loc_cs AND cfg_done AND ctrl_in(1)) OR (NOT cfg_done AND NOT loc_mode AND div(4)))); |
FDCPE_cfg_done: FDCPE port map (cfg_done,'1',cclk,cfg_done_CLR,'0',cfg_done_CE);
cfg_done_CLR <= (NOT init_b AND NOT powerup); cfg_done_CE <= (done AND maddr(0) AND NOT maddr(15) AND maddr(16) AND maddr(17) AND maddr(1) AND maddr(2) AND NOT maddr(3) AND NOT maddr(4) AND maddr(5) AND NOT maddr(6) AND maddr(8) AND maddr(10) AND maddr(11) AND maddr(12) AND maddr(13) AND NOT maddr(14) AND maddr(7) AND NOT maddr(9)); |
FDCPE_crc0: FDCPE port map (crc(0),crc_D(0),cclk,'0',crc_PRE(0),crc_CE(0));
crc_D(0) <= crc(17) XOR crc_D(0) <= ((EXP25_.EXP) OR (r_data(0).EXP) OR (crc(18) AND crc(21) AND mdata(0).PIN AND crc_0_xor0001/crc_0_xor0001_D) OR (crc(18) AND crc(21) AND NOT mdata(0).PIN AND NOT crc_0_xor0001/crc_0_xor0001_D)); crc_PRE(0) <= (NOT init_b AND NOT powerup); crc_CE(0) <= (NOT cfg_done AND en_conf); |
FDCPE_crc1: FDCPE port map (crc(1),crc_D(1),cclk,'0',crc_PRE(1),crc_CE(1));
crc_D(1) <= crc(22) XOR crc_D(1) <= ((crc(16) AND mdata(1).PIN) OR (NOT crc(16) AND NOT mdata(1).PIN)); crc_PRE(1) <= (NOT init_b AND NOT powerup); crc_CE(1) <= (NOT cfg_done AND en_conf); |
FDCPE_crc2: FDCPE port map (crc(2),crc_D(2),cclk,'0',crc_PRE(2),crc_CE(2));
crc_D(2) <= crc(17) XOR crc_D(2) <= ((crc(23) AND mdata(2).PIN) OR (NOT crc(23) AND NOT mdata(2).PIN)); crc_PRE(2) <= (NOT init_b AND NOT powerup); crc_CE(2) <= (NOT cfg_done AND en_conf); |
FDCPE_crc3: FDCPE port map (crc(3),crc_D(3),cclk,'0',crc_PRE(3),crc_CE(3));
crc_D(3) <= crc(19) XOR crc_D(3) <= ((EXP28_.EXP) OR (EXP29_.EXP) OR (crc(16) AND crc(17) AND crc(20) AND crc(21) AND NOT mdata(3).PIN) OR (crc(16) AND crc(17) AND crc(20) AND NOT crc(21) AND mdata(3).PIN)); crc_PRE(3) <= (NOT init_b AND NOT powerup); crc_CE(3) <= (NOT cfg_done AND en_conf); |
FDCPE_crc4: FDCPE port map (crc(4),crc_D(4),cclk,'0',crc_PRE(4),crc_CE(4));
crc_D(4) <= crc(22) XOR crc_D(4) <= EXP13_.EXP; crc_PRE(4) <= (NOT init_b AND NOT powerup); crc_CE(4) <= (NOT cfg_done AND en_conf); |
FDCPE_crc5: FDCPE port map (crc(5),crc_D(5),cclk,'0',crc_PRE(5),crc_CE(5));
crc_D(5) <= crc(16) XOR crc_D(5) <= ((crc(11).EXP) OR (crc(18) AND crc(21) AND NOT Mxor_crc_5_xor0000__xor0000/Mxor_crc_5_xor0000__xor0000_D) OR (crc(18) AND NOT crc(21) AND Mxor_crc_5_xor0000__xor0000/Mxor_crc_5_xor0000__xor0000_D)); crc_PRE(5) <= (NOT init_b AND NOT powerup); crc_CE(5) <= (NOT cfg_done AND en_conf); |
FDCPE_crc6: FDCPE port map (crc(6),crc_D(6),cclk,'0',crc_PRE(6),crc_CE(6));
crc_D(6) <= crc(22) XOR crc_D(6) <= ((EXP23_.EXP) OR (crc(16) AND crc(18) AND crc(21) AND mdata(6).PIN)); crc_PRE(6) <= (NOT init_b AND NOT powerup); crc_CE(6) <= (NOT cfg_done AND en_conf); |
FDCPE_crc7: FDCPE port map (crc(7),crc_D(7),cclk,'0',crc_PRE(7),crc_CE(7));
crc_D(7) <= crc(22) XOR crc_D(7) <= ((crc(16).EXP) OR (EXP14_.EXP) OR (crc(16) AND crc(21) AND mdata(7).PIN AND crc_7_xor0002/crc_7_xor0002_D) OR (crc(16) AND crc(21) AND NOT mdata(7).PIN AND NOT crc_7_xor0002/crc_7_xor0002_D)); crc_PRE(7) <= (NOT init_b AND NOT powerup); crc_CE(7) <= (NOT cfg_done AND en_conf); |
FDCPE_crc8: FDCPE port map (crc(8),crc_D(8),cclk,'0',crc_PRE(8),crc_CE(8));
crc_D(8) <= crc(19) XOR crc_D(8) <= ((maddr_cntr(3).EXP) OR (maddr_cntr(2).EXP) OR (crc(17) AND crc(23) AND crc(0) AND crc_7_xor0001/crc_7_xor0001_D) OR (crc(17) AND crc(23) AND NOT crc(0) AND NOT crc_7_xor0001/crc_7_xor0001_D)); crc_PRE(8) <= (NOT init_b AND NOT powerup); crc_CE(8) <= (NOT cfg_done AND en_conf); |
FDCPE_crc9: FDCPE port map (crc(9),crc_D(9),cclk,'0',crc_PRE(9),crc_CE(9));
crc_D(9) <= crc(22) XOR crc_D(9) <= ((EXP21_.EXP) OR (EXP31_.EXP) OR (crc(18) AND crc(20) AND crc(23) AND crc(1)) OR (crc(18) AND crc(20) AND NOT crc(23) AND NOT crc(1))); crc_PRE(9) <= (NOT init_b AND NOT powerup); crc_CE(9) <= (NOT cfg_done AND en_conf); |
FDCPE_crc10: FDCPE port map (crc(10),crc_D(10),cclk,'0',crc_PRE(10),crc_CE(10));
crc_D(10) <= crc(17) XOR crc_D(10) <= ((loc_add_out_0_OBUF$BUF0.EXP) OR (crc(18) AND crc(23) AND NOT Mxor_crc_10_xor0000__xor0000/Mxor_crc_10_xor0000__xor0000_D) OR (crc(18) AND NOT crc(23) AND Mxor_crc_10_xor0000__xor0000/Mxor_crc_10_xor0000__xor0000_D)); crc_PRE(10) <= (NOT init_b AND NOT powerup); crc_CE(10) <= (NOT cfg_done AND en_conf); |
FDCPE_crc11: FDCPE port map (crc(11),crc_D(11),cclk,'0',crc_PRE(11),crc_CE(11));
crc_D(11) <= crc(16) XOR crc_D(11) <= crc(12).EXP; crc_PRE(11) <= (NOT init_b AND NOT powerup); crc_CE(11) <= (NOT cfg_done AND en_conf); |
FDCPE_crc12: FDCPE port map (crc(12),crc_D(12),cclk,'0',crc_PRE(12),crc_CE(12));
crc_D(12) <= crc(17) XOR crc_D(12) <= crc(13).EXP; crc_PRE(12) <= (NOT init_b AND NOT powerup); crc_CE(12) <= (NOT cfg_done AND en_conf); |
FDCPE_crc13: FDCPE port map (crc(13),crc_D(13),cclk,'0',crc_PRE(13),crc_CE(13));
crc_D(13) <= crc(22) XOR crc_D(13) <= ring_os(3).EXP; crc_PRE(13) <= (NOT init_b AND NOT powerup); crc_CE(13) <= (NOT cfg_done AND en_conf); |
FDCPE_crc14: FDCPE port map (crc(14),crc_D(14),cclk,'0',crc_PRE(14),crc_CE(14));
crc_D(14) <= crc(17) XOR crc_D(14) <= ((EXP32_.EXP) OR (crc(18) AND crc(23) AND crc(6) AND crc_14_xor0001/crc_14_xor0001_D)); crc_PRE(14) <= (NOT init_b AND NOT powerup); crc_CE(14) <= (NOT cfg_done AND en_conf); |
FDCPE_crc15: FDCPE port map (crc(15),crc_D(15),cclk,'0',crc_PRE(15),crc_CE(15));
crc_D(15) <= crc(19) XOR crc_D(15) <= ((crc(6).EXP) OR (EXP24_.EXP) OR (crc(17) AND crc(21) AND crc(7) AND crc_13_xor0001/crc_13_xor0001_D) OR (crc(17) AND crc(21) AND NOT crc(7) AND NOT crc_13_xor0001/crc_13_xor0001_D)); crc_PRE(15) <= (NOT init_b AND NOT powerup); crc_CE(15) <= (NOT cfg_done AND en_conf); |
FDCPE_crc16: FDCPE port map (crc(16),crc_D(16),cclk,'0',crc_PRE(16),crc_CE(16));
crc_D(16) <= crc(19) XOR crc_D(16) <= ((w_data(6)/w_data(6)_TRST.EXP) OR (crc(20) AND crc(8) AND NOT crc_20_xor0001/crc_20_xor0001_D)); crc_PRE(16) <= (NOT init_b AND NOT powerup); crc_CE(16) <= (NOT cfg_done AND en_conf); |
FTCPE_crc17: FTCPE port map (crc(17),crc_T(17),cclk,'0',crc_PRE(17),crc_CE(17));
crc_T(17) <= crc(16) XOR crc_T(17) <= ((loc_add_out_2_OBUF$BUF0.EXP) OR (loc_add_out_1_OBUF$BUF0.EXP) OR (crc(18) AND crc(23) AND NOT crc(9)) OR (crc(18) AND NOT crc(23) AND crc(9))); crc_PRE(17) <= (NOT init_b AND NOT powerup); crc_CE(17) <= (NOT cfg_done AND en_conf); |
FDCPE_crc18: FDCPE port map (crc(18),crc_D(18),cclk,'0',crc_PRE(18),crc_CE(18));
crc_D(18) <= crc(16) XOR crc_D(18) <= ((cclkp_OBUF.EXP) OR (crc(20) AND crc(21) AND NOT crc(10)) OR (crc(20) AND NOT crc(21) AND crc(10))); crc_PRE(18) <= (NOT init_b AND NOT powerup); crc_CE(18) <= (NOT cfg_done AND en_conf); |
FDCPE_crc19: FDCPE port map (crc(19),crc_D(19),cclk,'0',crc_PRE(19),crc_CE(19));
crc_D(19) <= crc(22) XOR crc_D(19) <= ((crc(4).EXP) OR (crc(17) AND crc(21) AND NOT crc(11)) OR (crc(17) AND NOT crc(21) AND crc(11))); crc_PRE(19) <= (NOT init_b AND NOT powerup); crc_CE(19) <= (NOT cfg_done AND en_conf); |
FDCPE_crc20: FDCPE port map (crc(20),crc_D(20),cclk,'0',crc_PRE(20),crc_CE(20));
crc_D(20) <= crc(22) XOR crc_D(20) <= loc_add_out_3_OBUF$BUF0.EXP; crc_PRE(20) <= (NOT init_b AND NOT powerup); crc_CE(20) <= (NOT cfg_done AND en_conf); |
FDCPE_crc21: FDCPE port map (crc(21),crc_D(21),cclk,'0',crc_PRE(21),crc_CE(21));
crc_D(21) <= crc(19) XOR crc_D(21) <= ((crc(23) AND crc(13)) OR (NOT crc(23) AND NOT crc(13))); crc_PRE(21) <= (NOT init_b AND NOT powerup); crc_CE(21) <= (NOT cfg_done AND en_conf); |
FDCPE_crc22: FDCPE port map (crc(22),crc_D(22),cclk,'0',crc_PRE(22),crc_CE(22));
crc_D(22) <= crc(20) XOR crc_D(22) <= crc(14); crc_PRE(22) <= (NOT init_b AND NOT powerup); crc_CE(22) <= (NOT cfg_done AND en_conf); |
FDCPE_crc23: FDCPE port map (crc(23),crc_D(23),cclk,'0',crc_PRE(23),crc_CE(23));
crc_D(23) <= crc(16) XOR crc_D(23) <= ((crc(20).EXP) OR (crc(17) AND crc(18) AND NOT Mxor_crc_23_xor0000__xor0000/Mxor_crc_23_xor0000__xor0000_D) OR (crc(17) AND NOT crc(18) AND Mxor_crc_23_xor0000__xor0000/Mxor_crc_23_xor0000__xor0000_D)); crc_PRE(23) <= (NOT init_b AND NOT powerup); crc_CE(23) <= (NOT cfg_done AND en_conf); |
crc_0_xor0001/crc_0_xor0001_D <= NOT (crc(19)
XOR crc_0_xor0001/crc_0_xor0001_D <= NOT (((crc(16) AND crc(20)) OR (NOT crc(16) AND NOT crc(20)))); |
crc_13_xor0001/crc_13_xor0001_D <= crc(22)
XOR crc_13_xor0001/crc_13_xor0001_D <= crc(18); |
crc_14_xor0001/crc_14_xor0001_D <= NOT (crc(16)
XOR crc_14_xor0001/crc_14_xor0001_D <= NOT (((crc(20) AND crc(21)) OR (NOT crc(20) AND NOT crc(21)))); |
crc_20_xor0001/crc_20_xor0001_D <= NOT (crc(22)
XOR crc_20_xor0001/crc_20_xor0001_D <= NOT (((crc(18) AND crc(23)) OR (NOT crc(18) AND NOT crc(23)))); |
crc_7_xor0001/crc_7_xor0001_D <= crc(22)
XOR crc_7_xor0001/crc_7_xor0001_D <= crc(21); |
crc_7_xor0002/crc_7_xor0002_D <= NOT (crc(18)
XOR crc_7_xor0002/crc_7_xor0002_D <= NOT (((crc(20) AND crc(23)) OR (NOT crc(20) AND NOT crc(23)))); |
cs_b <= NOT (((NOT loc_cs AND cfg_done)
OR (NOT cfg_done AND init_b AND en_conf))); |
FTCPE_div0: FTCPE port map (div(0),'1',cclk_fb,div_CLR(0),'0');
div_CLR(0) <= (NOT init_b AND NOT powerup); |
FTCPE_div1: FTCPE port map (div(1),'1',NOT div(0),div_CLR(1),'0');
div_CLR(1) <= (NOT init_b AND NOT powerup); |
FTCPE_div2: FTCPE port map (div(2),'1',NOT div(1),div_CLR(2),'0');
div_CLR(2) <= (NOT init_b AND NOT powerup); |
FTCPE_div3: FTCPE port map (div(3),'1',NOT div(2),div_CLR(3),'0');
div_CLR(3) <= (NOT init_b AND NOT powerup); |
FTCPE_div4: FTCPE port map (div(4),'1',NOT div(3),div_CLR(4),'0');
div_CLR(4) <= (NOT init_b AND NOT powerup); |
FTCPE_en_conf: FTCPE port map (en_conf,en_conf_T,cclk,'0','0');
en_conf_T <= (maddr(0) AND maddr(15) AND maddr(16) AND maddr(17) AND maddr(1) AND maddr(2) AND maddr(3) AND maddr(4) AND maddr(5) AND maddr(6) AND maddr(8) AND maddr(10) AND maddr(11) AND maddr(12) AND maddr(13) AND maddr(14) AND maddr(7) AND maddr(9) AND NOT en_conf); |
FTCPE_en_loc_bus: FTCPE port map (en_loc_bus,en_loc_bus_T,cclk,'0','0');
en_loc_bus_T <= ((cfg_done AND NOT en_loc_bus) OR (maddr(15) AND maddr(16) AND maddr(17) AND en_conf AND NOT en_loc_bus)); |
loc_add_out(0) <= loc_add(0); |
loc_add_out(1) <= loc_add(1); |
loc_add_out(2) <= loc_add(2); |
loc_add_out(3) <= loc_add(3); |
loc_add_out(4) <= loc_add(4); |
loc_add_out(5) <= loc_add(5); |
loc_add_out(6) <= loc_add(6); |
loc_bus_I(0) <= NOT (((EXP26_.EXP)
OR (NOT loc_add(6) AND NOT mdata(0).PIN) OR (NOT maddr(8) AND loc_add(6) AND loc_add(5) AND NOT loc_add(1) AND loc_add(0)) OR (NOT crc(8) AND loc_add(6) AND NOT loc_add(5) AND NOT loc_add(1) AND loc_add(0)))); loc_bus(0) <= loc_bus_I(0) when loc_bus_OE(0) = '1' else 'Z'; loc_bus_OE(0) <= (loc_rw AND NOT loc_cs AND en_loc_bus); |
loc_bus_I(1) <= ((EXP27_.EXP)
OR (mdata(1).PIN AND NOT loc_add(6)) OR (maddr(1) AND loc_add(6) AND loc_add(5) AND NOT loc_add(1) AND NOT loc_add(0)) OR (crc(17) AND loc_add(6) AND NOT loc_add(5) AND loc_add(1) AND NOT loc_add(0)) OR (crc(1) AND loc_add(6) AND NOT loc_add(5) AND NOT loc_add(1) AND NOT loc_add(0))); loc_bus(1) <= loc_bus_I(1) when loc_bus_OE(1) = '1' else 'Z'; loc_bus_OE(1) <= (loc_rw AND NOT loc_cs AND en_loc_bus); |
loc_bus_I(2) <= ((EXP35_.EXP)
OR (EXP36_.EXP) OR (mdata(2).PIN AND NOT loc_add(6)) OR (maddr(2) AND loc_add(6) AND loc_add(5) AND NOT loc_add(1) AND NOT loc_add(0)) OR (crc(10) AND loc_add(6) AND NOT loc_add(5) AND NOT loc_add(1) AND loc_add(0)) OR (crc(2) AND loc_add(6) AND NOT loc_add(5) AND NOT loc_add(1) AND NOT loc_add(0))); loc_bus(2) <= loc_bus_I(2) when loc_bus_OE(2) = '1' else 'Z'; loc_bus_OE(2) <= (loc_rw AND NOT loc_cs AND en_loc_bus); |
loc_bus_I(3) <= ((EXP37_.EXP)
OR (EXP38_.EXP) OR (NOT loc_add(6) AND mdata(3).PIN) OR (maddr(3) AND loc_add(6) AND loc_add(5) AND NOT loc_add(1) AND NOT loc_add(0)) OR (crc(11) AND loc_add(6) AND NOT loc_add(5) AND NOT loc_add(1) AND loc_add(0)) OR (crc(3) AND loc_add(6) AND NOT loc_add(5) AND NOT loc_add(1) AND NOT loc_add(0))); loc_bus(3) <= loc_bus_I(3) when loc_bus_OE(3) = '1' else 'Z'; loc_bus_OE(3) <= (loc_rw AND NOT loc_cs AND en_loc_bus); |
loc_bus_I(4) <= ((EXP39_.EXP)
OR (EXP40_.EXP) OR (NOT loc_add(6) AND mdata(4).PIN) OR (maddr(4) AND loc_add(6) AND loc_add(5) AND NOT loc_add(1) AND NOT loc_add(0)) OR (crc(12) AND loc_add(6) AND NOT loc_add(5) AND NOT loc_add(1) AND loc_add(0)) OR (crc(4) AND loc_add(6) AND NOT loc_add(5) AND NOT loc_add(1) AND NOT loc_add(0))); loc_bus(4) <= loc_bus_I(4) when loc_bus_OE(4) = '1' else 'Z'; loc_bus_OE(4) <= (loc_rw AND NOT loc_cs AND en_loc_bus); |
loc_bus_I(5) <= ((EXP41_.EXP)
OR (spare5_OBUF.EXP) OR (NOT loc_add(6) AND mdata(5).PIN) OR (maddr(5) AND loc_add(6) AND loc_add(5) AND NOT loc_add(1) AND NOT loc_add(0)) OR (crc(13) AND loc_add(6) AND NOT loc_add(5) AND NOT loc_add(1) AND loc_add(0)) OR (crc(5) AND loc_add(6) AND NOT loc_add(5) AND NOT loc_add(1) AND NOT loc_add(0))); loc_bus(5) <= loc_bus_I(5) when loc_bus_OE(5) = '1' else 'Z'; loc_bus_OE(5) <= (loc_rw AND NOT loc_cs AND en_loc_bus); |
loc_bus_I(6) <= ((EXP42_.EXP)
OR (EXP43_.EXP) OR (NOT loc_add(6) AND mdata(6).PIN) OR (maddr(6) AND loc_add(6) AND loc_add(5) AND NOT loc_add(1) AND NOT loc_add(0)) OR (crc(14) AND loc_add(6) AND NOT loc_add(5) AND NOT loc_add(1) AND loc_add(0)) OR (crc(6) AND loc_add(6) AND NOT loc_add(5) AND NOT loc_add(1) AND NOT loc_add(0))); loc_bus(6) <= loc_bus_I(6) when loc_bus_OE(6) = '1' else 'Z'; loc_bus_OE(6) <= (loc_rw AND NOT loc_cs AND en_loc_bus); |
loc_bus_I(7) <= ((EXP44_.EXP)
OR (EXP45_.EXP) OR (NOT loc_add(6) AND mdata(7).PIN) OR (maddr(7) AND loc_add(6) AND loc_add(5) AND NOT loc_add(1) AND NOT loc_add(0)) OR (crc(15) AND loc_add(6) AND NOT loc_add(5) AND NOT loc_add(1) AND loc_add(0)) OR (crc(7) AND loc_add(6) AND NOT loc_add(5) AND NOT loc_add(1) AND NOT loc_add(0))); loc_bus(7) <= loc_bus_I(7) when loc_bus_OE(7) = '1' else 'Z'; loc_bus_OE(7) <= (loc_rw AND NOT loc_cs AND en_loc_bus); |
FDCPE_loc_mode: FDCPE port map (loc_mode,loc_bus(0).PIN,NOT loc_cs,'0','0',loc_mode_CE);
loc_mode_CE <= (NOT loc_rw AND loc_add(6) AND NOT loc_add(5) AND NOT loc_add(4) AND NOT loc_add(3) AND NOT loc_add(2) AND loc_add(1) AND loc_add(0) AND en_loc_bus); |
FTCPE_maddr0: FTCPE port map (maddr(0),maddr_T(0),cclk,maddr_CLR(0),'0');
maddr_T(0) <= ((NOT cfg_done) OR (crc(14).EXP) OR (NOT ctrl_in(1) AND NOT wr_maddr) OR (maddr(0) AND NOT mdata(0) AND wr_maddr AND NOT sel_byte(0) AND NOT sel_byte(1)) OR (NOT maddr(0) AND mdata(0) AND wr_maddr AND NOT sel_byte(0) AND NOT sel_byte(1))); maddr_CLR(0) <= (NOT init_b AND NOT powerup); |
FTCPE_maddr1: FTCPE port map (maddr(1),maddr_T(1),cclk,maddr_CLR(1),'0');
maddr_T(1) <= ((EXP34_.EXP) OR (maddr(0) AND NOT cfg_done)); maddr_CLR(1) <= (NOT init_b AND NOT powerup); |
FTCPE_maddr2: FTCPE port map (maddr(2),maddr_T(2),cclk,maddr_CLR(2),'0');
maddr_T(2) <= ((maddr_cntr(1).EXP) OR (maddr(0) AND maddr(1) AND NOT cfg_done) OR (maddr(0) AND maddr(1) AND NOT ctrl_in(1) AND NOT wr_maddr)); maddr_CLR(2) <= (NOT init_b AND NOT powerup); |
FTCPE_maddr3: FTCPE port map (maddr(3),EXP33_.EXP,cclk,maddr_CLR(3),'0');
maddr_CLR(3) <= (NOT init_b AND NOT powerup); |
FTCPE_maddr4: FTCPE port map (maddr(4),maddr_T(4),cclk,maddr_CLR(4),'0');
maddr_T(4) <= ((EXP15_.EXP) OR (maddr(0) AND maddr(1) AND maddr(2) AND maddr(3) AND NOT cfg_done) OR (maddr(0) AND maddr(1) AND maddr(2) AND maddr(3) AND NOT ctrl_in(1) AND NOT wr_maddr) OR (maddr(4) AND NOT mdata(4) AND cfg_done AND wr_maddr AND NOT sel_byte(0) AND NOT sel_byte(1)) OR (NOT maddr(4) AND mdata(4) AND cfg_done AND wr_maddr AND NOT sel_byte(0) AND NOT sel_byte(1))); maddr_CLR(4) <= (NOT init_b AND NOT powerup); |
FTCPE_maddr5: FTCPE port map (maddr(5),maddr_T(5),cclk,maddr_CLR(5),'0');
maddr_T(5) <= ((EXP16_.EXP) OR (maddr(0) AND maddr(1) AND maddr(2) AND maddr(3) AND maddr(4) AND NOT cfg_done) OR (NOT maddr(5) AND mdata(5) AND cfg_done AND wr_maddr AND NOT sel_byte(0) AND NOT sel_byte(1)) OR (maddr(0) AND maddr(1) AND maddr(2) AND maddr(3) AND maddr(4) AND NOT ctrl_in(1) AND NOT wr_maddr)); maddr_CLR(5) <= (NOT init_b AND NOT powerup); |
FTCPE_maddr6: FTCPE port map (maddr(6),maddr_T(6),cclk,maddr_CLR(6),'0');
maddr_T(6) <= ((maddr_cntr(5).EXP) OR (maddr(6) AND NOT mdata(6) AND cfg_done AND wr_maddr AND NOT sel_byte(0) AND NOT sel_byte(1)) OR (NOT maddr(6) AND mdata(6) AND cfg_done AND wr_maddr AND NOT sel_byte(0) AND NOT sel_byte(1)) OR (maddr(0) AND maddr(1) AND maddr(2) AND maddr(3) AND maddr(4) AND maddr(5) AND NOT cfg_done) OR (maddr(0) AND maddr(1) AND maddr(2) AND maddr(3) AND maddr(4) AND maddr(5) AND NOT ctrl_in(1) AND NOT wr_maddr)); maddr_CLR(6) <= (NOT init_b AND NOT powerup); |
FTCPE_maddr7: FTCPE port map (maddr(7),maddr_T(7),cclk,maddr_CLR(7),'0');
maddr_T(7) <= ((EXP17_.EXP) OR (maddr(7) AND NOT mdata(7) AND cfg_done AND wr_maddr AND NOT sel_byte(0) AND NOT sel_byte(1)) OR (NOT maddr(7) AND mdata(7) AND cfg_done AND wr_maddr AND NOT sel_byte(0) AND NOT sel_byte(1)) OR (maddr(0) AND maddr(1) AND maddr(2) AND maddr(3) AND maddr(4) AND maddr(5) AND maddr(6) AND NOT cfg_done) OR (maddr(0) AND maddr(1) AND maddr(2) AND maddr(3) AND maddr(4) AND maddr(5) AND maddr(6) AND NOT ctrl_in(1) AND NOT wr_maddr)); maddr_CLR(7) <= (NOT init_b AND NOT powerup); |
FTCPE_maddr8: FTCPE port map (maddr(8),maddr_T(8),cclk,maddr_CLR(8),'0');
maddr_T(8) <= ((maddr_cntr(13).EXP) OR (maddr(8) AND NOT mdata(0) AND cfg_done AND wr_maddr AND sel_byte(0)) OR (NOT maddr(8) AND mdata(0) AND cfg_done AND wr_maddr AND sel_byte(0) AND NOT sel_byte(1)) OR (maddr(0) AND maddr(1) AND maddr(2) AND maddr(3) AND maddr(4) AND maddr(5) AND maddr(6) AND maddr(7) AND NOT cfg_done) OR (maddr(0) AND maddr(1) AND maddr(2) AND maddr(3) AND maddr(4) AND maddr(5) AND maddr(6) AND maddr(7) AND NOT ctrl_in(1) AND NOT wr_maddr)); maddr_CLR(8) <= (NOT init_b AND NOT powerup); |
FTCPE_maddr9: FTCPE port map (maddr(9),maddr_T(9),cclk,maddr_CLR(9),'0');
maddr_T(9) <= ((powerup.EXP) OR (maddr(9) AND NOT mdata(1) AND cfg_done AND wr_maddr AND sel_byte(0)) OR (NOT maddr(9) AND mdata(1) AND cfg_done AND wr_maddr AND sel_byte(0) AND NOT sel_byte(1)) OR (maddr(0) AND maddr(1) AND maddr(2) AND maddr(3) AND maddr(4) AND maddr(5) AND maddr(6) AND maddr(8) AND maddr(7) AND NOT cfg_done) OR (maddr(0) AND maddr(1) AND maddr(2) AND maddr(3) AND maddr(4) AND maddr(5) AND maddr(6) AND maddr(8) AND maddr(7) AND NOT ctrl_in(1) AND NOT wr_maddr)); maddr_CLR(9) <= (NOT init_b AND NOT powerup); |
FTCPE_maddr10: FTCPE port map (maddr(10),maddr_T(10),cclk,maddr_CLR(10),'0');
maddr_T(10) <= ((mce_b_OBUF.EXP) OR (maddr(10) AND NOT mdata(2) AND cfg_done AND wr_maddr AND sel_byte(0)) OR (NOT maddr(10) AND mdata(2) AND cfg_done AND wr_maddr AND sel_byte(0) AND NOT sel_byte(1)) OR (maddr(0) AND maddr(1) AND maddr(2) AND maddr(3) AND maddr(4) AND maddr(5) AND maddr(6) AND maddr(8) AND maddr(7) AND maddr(9) AND NOT cfg_done) OR (maddr(0) AND maddr(1) AND maddr(2) AND maddr(3) AND maddr(4) AND maddr(5) AND maddr(6) AND maddr(8) AND maddr(7) AND maddr(9) AND NOT ctrl_in(1) AND NOT wr_maddr)); maddr_CLR(10) <= (NOT init_b AND NOT powerup); |
FTCPE_maddr11: FTCPE port map (maddr(11),maddr_T(11),cclk,maddr_CLR(11),'0');
maddr_T(11) <= ((en_conf.EXP) OR (maddr(11) AND NOT mdata(3) AND cfg_done AND wr_maddr AND sel_byte(0)) OR (NOT maddr(11) AND mdata(3) AND cfg_done AND wr_maddr AND sel_byte(0) AND NOT sel_byte(1)) OR (maddr(0) AND maddr(1) AND maddr(2) AND maddr(3) AND maddr(4) AND maddr(5) AND maddr(6) AND maddr(8) AND maddr(10) AND maddr(7) AND maddr(9) AND NOT cfg_done) OR (maddr(0) AND maddr(1) AND maddr(2) AND maddr(3) AND maddr(4) AND maddr(5) AND maddr(6) AND maddr(8) AND maddr(10) AND maddr(7) AND maddr(9) AND NOT ctrl_in(1) AND NOT wr_maddr)); maddr_CLR(11) <= (NOT init_b AND NOT powerup); |
FTCPE_maddr12: FTCPE port map (maddr(12),maddr_T(12),cclk,maddr_CLR(12),'0');
maddr_T(12) <= ((EXP18_.EXP) OR (maddr(12) AND NOT mdata(4) AND cfg_done AND wr_maddr AND sel_byte(0)) OR (NOT maddr(12) AND mdata(4) AND cfg_done AND wr_maddr AND sel_byte(0) AND NOT sel_byte(1)) OR (maddr(0) AND maddr(1) AND maddr(2) AND maddr(3) AND maddr(4) AND maddr(5) AND maddr(6) AND maddr(8) AND maddr(10) AND maddr(11) AND maddr(7) AND maddr(9) AND NOT cfg_done) OR (maddr(0) AND maddr(1) AND maddr(2) AND maddr(3) AND maddr(4) AND maddr(5) AND maddr(6) AND maddr(8) AND maddr(10) AND maddr(11) AND maddr(7) AND maddr(9) AND NOT ctrl_in(1) AND NOT wr_maddr)); maddr_CLR(12) <= (NOT init_b AND NOT powerup); |
FTCPE_maddr13: FTCPE port map (maddr(13),maddr_T(13),cclk,maddr_CLR(13),'0');
maddr_T(13) <= ((EXP11_.EXP) OR (NOT maddr(13) AND mdata(5) AND cfg_done AND wr_maddr AND sel_byte(0) AND NOT sel_byte(1)) OR (maddr(0) AND maddr(1) AND maddr(2) AND maddr(3) AND maddr(4) AND maddr(5) AND maddr(6) AND maddr(8) AND maddr(10) AND maddr(11) AND maddr(12) AND maddr(7) AND maddr(9) AND NOT cfg_done) OR (maddr(0) AND maddr(1) AND maddr(2) AND maddr(3) AND maddr(4) AND maddr(5) AND maddr(6) AND maddr(8) AND maddr(10) AND maddr(11) AND maddr(12) AND maddr(7) AND maddr(9) AND NOT ctrl_in(1) AND NOT wr_maddr)); maddr_CLR(13) <= (NOT init_b AND NOT powerup); |
FTCPE_maddr14: FTCPE port map (maddr(14),maddr_T(14),cclk,maddr_CLR(14),'0');
maddr_T(14) <= ((EXP10_.EXP) OR (maddr(14) AND NOT mdata(6) AND cfg_done AND wr_maddr AND sel_byte(0)) OR (NOT maddr(14) AND mdata(6) AND cfg_done AND wr_maddr AND sel_byte(0) AND NOT sel_byte(1)) OR (maddr(0) AND maddr(1) AND maddr(2) AND maddr(3) AND maddr(4) AND maddr(5) AND maddr(6) AND maddr(8) AND maddr(10) AND maddr(11) AND maddr(12) AND maddr(13) AND maddr(7) AND maddr(9) AND NOT cfg_done) OR (maddr(0) AND maddr(1) AND maddr(2) AND maddr(3) AND maddr(4) AND maddr(5) AND maddr(6) AND maddr(8) AND maddr(10) AND maddr(11) AND maddr(12) AND maddr(13) AND maddr(7) AND maddr(9) AND NOT ctrl_in(1) AND NOT wr_maddr)); maddr_CLR(14) <= (NOT init_b AND NOT powerup); |
FTCPE_maddr15: FTCPE port map (maddr(15),maddr_T(15),cclk,maddr_CLR(15),'0');
maddr_T(15) <= ((maddr_cntr(16).EXP) OR (maddr(15) AND NOT mdata(7) AND cfg_done AND wr_maddr AND sel_byte(0)) OR (NOT maddr(15) AND mdata(7) AND cfg_done AND wr_maddr AND sel_byte(0) AND NOT sel_byte(1)) OR (maddr(0) AND maddr(1) AND maddr(2) AND maddr(3) AND maddr(4) AND maddr(5) AND maddr(6) AND maddr(8) AND maddr(10) AND maddr(11) AND maddr(12) AND maddr(13) AND maddr(14) AND maddr(7) AND maddr(9) AND NOT cfg_done) OR (maddr(0) AND maddr(1) AND maddr(2) AND maddr(3) AND maddr(4) AND maddr(5) AND maddr(6) AND maddr(8) AND maddr(10) AND maddr(11) AND maddr(12) AND maddr(13) AND maddr(14) AND maddr(7) AND maddr(9) AND NOT ctrl_in(1) AND NOT wr_maddr)); maddr_CLR(15) <= (NOT init_b AND NOT powerup); |
FTCPE_maddr16: FTCPE port map (maddr(16),maddr_T(16),cclk,maddr_CLR(16),'0');
maddr_T(16) <= ((EXP19_.EXP) OR (NOT maddr(16) AND mdata(0) AND cfg_done AND wr_maddr AND NOT sel_byte(0) AND sel_byte(1)) OR (maddr(0) AND maddr(15) AND maddr(1) AND maddr(2) AND maddr(3) AND maddr(4) AND maddr(5) AND maddr(6) AND maddr(8) AND maddr(10) AND maddr(11) AND maddr(12) AND maddr(13) AND maddr(14) AND maddr(7) AND maddr(9) AND NOT cfg_done) OR (maddr(0) AND maddr(15) AND maddr(1) AND maddr(2) AND maddr(3) AND maddr(4) AND maddr(5) AND maddr(6) AND maddr(8) AND maddr(10) AND maddr(11) AND maddr(12) AND maddr(13) AND maddr(14) AND maddr(7) AND maddr(9) AND NOT ctrl_in(1) AND NOT wr_maddr)); maddr_CLR(16) <= (NOT init_b AND NOT powerup); |
FTCPE_maddr17: FTCPE port map (maddr(17),maddr_T(17),cclk,maddr_CLR(17),'0');
maddr_T(17) <= ((EXP20_.EXP) OR (maddr(17) AND NOT mdata(1) AND cfg_done AND wr_maddr AND sel_byte(1)) OR (NOT maddr(17) AND mdata(1) AND cfg_done AND wr_maddr AND NOT sel_byte(0) AND sel_byte(1)) OR (maddr(0) AND maddr(15) AND maddr(16) AND maddr(1) AND maddr(2) AND maddr(3) AND maddr(4) AND maddr(5) AND maddr(6) AND maddr(8) AND maddr(10) AND maddr(11) AND maddr(12) AND maddr(13) AND maddr(14) AND maddr(7) AND maddr(9) AND NOT cfg_done) OR (maddr(0) AND maddr(15) AND maddr(16) AND maddr(1) AND maddr(2) AND maddr(3) AND maddr(4) AND maddr(5) AND maddr(6) AND maddr(8) AND maddr(10) AND maddr(11) AND maddr(12) AND maddr(13) AND maddr(14) AND maddr(7) AND maddr(9) AND NOT ctrl_in(1) AND NOT wr_maddr)); maddr_CLR(17) <= (NOT init_b AND NOT powerup); |
maddr(18) <= '0'; |
mce_b <= NOT (((NOT ctrl_in(0))
OR (NOT cfg_done AND NOT loc_mode) OR (NOT loc_cs AND NOT loc_add(6) AND loc_add(5) AND NOT loc_add(4) AND NOT loc_add(3) AND NOT loc_add(2) AND NOT loc_add(1) AND NOT loc_add(0) AND ctrl_in(1)))); |
FDCPE_mdata0: FDCPE port map (mdata_I(0),loc_bus(0).PIN,NOT loc_cs,'0','0');
mdata(0) <= mdata_I(0) when mdata_OE(0) = '1' else 'Z'; mdata_OE(0) <= w_data(6)/w_data(6)_TRST; |
FDCPE_mdata1: FDCPE port map (mdata_I(1),loc_bus(1).PIN,NOT loc_cs,'0','0');
mdata(1) <= mdata_I(1) when mdata_OE(1) = '1' else 'Z'; mdata_OE(1) <= w_data(6)/w_data(6)_TRST; |
FDCPE_mdata2: FDCPE port map (mdata_I(2),loc_bus(2).PIN,NOT loc_cs,'0','0');
mdata(2) <= mdata_I(2) when mdata_OE(2) = '1' else 'Z'; mdata_OE(2) <= w_data(6)/w_data(6)_TRST; |
FDCPE_mdata3: FDCPE port map (mdata_I(3),loc_bus(3).PIN,NOT loc_cs,'0','0');
mdata(3) <= mdata_I(3) when mdata_OE(3) = '1' else 'Z'; mdata_OE(3) <= w_data(6)/w_data(6)_TRST; |
FDCPE_mdata4: FDCPE port map (mdata_I(4),loc_bus(4).PIN,NOT loc_cs,'0','0');
mdata(4) <= mdata_I(4) when mdata_OE(4) = '1' else 'Z'; mdata_OE(4) <= w_data(6)/w_data(6)_TRST; |
FDCPE_mdata5: FDCPE port map (mdata_I(5),loc_bus(5).PIN,NOT loc_cs,'0','0');
mdata(5) <= mdata_I(5) when mdata_OE(5) = '1' else 'Z'; mdata_OE(5) <= w_data(6)/w_data(6)_TRST; |
FDCPE_mdata6: FDCPE port map (mdata_I(6),loc_bus(6).PIN,NOT loc_cs,'0','0');
mdata(6) <= mdata_I(6) when mdata_OE(6) = '1' else 'Z'; mdata_OE(6) <= w_data(6)/w_data(6)_TRST; |
FDCPE_mdata7: FDCPE port map (mdata_I(7),loc_bus(7).PIN,NOT loc_cs,'0','0');
mdata(7) <= mdata_I(7) when mdata_OE(7) = '1' else 'Z'; mdata_OE(7) <= w_data(6)/w_data(6)_TRST; |
moe_b <= ((NOT loc_rw AND cfg_done)
OR (cfg_done AND NOT ctrl_in(1))); |
mwe_b <= ((NOT cfg_done)
OR (loc_rw AND ctrl_in(1))); |
FDCPE_powerup: FDCPE port map (powerup,powerup_D,cclk,'0','0');
powerup_D <= (NOT maddr(17) AND powerup); |
FDCPE_prog: FDCPE port map (prog,loc_bus(1).PIN,NOT loc_cs,'0','0',prog_CE);
prog_CE <= (NOT loc_rw AND loc_add(6) AND NOT loc_add(5) AND NOT loc_add(4) AND NOT loc_add(3) AND NOT loc_add(2) AND loc_add(1) AND loc_add(0) AND en_loc_bus); |
prog_b_I <= '0';
prog_b <= prog_b_I when prog_b_OE = '1' else 'Z'; prog_b_OE <= NOT ((NOT prog AND NOT powerup)); |
rdwr_b <= (loc_rw AND cfg_done); |
ring_os(0) <= ((cfg_done)
OR (loc_mode) OR (NOT cclk_fb) OR (NOT init_b AND NOT powerup)); |
ring_os(1) <= ring_os(0); |
ring_os(2) <= ring_os(1); |
FDCPE_sel_byte0: FDCPE port map (sel_byte(0),loc_add(0),NOT loc_cs,'0','0'); |
FDCPE_sel_byte1: FDCPE port map (sel_byte(1),loc_add(1),NOT loc_cs,'0','0'); |
spare5 <= (loc_cs AND cfg_done); |
w_data(6)/w_data(6)_TRST <= ((done AND NOT loc_rw AND ctrl_in(1))
OR (NOT done AND NOT loc_rw AND loc_mode)); |
FDCPE_wr_maddr: FDCPE port map (wr_maddr,wr_maddr_D,NOT loc_cs,NOT ctrl_in(1),'0');
wr_maddr_D <= (NOT loc_rw AND loc_add(6) AND loc_add(5) AND NOT loc_add(4) AND NOT loc_add(3) AND NOT loc_add(2) AND cfg_done); |
Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); |