********** Mapped Logic ********** |
$OpTx$crc_10_xor0001/crc_10_xor0001_D211__INV$36 <= NOT (crc(16)
XOR $OpTx$crc_10_xor0001/crc_10_xor0001_D211__INV$36 <= NOT (crc(20)); |
$OpTx$crc_10_xor0001/crc_10_xor0001_D214__INV$38 <= NOT (crc(16)
XOR $OpTx$crc_10_xor0001/crc_10_xor0001_D214__INV$38 <= NOT (crc(20)); |
$OpTx$crc_10_xor0003/crc_10_xor0003_D210__INV$35 <= NOT (crc(18)
XOR $OpTx$crc_10_xor0003/crc_10_xor0003_D210__INV$35 <= NOT (crc(23)); |
$OpTx$crc_10_xor0003/crc_10_xor0003_D2_INV$28 <= NOT (crc(18)
XOR $OpTx$crc_10_xor0003/crc_10_xor0003_D2_INV$28 <= NOT (crc(23)); |
$OpTx$crc_12_xor0001/crc_12_xor0001_D2_INV$29 <= NOT (crc(17)
XOR $OpTx$crc_12_xor0001/crc_12_xor0001_D2_INV$29 <= NOT (crc(21)); |
$OpTx$crc_13_xor0001/crc_13_xor0001_D2_INV$30 <= NOT (crc(22)
XOR $OpTx$crc_13_xor0001/crc_13_xor0001_D2_INV$30 <= NOT (crc(18)); |
$OpTx$crc_16_xor0001/crc_16_xor0001_D2_INV$31 <= NOT (crc(19)
XOR $OpTx$crc_16_xor0001/crc_16_xor0001_D2_INV$31 <= NOT (crc(20)); |
$OpTx$crc_17_xor0002/crc_17_xor0002_D213__INV$37 <= NOT (crc(16)
XOR $OpTx$crc_17_xor0002/crc_17_xor0002_D213__INV$37 <= NOT (crc(18)); |
$OpTx$crc_17_xor0002/crc_17_xor0002_D2_INV$32 <= NOT (crc(16)
XOR $OpTx$crc_17_xor0002/crc_17_xor0002_D2_INV$32 <= NOT (crc(18)); |
$OpTx$crc_7_xor0001/crc_7_xor0001_D2_INV$33 <= NOT (crc(22)
XOR $OpTx$crc_7_xor0001/crc_7_xor0001_D2_INV$33 <= NOT (crc(21)); |
$OpTx$mdata_and00004/mdata_and00004_D2_INV$34 <= ((done AND NOT ctrl_in(1))
OR (NOT done AND NOT loc_mode)); |
cclk_fbp <= ring_os(2); |
cclkp <= NOT (((prog)
OR (div(0).EXP) OR (cfg_done AND NOT ctrl_in(0)) OR (ctrl_in(1) AND NOT loc_cs AND cfg_done) OR (NOT cfg_done AND NOT loc_mode AND div(4)))); |
FDCPE_cfg_done: FDCPE port map (cfg_done,'1',cclk,prog,'0',cfg_done_CE);
cfg_done_CE <= (done AND maddr(0) AND maddr(8) AND NOT maddr(15) AND maddr(1) AND NOT maddr(3) AND maddr(5) AND maddr(11) AND maddr(13) AND NOT maddr(4) AND NOT maddr(9) AND maddr(16) AND maddr(2) AND NOT maddr(6) AND maddr(10) AND maddr(12) AND NOT maddr(14) AND maddr(17) AND maddr(7)); |
FDCPE_cfg_fail: FDCPE port map (cfg_fail,cfg_fail_D,cclk,prog,'0',cfg_fail_CE);
cfg_fail_D <= (en_conf AND NOT cfg_done); cfg_fail_CE <= (maddr(0) AND maddr(8) AND maddr(15) AND maddr(1) AND maddr(3) AND maddr(5) AND maddr(11) AND maddr(13) AND maddr(4) AND maddr(9) AND maddr(16) AND maddr(2) AND maddr(6) AND maddr(10) AND maddr(12) AND maddr(14) AND maddr(17) AND maddr(7)); |
FDCPE_crc0: FDCPE port map (crc(0),crc_D(0),cclk,'0',NOT crc_10_or0000/crc_10_or0000_D2__$INT,crc_CE(0));
crc_D(0) <= crc(19) XOR crc_D(0) <= ((w_data(2).EXP) OR (w_data(3).EXP) OR (crc(18) AND mdata(0).PIN AND $OpTx$crc_10_xor0001/crc_10_xor0001_D214__INV$38 AND $OpTx$crc_12_xor0001/crc_12_xor0001_D2_INV$29) OR (crc(18) AND mdata(0).PIN AND NOT $OpTx$crc_10_xor0001/crc_10_xor0001_D214__INV$38 AND NOT $OpTx$crc_12_xor0001/crc_12_xor0001_D2_INV$29)); crc_CE(0) <= (en_conf AND NOT cfg_done); |
FDCPE_crc1: FDCPE port map (crc(1),crc_D(1),cclk,'0',NOT crc_10_or0000/crc_10_or0000_D2__$INT,crc_CE(1));
crc_D(1) <= crc(22) XOR crc_D(1) <= ((crc(21).EXP) OR (crc(16) AND mdata(1).PIN)); crc_CE(1) <= (en_conf AND NOT cfg_done); |
FDCPE_crc2: FDCPE port map (crc(2),crc_D(2),cclk,'0',NOT crc_10_or0000/crc_10_or0000_D2__$INT,crc_CE(2));
crc_D(2) <= crc(17) XOR crc_D(2) <= ((crc(22).EXP) OR (crc(23) AND mdata(2).PIN)); crc_CE(2) <= (en_conf AND NOT cfg_done); |
FDCPE_crc3: FDCPE port map (crc(3),crc_D(3),cclk,'0',NOT crc_10_or0000/crc_10_or0000_D2__$INT,crc_CE(3));
crc_D(3) <= crc(19) XOR crc_D(3) <= ((w_data(0).EXP) OR (EXP13_.EXP) OR (crc(16) AND crc(20) AND mdata(3).PIN AND NOT $OpTx$crc_12_xor0001/crc_12_xor0001_D2_INV$29) OR (crc(16) AND crc(20) AND NOT mdata(3).PIN AND $OpTx$crc_12_xor0001/crc_12_xor0001_D2_INV$29)); crc_CE(3) <= (en_conf AND NOT cfg_done); |
FDCPE_crc4: FDCPE port map (crc(4),crc_D(4),cclk,'0',NOT crc_10_or0000/crc_10_or0000_D2__$INT,crc_CE(4));
crc_D(4) <= crc(22) XOR crc_D(4) <= ((crc(20).EXP) OR (crc(19) AND crc(16) AND NOT mdata(4).PIN) OR (crc(19) AND NOT crc(16) AND mdata(4).PIN)); crc_CE(4) <= (en_conf AND NOT cfg_done); |
FDCPE_crc5: FDCPE port map (crc(5),crc_D(5),cclk,'0',NOT crc_10_or0000/crc_10_or0000_D2__$INT,crc_CE(5));
crc_D(5) <= crc(19) XOR crc_D(5) <= ((loc_add_out_2.EXP) OR (loc_add_out_1.EXP) OR (crc(21) AND crc(23) AND mdata(5).PIN AND NOT $OpTx$crc_17_xor0002/crc_17_xor0002_D2_INV$32) OR (crc(21) AND crc(23) AND NOT mdata(5).PIN AND $OpTx$crc_17_xor0002/crc_17_xor0002_D2_INV$32)); crc_CE(5) <= (en_conf AND NOT cfg_done); |
FDCPE_crc6: FDCPE port map (crc(6),crc_D(6),cclk,'0',NOT crc_10_or0000/crc_10_or0000_D2__$INT,crc_CE(6));
crc_D(6) <= crc(22) XOR crc_D(6) <= ((EXP21_.EXP) OR (r_data(1).EXP) OR (crc(16) AND crc(18) AND crc(21) AND mdata(6).PIN) OR (crc(16) AND crc(18) AND NOT crc(21) AND NOT mdata(6).PIN)); crc_CE(6) <= (en_conf AND NOT cfg_done); |
FDCPE_crc7: FDCPE port map (crc(7),crc_D(7),cclk,'0',NOT crc_10_or0000/crc_10_or0000_D2__$INT,crc_CE(7));
crc_D(7) <= crc(16) XOR crc_D(7) <= ((sel_byte(1).EXP) OR (crc(1).EXP) OR (crc(20) AND mdata(7).PIN AND $OpTx$crc_10_xor0003/crc_10_xor0003_D2_INV$28 AND $OpTx$crc_7_xor0001/crc_7_xor0001_D2_INV$33) OR (crc(20) AND mdata(7).PIN AND NOT $OpTx$crc_10_xor0003/crc_10_xor0003_D2_INV$28 AND NOT $OpTx$crc_7_xor0001/crc_7_xor0001_D2_INV$33)); crc_CE(7) <= (en_conf AND NOT cfg_done); |
FDCPE_crc8: FDCPE port map (crc(8),crc_D(8),cclk,'0',NOT crc_10_or0000/crc_10_or0000_D2__$INT,crc_CE(8));
crc_D(8) <= crc(19) XOR crc_D(8) <= ((crc(9).EXP) OR (EXP19_.EXP) OR (crc(17) AND crc(23) AND crc(0) AND NOT $OpTx$crc_7_xor0001/crc_7_xor0001_D2_INV$33) OR (crc(17) AND crc(23) AND NOT crc(0) AND $OpTx$crc_7_xor0001/crc_7_xor0001_D2_INV$33)); crc_CE(8) <= (en_conf AND NOT cfg_done); |
FDCPE_crc9: FDCPE port map (crc(9),crc_D(9),cclk,'0',NOT crc_10_or0000/crc_10_or0000_D2__$INT,crc_CE(9));
crc_D(9) <= crc(22) XOR crc_D(9) <= ((EXP18_.EXP) OR (crc(18) AND crc(20) AND crc(23) AND crc(1))); crc_CE(9) <= (en_conf AND NOT cfg_done); |
FDCPE_crc10: FDCPE port map (crc(10),crc_D(10),cclk,'0',NOT crc_10_or0000/crc_10_or0000_D2__$INT,crc_CE(10));
crc_D(10) <= crc(16) XOR crc_D(10) <= ((EXP14_.EXP) OR (crc(17) AND crc(20) AND crc(2) AND NOT $OpTx$crc_10_xor0003/crc_10_xor0003_D210__INV$35)); crc_CE(10) <= (en_conf AND NOT cfg_done); |
FDCPE_crc11: FDCPE port map (crc(11),crc_D(11),cclk,'0',NOT crc_10_or0000/crc_10_or0000_D2__$INT,crc_CE(11));
crc_D(11) <= crc(16) XOR crc_D(11) <= ((crc(20) AND crc(3)) OR (NOT crc(20) AND NOT crc(3))); crc_CE(11) <= (en_conf AND NOT cfg_done); |
FDCPE_crc12: FDCPE port map (crc(12),crc_D(12),cclk,'0',NOT crc_10_or0000/crc_10_or0000_D2__$INT,crc_CE(12));
crc_D(12) <= crc(17) XOR crc_D(12) <= ((crc(21) AND crc(4)) OR (NOT crc(21) AND NOT crc(4))); crc_CE(12) <= (en_conf AND NOT cfg_done); |
FDCPE_crc13: FDCPE port map (crc(13),crc_D(13),cclk,'0',NOT crc_10_or0000/crc_10_or0000_D2__$INT,crc_CE(13));
crc_D(13) <= crc(22) XOR crc_D(13) <= ((crc(19).EXP) OR (crc(18) AND crc(5))); crc_CE(13) <= (en_conf AND NOT cfg_done); |
FDCPE_crc14: FDCPE port map (crc(14),crc_D(14),cclk,'0',NOT crc_10_or0000/crc_10_or0000_D2__$INT,crc_CE(14));
crc_D(14) <= crc(17) XOR crc_D(14) <= ((mwe_b_OBUF.EXP) OR (maddr_cntr(17).EXP) OR (crc(21) AND crc(6) AND $OpTx$crc_10_xor0003/crc_10_xor0003_D210__INV$35 AND $OpTx$crc_10_xor0001/crc_10_xor0001_D211__INV$36) OR (crc(21) AND crc(6) AND NOT $OpTx$crc_10_xor0003/crc_10_xor0003_D210__INV$35 AND NOT $OpTx$crc_10_xor0001/crc_10_xor0001_D211__INV$36)); crc_CE(14) <= (en_conf AND NOT cfg_done); |
FDCPE_crc15: FDCPE port map (crc(15),crc_D(15),cclk,'0',NOT crc_10_or0000/crc_10_or0000_D2__$INT,crc_CE(15));
crc_D(15) <= crc(19) XOR crc_D(15) <= ((maddr_cntr(3).EXP) OR (maddr_cntr(2).EXP) OR (crc(17) AND crc(21) AND crc(7) AND NOT $OpTx$crc_13_xor0001/crc_13_xor0001_D2_INV$30) OR (crc(17) AND crc(21) AND NOT crc(7) AND $OpTx$crc_13_xor0001/crc_13_xor0001_D2_INV$30)); crc_CE(15) <= (en_conf AND NOT cfg_done); |
FDCPE_crc16: FDCPE port map (crc(16),crc_D(16),cclk,'0',NOT crc_10_or0000/crc_10_or0000_D2__$INT,crc_CE(16));
crc_D(16) <= crc(22) XOR crc_D(16) <= ((crc(23).EXP) OR (EXP24_.EXP) OR (crc(18) AND crc(23) AND crc(8) AND NOT $OpTx$crc_16_xor0001/crc_16_xor0001_D2_INV$31) OR (crc(18) AND crc(23) AND NOT crc(8) AND $OpTx$crc_16_xor0001/crc_16_xor0001_D2_INV$31)); crc_CE(16) <= (en_conf AND NOT cfg_done); |
FTCPE_crc17: FTCPE port map (crc(17),crc_T(17),cclk,'0',NOT crc_10_or0000/crc_10_or0000_D2__$INT,crc_CE(17));
crc_T(17) <= crc(16) XOR crc_T(17) <= ((loc_mode.EXP) OR (crc(18) AND crc(23) AND NOT crc(9)) OR (crc(18) AND NOT crc(23) AND crc(9))); crc_CE(17) <= (en_conf AND NOT cfg_done); |
FDCPE_crc18: FDCPE port map (crc(18),crc_D(18),cclk,'0',NOT crc_10_or0000/crc_10_or0000_D2__$INT,crc_CE(18));
crc_D(18) <= crc(16) XOR crc_D(18) <= maddr_18_OBUF$BUF0.EXP; crc_CE(18) <= (en_conf AND NOT cfg_done); |
FDCPE_crc19: FDCPE port map (crc(19),crc_D(19),cclk,'0',NOT crc_10_or0000/crc_10_or0000_D2__$INT,crc_CE(19));
crc_D(19) <= crc(22) XOR crc_D(19) <= ((loc_add_out_4.EXP) OR (crc(17) AND crc(21) AND NOT crc(11))); crc_CE(19) <= (en_conf AND NOT cfg_done); |
FDCPE_crc20: FDCPE port map (crc(20),crc_D(20),cclk,'0',NOT crc_10_or0000/crc_10_or0000_D2__$INT,crc_CE(20));
crc_D(20) <= crc(22) XOR crc_D(20) <= loc_add_out_3.EXP; crc_CE(20) <= (en_conf AND NOT cfg_done); |
FDCPE_crc21: FDCPE port map (crc(21),crc_D(21),cclk,'0',NOT crc_10_or0000/crc_10_or0000_D2__$INT,crc_CE(21));
crc_D(21) <= crc(19) XOR crc_D(21) <= ((crc(2).EXP) OR (crc(23) AND crc(13))); crc_CE(21) <= (en_conf AND NOT cfg_done); |
FDCPE_crc22: FDCPE port map (crc(22),crc_D(22),cclk,'0',NOT crc_10_or0000/crc_10_or0000_D2__$INT,crc_CE(22));
crc_D(22) <= crc(20) XOR crc_D(22) <= crc(14); crc_CE(22) <= (en_conf AND NOT cfg_done); |
FDCPE_crc23: FDCPE port map (crc(23),crc_D(23),cclk,'0',NOT crc_10_or0000/crc_10_or0000_D2__$INT,crc_CE(23));
crc_D(23) <= crc(19) XOR crc_D(23) <= ((EXP23_.EXP) OR (crc(17) AND crc(20) AND crc(15) AND NOT $OpTx$crc_17_xor0002/crc_17_xor0002_D213__INV$37)); crc_CE(23) <= (en_conf AND NOT cfg_done); |
crc_10_or0000/crc_10_or0000_D2__$INT <= (NOT prog AND NOT powerup); |
cs_b <= NOT (((NOT loc_cs AND cfg_done)
OR (en_conf AND NOT cfg_done AND init_b))); |
FTCPE_div0: FTCPE port map (div(0),'1',cclk_fb,'0','0'); |
FTCPE_div1: FTCPE port map (div(1),'1',NOT div(0),'0','0'); |
FTCPE_div2: FTCPE port map (div(2),'1',NOT div(1),'0','0'); |
FTCPE_div3: FTCPE port map (div(3),'1',NOT div(2),'0','0'); |
FTCPE_div4: FTCPE port map (div(4),'1',NOT div(3),'0','0'); |
FDCPE_en_conf: FDCPE port map (en_conf,en_conf_D,cclk,en_conf_CLR,en_conf_PRE);
en_conf_D <= ((EXP10_.EXP) OR (EXP11_.EXP) OR (NOT maddr(0) AND en_conf) OR (NOT maddr(1) AND en_conf) OR (NOT maddr(3) AND en_conf)); en_conf_CLR <= (prog AND NOT loc_mode); en_conf_PRE <= (prog AND loc_mode); |
FDCPE_en_loc_bus: FDCPE port map (en_loc_bus,maddr_cntr(7).EXP,cclk,'0','0',NOT en_loc_bus); |
FDCPE_loc_add_out0: FDCPE port map (loc_add_out(0),loc_add(0),NOT loc_cs,'0','0'); |
FDCPE_loc_add_out1: FDCPE port map (loc_add_out(1),loc_add(1),NOT loc_cs,'0','0'); |
FDCPE_loc_add_out2: FDCPE port map (loc_add_out(2),loc_add(2),NOT loc_cs,'0','0'); |
FDCPE_loc_add_out3: FDCPE port map (loc_add_out(3),loc_add(3),NOT loc_cs,'0','0'); |
FDCPE_loc_add_out4: FDCPE port map (loc_add_out(4),loc_add(4),NOT loc_cs,'0','0'); |
FDCPE_loc_add_out5: FDCPE port map (loc_add_out(5),loc_add(5),NOT loc_cs,'0','0'); |
FDCPE_loc_add_out6: FDCPE port map (loc_add_out(6),loc_add(6),NOT loc_cs,'0','0'); |
loc_bus_I(0) <= ((EXP20_.EXP)
OR (NOT loc_add(6) AND mdata(0).PIN) OR (loc_add(5) AND NOT loc_add(1) AND NOT loc_add(0) AND loc_add(6) AND maddr(0)) OR (NOT loc_add(5) AND loc_add(1) AND NOT loc_add(0) AND loc_add(6) AND crc(16)) OR (NOT loc_add(5) AND NOT loc_add(1) AND NOT loc_add(0) AND loc_add(6) AND crc(0))); loc_bus(0) <= loc_bus_I(0) when loc_bus_OE(0) = '1' else 'Z'; loc_bus_OE(0) <= (NOT loc_cs AND loc_rw); |
loc_bus_I(1) <= ((EXP22_.EXP)
OR (NOT loc_add(6) AND mdata(1).PIN) OR (loc_add(5) AND NOT loc_add(1) AND NOT loc_add(0) AND loc_add(6) AND maddr(1)) OR (NOT loc_add(5) AND NOT loc_add(1) AND NOT loc_add(0) AND loc_add(6) AND crc(1))); loc_bus(1) <= loc_bus_I(1) when loc_bus_OE(1) = '1' else 'Z'; loc_bus_OE(1) <= (NOT loc_cs AND loc_rw); |
loc_bus_I(2) <= ((EXP27_.EXP)
OR (EXP28_.EXP) OR (NOT loc_add(6) AND mdata(2).PIN) OR (loc_add(5) AND loc_add(1) AND loc_add(0) AND loc_add(6)) OR (loc_add(5) AND loc_add(0) AND loc_add(6) AND maddr(10)) OR (loc_add(1) AND loc_add(0) AND loc_add(6) AND init_b)); loc_bus(2) <= loc_bus_I(2) when loc_bus_OE(2) = '1' else 'Z'; loc_bus_OE(2) <= (NOT loc_cs AND loc_rw); |
loc_bus_I(3) <= ((EXP29_.EXP)
OR (spare3_OBUF.EXP) OR (NOT loc_add(6) AND mdata(3).PIN) OR (loc_add(5) AND NOT loc_add(1) AND NOT loc_add(0) AND loc_add(6) AND maddr(3)) OR (NOT loc_add(5) AND loc_add(1) AND NOT loc_add(0) AND loc_add(6) AND crc(19)) OR (NOT loc_add(5) AND NOT loc_add(1) AND NOT loc_add(0) AND loc_add(6) AND crc(3))); loc_bus(3) <= loc_bus_I(3) when loc_bus_OE(3) = '1' else 'Z'; loc_bus_OE(3) <= (NOT loc_cs AND loc_rw); |
loc_bus_I(4) <= ((EXP30_.EXP)
OR (EXP31_.EXP) OR (NOT loc_add(6) AND mdata(4).PIN) OR (loc_add(5) AND NOT loc_add(1) AND NOT loc_add(0) AND loc_add(6) AND maddr(4)) OR (NOT loc_add(5) AND loc_add(1) AND NOT loc_add(0) AND loc_add(6) AND crc(20)) OR (NOT loc_add(5) AND NOT loc_add(1) AND NOT loc_add(0) AND loc_add(6) AND crc(4))); loc_bus(4) <= loc_bus_I(4) when loc_bus_OE(4) = '1' else 'Z'; loc_bus_OE(4) <= (NOT loc_cs AND loc_rw); |
loc_bus_I(5) <= ((EXP32_.EXP)
OR (spare5_OBUF.EXP) OR (NOT loc_add(6) AND mdata(5).PIN) OR (loc_add(5) AND NOT loc_add(1) AND NOT loc_add(0) AND loc_add(6) AND maddr(5)) OR (NOT loc_add(5) AND loc_add(1) AND NOT loc_add(0) AND loc_add(6) AND crc(21)) OR (NOT loc_add(5) AND NOT loc_add(1) AND NOT loc_add(0) AND loc_add(6) AND crc(5))); loc_bus(5) <= loc_bus_I(5) when loc_bus_OE(5) = '1' else 'Z'; loc_bus_OE(5) <= (NOT loc_cs AND loc_rw); |
loc_bus_I(6) <= ((EXP33_.EXP)
OR (EXP34_.EXP) OR (NOT loc_add(6) AND mdata(6).PIN) OR (loc_add(5) AND NOT loc_add(1) AND NOT loc_add(0) AND loc_add(6) AND maddr(6)) OR (NOT loc_add(5) AND loc_add(1) AND NOT loc_add(0) AND loc_add(6) AND crc(22)) OR (NOT loc_add(5) AND NOT loc_add(1) AND NOT loc_add(0) AND loc_add(6) AND crc(6))); loc_bus(6) <= loc_bus_I(6) when loc_bus_OE(6) = '1' else 'Z'; loc_bus_OE(6) <= (NOT loc_cs AND loc_rw); |
loc_bus_I(7) <= ((EXP35_.EXP)
OR (EXP36_.EXP) OR (NOT loc_add(6) AND mdata(7).PIN) OR (loc_add(5) AND NOT loc_add(1) AND NOT loc_add(0) AND loc_add(6) AND maddr(7)) OR (NOT loc_add(5) AND loc_add(1) AND NOT loc_add(0) AND loc_add(6) AND crc(23)) OR (NOT loc_add(5) AND NOT loc_add(1) AND NOT loc_add(0) AND loc_add(6) AND crc(7))); loc_bus(7) <= loc_bus_I(7) when loc_bus_OE(7) = '1' else 'Z'; loc_bus_OE(7) <= (NOT loc_cs AND loc_rw); |
FDCPE_loc_mode: FDCPE port map (loc_mode,loc_bus(0).PIN,NOT loc_cs,'0','0',loc_mode_CE);
loc_mode_CE <= (NOT loc_add(5) AND NOT loc_add(4) AND NOT loc_add(3) AND NOT loc_add(2) AND loc_add(1) AND loc_add(0) AND loc_add(6) AND NOT loc_rw AND en_loc_bus); |
FTCPE_maddr0: FTCPE port map (maddr(0),maddr_T(0),cclk,prog,'0');
maddr_T(0) <= ((NOT cfg_done) OR (crc(13).EXP) OR (NOT ctrl_in(1) AND NOT wr_maddr) OR (maddr(0) AND NOT mdata(0) AND wr_maddr AND NOT sel_byte(0) AND NOT sel_byte(1)) OR (NOT maddr(0) AND mdata(0) AND wr_maddr AND NOT sel_byte(0) AND NOT sel_byte(1))); |
FTCPE_maddr1: FTCPE port map (maddr(1),maddr_T(1),cclk,prog,'0');
maddr_T(1) <= ((EXP26_.EXP) OR (maddr(0) AND NOT cfg_done)); |
FTCPE_maddr2: FTCPE port map (maddr(2),maddr_T(2),cclk,prog,'0');
maddr_T(2) <= ((maddr_cntr(1).EXP) OR (maddr(0) AND maddr(1) AND NOT cfg_done) OR (NOT ctrl_in(1) AND maddr(0) AND maddr(1) AND NOT wr_maddr)); |
FTCPE_maddr3: FTCPE port map (maddr(3),EXP25_.EXP,cclk,prog,'0'); |
FTCPE_maddr4: FTCPE port map (maddr(4),maddr_T(4),cclk,prog,'0');
maddr_T(4) <= ((crc(10).EXP) OR (maddr(0) AND maddr(1) AND maddr(3) AND maddr(2) AND NOT cfg_done) OR (maddr(4) AND cfg_done AND wr_maddr AND sel_byte(0) AND sel_byte(1)) OR (NOT ctrl_in(1) AND maddr(0) AND maddr(1) AND maddr(3) AND maddr(2) AND NOT wr_maddr) OR (NOT maddr(4) AND mdata(4) AND cfg_done AND wr_maddr AND NOT sel_byte(0) AND NOT sel_byte(1))); |
FTCPE_maddr5: FTCPE port map (maddr(5),maddr_T(5),cclk,prog,'0');
maddr_T(5) <= ((maddr_cntr(6).EXP) OR (maddr(0) AND maddr(1) AND maddr(3) AND maddr(4) AND maddr(2) AND NOT cfg_done) OR (NOT ctrl_in(1) AND maddr(0) AND maddr(1) AND maddr(3) AND maddr(4) AND maddr(2) AND NOT wr_maddr)); |
FTCPE_maddr6: FTCPE port map (maddr(6),maddr_T(6),cclk,prog,'0');
maddr_T(6) <= ((en_loc_bus.EXP) OR (maddr(0) AND maddr(1) AND maddr(3) AND maddr(5) AND maddr(4) AND maddr(2) AND NOT cfg_done)); |
FTCPE_maddr7: FTCPE port map (maddr(7),maddr_T(7),cclk,prog,'0');
maddr_T(7) <= ((maddr_cntr(12).EXP) OR (maddr(0) AND maddr(1) AND maddr(3) AND maddr(5) AND maddr(4) AND maddr(2) AND maddr(6) AND NOT cfg_done) OR (NOT ctrl_in(1) AND maddr(0) AND maddr(1) AND maddr(3) AND maddr(5) AND maddr(4) AND maddr(2) AND maddr(6) AND NOT wr_maddr)); |
FTCPE_maddr8: FTCPE port map (maddr(8),maddr_T(8),cclk,prog,'0');
maddr_T(8) <= ((maddr_cntr(13).EXP) OR (maddr(8) AND NOT mdata(0) AND cfg_done AND wr_maddr AND sel_byte(0)) OR (NOT maddr(8) AND mdata(0) AND cfg_done AND wr_maddr AND sel_byte(0) AND NOT sel_byte(1)) OR (maddr(0) AND maddr(1) AND maddr(3) AND maddr(5) AND maddr(4) AND maddr(2) AND maddr(6) AND maddr(7) AND NOT cfg_done) OR (NOT ctrl_in(1) AND maddr(0) AND maddr(1) AND maddr(3) AND maddr(5) AND maddr(4) AND maddr(2) AND maddr(6) AND maddr(7) AND NOT wr_maddr)); |
FTCPE_maddr9: FTCPE port map (maddr(9),maddr_T(9),cclk,prog,'0');
maddr_T(9) <= ((maddr_cntr(11).EXP) OR (maddr(9) AND NOT mdata(1) AND cfg_done AND wr_maddr AND sel_byte(0)) OR (NOT maddr(9) AND mdata(1) AND cfg_done AND wr_maddr AND sel_byte(0) AND NOT sel_byte(1)) OR (maddr(0) AND maddr(8) AND maddr(1) AND maddr(3) AND maddr(5) AND maddr(4) AND maddr(2) AND maddr(6) AND maddr(7) AND NOT cfg_done) OR (NOT ctrl_in(1) AND maddr(0) AND maddr(8) AND maddr(1) AND maddr(3) AND maddr(5) AND maddr(4) AND maddr(2) AND maddr(6) AND maddr(7) AND NOT wr_maddr)); |
FTCPE_maddr10: FTCPE port map (maddr(10),maddr_T(10),cclk,prog,'0');
maddr_T(10) <= ((mce_b_OBUF.EXP) OR (maddr(10) AND NOT mdata(2) AND cfg_done AND wr_maddr AND sel_byte(0)) OR (NOT maddr(10) AND mdata(2) AND cfg_done AND wr_maddr AND sel_byte(0) AND NOT sel_byte(1)) OR (maddr(0) AND maddr(8) AND maddr(1) AND maddr(3) AND maddr(5) AND maddr(4) AND maddr(9) AND maddr(2) AND maddr(6) AND maddr(7) AND NOT cfg_done) OR (NOT ctrl_in(1) AND maddr(0) AND maddr(8) AND maddr(1) AND maddr(3) AND maddr(5) AND maddr(4) AND maddr(9) AND maddr(2) AND maddr(6) AND maddr(7) AND NOT wr_maddr)); |
FTCPE_maddr11: FTCPE port map (maddr(11),maddr_T(11),cclk,prog,'0');
maddr_T(11) <= ((EXP12_.EXP) OR (NOT maddr(11) AND mdata(3) AND cfg_done AND wr_maddr AND sel_byte(0) AND NOT sel_byte(1)) OR (maddr(0) AND maddr(8) AND maddr(1) AND maddr(3) AND maddr(5) AND maddr(4) AND maddr(9) AND maddr(2) AND maddr(6) AND maddr(10) AND maddr(7) AND NOT cfg_done) OR (NOT ctrl_in(1) AND maddr(0) AND maddr(8) AND maddr(1) AND maddr(3) AND maddr(5) AND maddr(4) AND maddr(9) AND maddr(2) AND maddr(6) AND maddr(10) AND maddr(7) AND NOT wr_maddr)); |
FTCPE_maddr12: FTCPE port map (maddr(12),maddr_T(12),cclk,prog,'0');
maddr_T(12) <= ((EXP15_.EXP) OR (maddr(0) AND maddr(8) AND maddr(1) AND maddr(3) AND maddr(5) AND maddr(11) AND maddr(4) AND maddr(9) AND maddr(2) AND maddr(6) AND maddr(10) AND maddr(7) AND NOT cfg_done)); |
FTCPE_maddr13: FTCPE port map (maddr(13),maddr_T(13),cclk,prog,'0');
maddr_T(13) <= (($OpTx$crc_16_xor0001/crc_16_xor0001_D2_INV$31.EXP) OR (NOT maddr(13) AND mdata(5) AND cfg_done AND wr_maddr AND sel_byte(0) AND NOT sel_byte(1)) OR (maddr(0) AND maddr(8) AND maddr(1) AND maddr(3) AND maddr(5) AND maddr(11) AND maddr(4) AND maddr(9) AND maddr(2) AND maddr(6) AND maddr(10) AND maddr(12) AND maddr(7) AND NOT cfg_done) OR (NOT ctrl_in(1) AND maddr(0) AND maddr(8) AND maddr(1) AND maddr(3) AND maddr(5) AND maddr(11) AND maddr(4) AND maddr(9) AND maddr(2) AND maddr(6) AND maddr(10) AND maddr(12) AND maddr(7) AND NOT wr_maddr)); |
FTCPE_maddr14: FTCPE port map (maddr(14),maddr_T(14),cclk,prog,'0');
maddr_T(14) <= (($OpTx$crc_17_xor0002/crc_17_xor0002_D2_INV$32.EXP) OR (maddr(14) AND NOT mdata(6) AND cfg_done AND wr_maddr AND sel_byte(0)) OR (NOT maddr(14) AND mdata(6) AND cfg_done AND wr_maddr AND sel_byte(0) AND NOT sel_byte(1)) OR (maddr(0) AND maddr(8) AND maddr(1) AND maddr(3) AND maddr(5) AND maddr(11) AND maddr(13) AND maddr(4) AND maddr(9) AND maddr(2) AND maddr(6) AND maddr(10) AND maddr(12) AND maddr(7) AND NOT cfg_done) OR (NOT ctrl_in(1) AND maddr(0) AND maddr(8) AND maddr(1) AND maddr(3) AND maddr(5) AND maddr(11) AND maddr(13) AND maddr(4) AND maddr(9) AND maddr(2) AND maddr(6) AND maddr(10) AND maddr(12) AND maddr(7) AND NOT wr_maddr)); |
FTCPE_maddr15: FTCPE port map (maddr(15),maddr_T(15),cclk,prog,'0');
maddr_T(15) <= ((maddr_cntr(16).EXP) OR (maddr(15) AND NOT mdata(7) AND cfg_done AND wr_maddr AND sel_byte(0)) OR (NOT maddr(15) AND mdata(7) AND cfg_done AND wr_maddr AND sel_byte(0) AND NOT sel_byte(1)) OR (maddr(0) AND maddr(8) AND maddr(1) AND maddr(3) AND maddr(5) AND maddr(11) AND maddr(13) AND maddr(4) AND maddr(9) AND maddr(2) AND maddr(6) AND maddr(10) AND maddr(12) AND maddr(14) AND maddr(7) AND NOT cfg_done) OR (NOT ctrl_in(1) AND maddr(0) AND maddr(8) AND maddr(1) AND maddr(3) AND maddr(5) AND maddr(11) AND maddr(13) AND maddr(4) AND maddr(9) AND maddr(2) AND maddr(6) AND maddr(10) AND maddr(12) AND maddr(14) AND maddr(7) AND NOT wr_maddr)); |
FTCPE_maddr16: FTCPE port map (maddr(16),maddr_T(16),cclk,prog,'0');
maddr_T(16) <= ((crc(18).EXP) OR (NOT maddr(16) AND mdata(0) AND cfg_done AND wr_maddr AND NOT sel_byte(0) AND sel_byte(1)) OR (maddr(0) AND maddr(8) AND maddr(15) AND maddr(1) AND maddr(3) AND maddr(5) AND maddr(11) AND maddr(13) AND maddr(4) AND maddr(9) AND maddr(2) AND maddr(6) AND maddr(10) AND maddr(12) AND maddr(14) AND maddr(7) AND NOT cfg_done) OR (NOT ctrl_in(1) AND maddr(0) AND maddr(8) AND maddr(15) AND maddr(1) AND maddr(3) AND maddr(5) AND maddr(11) AND maddr(13) AND maddr(4) AND maddr(9) AND maddr(2) AND maddr(6) AND maddr(10) AND maddr(12) AND maddr(14) AND maddr(7) AND NOT wr_maddr)); |
FTCPE_maddr17: FTCPE port map (maddr(17),maddr_T(17),cclk,prog,'0');
maddr_T(17) <= ((EXP16_.EXP) OR (maddr(0) AND maddr(8) AND maddr(15) AND maddr(1) AND maddr(3) AND maddr(5) AND maddr(11) AND maddr(13) AND maddr(4) AND maddr(9) AND maddr(16) AND maddr(2) AND maddr(6) AND maddr(10) AND maddr(12) AND maddr(14) AND maddr(7) AND NOT cfg_done)); |
maddr(18) <= '0'; |
mce_b <= NOT (((NOT ctrl_in(0))
OR (NOT cfg_done AND NOT loc_mode) OR (loc_add(5) AND ctrl_in(1) AND NOT loc_cs AND NOT loc_add(4) AND NOT loc_add(3) AND NOT loc_add(2) AND NOT loc_add(1) AND NOT loc_add(0) AND NOT loc_add(6)))); |
FDCPE_mdata0: FDCPE port map (mdata_I(0),loc_bus(0).PIN,NOT loc_cs,'0','0');
mdata(0) <= mdata_I(0) when mdata_OE(0) = '1' else 'Z'; mdata_OE(0) <= (NOT loc_rw AND NOT $OpTx$mdata_and00004/mdata_and00004_D2_INV$34); |
FDCPE_mdata1: FDCPE port map (mdata_I(1),loc_bus(1).PIN,NOT loc_cs,'0','0');
mdata(1) <= mdata_I(1) when mdata_OE(1) = '1' else 'Z'; mdata_OE(1) <= (NOT loc_rw AND NOT $OpTx$mdata_and00004/mdata_and00004_D2_INV$34); |
FDCPE_mdata2: FDCPE port map (mdata_I(2),loc_bus(2).PIN,NOT loc_cs,'0','0');
mdata(2) <= mdata_I(2) when mdata_OE(2) = '1' else 'Z'; mdata_OE(2) <= (NOT loc_rw AND NOT $OpTx$mdata_and00004/mdata_and00004_D2_INV$34); |
FDCPE_mdata3: FDCPE port map (mdata_I(3),loc_bus(3).PIN,NOT loc_cs,'0','0');
mdata(3) <= mdata_I(3) when mdata_OE(3) = '1' else 'Z'; mdata_OE(3) <= (NOT loc_rw AND NOT $OpTx$mdata_and00004/mdata_and00004_D2_INV$34); |
FDCPE_mdata4: FDCPE port map (mdata_I(4),loc_bus(4).PIN,NOT loc_cs,'0','0');
mdata(4) <= mdata_I(4) when mdata_OE(4) = '1' else 'Z'; mdata_OE(4) <= (NOT loc_rw AND NOT $OpTx$mdata_and00004/mdata_and00004_D2_INV$34); |
FDCPE_mdata5: FDCPE port map (mdata_I(5),loc_bus(5).PIN,NOT loc_cs,'0','0');
mdata(5) <= mdata_I(5) when mdata_OE(5) = '1' else 'Z'; mdata_OE(5) <= (NOT loc_rw AND NOT $OpTx$mdata_and00004/mdata_and00004_D2_INV$34); |
FDCPE_mdata6: FDCPE port map (mdata_I(6),loc_bus(6).PIN,NOT loc_cs,'0','0');
mdata(6) <= mdata_I(6) when mdata_OE(6) = '1' else 'Z'; mdata_OE(6) <= (NOT loc_rw AND NOT $OpTx$mdata_and00004/mdata_and00004_D2_INV$34); |
FDCPE_mdata7: FDCPE port map (mdata_I(7),loc_bus(7).PIN,NOT loc_cs,'0','0');
mdata(7) <= mdata_I(7) when mdata_OE(7) = '1' else 'Z'; mdata_OE(7) <= (NOT loc_rw AND NOT $OpTx$mdata_and00004/mdata_and00004_D2_INV$34); |
moe_b <= ((NOT ctrl_in(1) AND cfg_done)
OR (NOT loc_rw AND cfg_done)); |
mwe_b <= ((NOT cfg_done)
OR (ctrl_in(1) AND loc_rw)); |
FDCPE_powerup: FDCPE port map (powerup,'0',cclk,'0','0',maddr(4)); |
FDCPE_prog: FDCPE port map (prog,loc_bus(1).PIN,NOT loc_cs,'0','0',prog_CE);
prog_CE <= (NOT loc_add(5) AND NOT loc_add(4) AND NOT loc_add(3) AND NOT loc_add(2) AND loc_add(1) AND loc_add(0) AND loc_add(6) AND NOT loc_rw AND en_loc_bus); |
prog_b_I <= '0';
prog_b <= prog_b_I when prog_b_OE = '1' else 'Z'; prog_b_OE <= NOT ((NOT prog AND NOT powerup)); |
rdwr_b <= (loc_rw AND cfg_done); |
ring_os(0) <= ((cfg_fail)
OR (NOT cclk_fb) OR (loc_mode) OR (ctrl_in(1) AND cfg_done AND NOT div(4))); |
ring_os(1) <= ring_os(0); |
ring_os(2) <= ring_os(1); |
FDCPE_sel_byte0: FDCPE port map (sel_byte(0),loc_add(0),NOT loc_cs,'0','0'); |
FDCPE_sel_byte1: FDCPE port map (sel_byte(1),cclkp_OBUF.EXP,NOT loc_cs,'0','0'); |
spare3 <= NOT ((cfg_done AND NOT div(4))); |
spare5 <= NOT ((NOT loc_cs AND cfg_done)); |
FDCPE_wr_maddr: FDCPE port map (wr_maddr,wr_maddr_D,NOT loc_cs,NOT ctrl_in(1),'0');
wr_maddr_D <= (loc_add(5) AND NOT loc_add(4) AND NOT loc_add(3) AND NOT loc_add(2) AND loc_add(6) AND NOT loc_rw AND cfg_done); |
Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); |