Timing Report

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Design Name HTR_SLB
Device, Speed (SpeedFile Version) XC95144XL, -10 (3.0)
Date Created Wed Apr 25 11:07:03 2007
Created By Timing Report Generator: version J.33
Copyright Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.

Summary

Performance Summary
Min. Clock Period 30.100 ns.
Max. Clock Frequency (fSYSTEM) 33.223 MHz.
Limited by Cycle Time for cclk
Clock to Setup (tCYC) 30.100 ns.
Pad to Pad Delay (tPD) 59.600 ns.
Setup to Clock at the Pad (tSU) 26.200 ns.
Clock Pad to Output Pad Delay (tCO) 63.100 ns.

Timing Constraints

Constraint Name Requirement (ns) Delay (ns) Paths Paths Failing
TS_loc_cs 200.0 0.0 0 0


Constraint: TS_loc_cs

Description: PERIOD:loc_cs:200.000nS:HIGH:100.000nS
Path Requirement (ns) Delay (ns) Slack (ns)



Number of constraints not met: 0

Data Sheet Report

Maximum External Clock Speeds

Clock fEXT (MHz) Reason
div<3>.Q 71.429 Limited by Clock Pulse Width for div<3>.Q
div<2>.Q 71.429 Limited by Clock Pulse Width for div<2>.Q
div<1>.Q 71.429 Limited by Clock Pulse Width for div<1>.Q
div<0>.Q 71.429 Limited by Clock Pulse Width for div<0>.Q
cclk_fb 71.429 Limited by Clock Pulse Width for cclk_fb
loc_cs 111.111 Limited by Clock Pulse Width for loc_cs
cclk 33.223 Limited by Cycle Time for cclk

Setup/Hold Times for Clocks

Setup/Hold Times for Clock loc_cs
Source Pad Setup to clk (edge) Hold to clk (edge)
loc_add<0> 12.000 0.000
loc_add<1> 12.000 0.000
loc_add<2> 12.000 0.000
loc_add<3> 12.000 0.000
loc_add<4> 12.000 0.000
loc_add<5> 12.000 0.000
loc_add<6> 12.000 0.000
loc_bus<0> 12.000 0.000
loc_bus<1> 12.000 0.000
loc_bus<2> 12.000 0.000
loc_bus<3> 12.000 0.000
loc_bus<4> 12.000 0.000
loc_bus<5> 12.000 0.000
loc_bus<6> 12.000 0.000
loc_bus<7> 12.000 0.000
loc_rw 12.000 0.000

Setup/Hold Times for Clock cclk
Source Pad Setup to clk (edge) Hold to clk (edge)
ctrl_in<1> 13.000 0.000
done 6.500 0.000
mdata<0> 13.000 0.000
mdata<1> 12.000 0.000
mdata<2> 12.000 0.000
mdata<3> 13.400 0.000
mdata<4> 13.000 0.000
mdata<5> 26.200 0.000
mdata<6> 13.400 0.000
mdata<7> 13.000 0.000


Clock to Pad Timing

Clock cclk_fb to Pad
Destination Pad Clock (edge) to Pad
cclkp 59.500

Clock loc_cs to Pad
Destination Pad Clock (edge) to Pad
cclk_fbp 63.100
mdata<0> 27.700
mdata<1> 27.700
mdata<2> 27.700
mdata<3> 27.700
mdata<4> 27.700
mdata<5> 27.700
mdata<6> 27.700
mdata<7> 27.700
cclkp 24.500
loc_bus<0> 24.500
loc_bus<1> 24.500
mce_b 23.500
prog_b 14.500

Clock cclk to Pad
Destination Pad Clock (edge) to Pad
cclk_fbp 63.100
cclkp 24.500
loc_bus<0> 24.500
loc_bus<1> 24.500
loc_bus<2> 24.500
loc_bus<3> 24.500
loc_bus<4> 24.500
loc_bus<5> 24.500
loc_bus<6> 24.500
loc_bus<7> 24.500
cs_b 23.500
mce_b 23.500
moe_b 23.500
mwe_b 23.500
rdwr_b 23.500
spare5 23.500
prog_b 14.500
maddr<0> 10.300
maddr<10> 10.300
maddr<11> 10.300
maddr<12> 10.300
maddr<13> 10.300
maddr<14> 10.300
maddr<15> 10.300
maddr<16> 10.300
maddr<17> 10.300
maddr<1> 10.300
maddr<2> 10.300
maddr<3> 10.300
maddr<4> 10.300
maddr<5> 10.300
maddr<6> 10.300
maddr<7> 10.300
maddr<8> 10.300
maddr<9> 10.300


Clock to Setup Times for Clocks

Clock to Setup for clock cclk
Source Destination Delay
crc<16>.Q crc<14>.D 30.100
crc<20>.Q crc<14>.D 30.100
crc<21>.Q crc<14>.D 30.100
crc<15>.Q crc<23>.D 29.700
crc<16>.Q crc<0>.D 29.700
crc<16>.Q crc<10>.D 29.700
crc<18>.Q crc<15>.D 29.700
crc<18>.Q crc<16>.D 29.700
crc<18>.Q crc<7>.D 29.700
crc<19>.Q crc<0>.D 29.700
crc<19>.Q crc<23>.D 29.700
crc<19>.Q crc<5>.D 29.700
crc<20>.Q crc<0>.D 29.700
crc<20>.Q crc<10>.D 29.700
crc<20>.Q crc<23>.D 29.700
crc<20>.Q crc<7>.D 29.700
crc<21>.Q crc<8>.D 29.700
crc<22>.Q crc<15>.D 29.700
crc<22>.Q crc<16>.D 29.700
crc<22>.Q crc<8>.D 29.700
crc<23>.Q crc<16>.D 29.700
crc<23>.Q crc<5>.D 29.700
crc<23>.Q crc<7>.D 29.700
crc<2>.Q crc<10>.D 29.700
crc<16>.Q crc<3>.D 16.900
crc<16>.Q crc<6>.D 16.900
crc<17>.Q crc<3>.D 16.900
crc<18>.Q crc<14>.D 16.900
crc<18>.Q crc<6>.D 16.900
crc<20>.Q crc<3>.D 16.900
crc<21>.Q crc<3>.D 16.900
crc<21>.Q crc<6>.D 16.900
crc<23>.Q crc<14>.D 16.900
crc<6>.Q crc<14>.D 16.900
cfg_done.Q maddr<10>.D 16.500
cfg_done.Q maddr<11>.D 16.500
cfg_done.Q maddr<12>.D 16.500
cfg_done.Q maddr<13>.D 16.500
cfg_done.Q maddr<14>.D 16.500
cfg_done.Q maddr<15>.D 16.500
cfg_done.Q maddr<16>.D 16.500
cfg_done.Q maddr<17>.D 16.500
cfg_done.Q maddr<1>.D 16.500
cfg_done.Q maddr<2>.D 16.500
cfg_done.Q maddr<3>.D 16.500
cfg_done.Q maddr<4>.D 16.500
cfg_done.Q maddr<5>.D 16.500
cfg_done.Q maddr<6>.D 16.500
cfg_done.Q maddr<7>.D 16.500
cfg_done.Q maddr<8>.D 16.500
cfg_done.Q maddr<9>.D 16.500
crc<0>.Q crc<8>.D 16.500
crc<10>.Q crc<18>.D 16.500
crc<11>.Q crc<19>.D 16.500
crc<12>.Q crc<20>.D 16.500
crc<16>.Q crc<4>.D 16.500
crc<16>.Q crc<7>.D 16.500
crc<17>.Q crc<15>.D 16.500
crc<17>.Q crc<19>.D 16.500
crc<17>.Q crc<23>.D 16.500
crc<17>.Q crc<8>.D 16.500
crc<18>.Q crc<0>.D 16.500
crc<18>.Q crc<10>.D 16.500
crc<18>.Q crc<13>.D 16.500
crc<18>.Q crc<17>.D 16.500
crc<18>.Q crc<20>.D 16.500
crc<18>.Q crc<23>.D 16.500
crc<18>.Q crc<5>.D 16.500
crc<18>.Q crc<9>.D 16.500
crc<19>.Q crc<4>.D 16.500
crc<1>.Q crc<9>.D 16.500
crc<20>.Q crc<11>.D 16.500
crc<20>.Q crc<16>.D 16.500
crc<20>.Q crc<18>.D 16.500
crc<20>.Q crc<9>.D 16.500
crc<21>.Q crc<0>.D 16.500
crc<21>.Q crc<12>.D 16.500
crc<21>.Q crc<15>.D 16.500
crc<21>.Q crc<18>.D 16.500
crc<21>.Q crc<19>.D 16.500
crc<21>.Q crc<5>.D 16.500
crc<21>.Q crc<7>.D 16.500
crc<23>.Q crc<10>.D 16.500
crc<23>.Q crc<17>.D 16.500
crc<23>.Q crc<20>.D 16.500
crc<23>.Q crc<8>.D 16.500
crc<23>.Q crc<9>.D 16.500
crc<3>.Q crc<11>.D 16.500
crc<4>.Q crc<12>.D 16.500
crc<5>.Q crc<13>.D 16.500
crc<7>.Q crc<15>.D 16.500
crc<8>.Q crc<16>.D 16.500
crc<9>.Q crc<17>.D 16.500
maddr<0>.Q maddr<0>.D 16.500
maddr<0>.Q maddr<1>.D 16.500
maddr<0>.Q maddr<3>.D 16.500
maddr<10>.Q maddr<10>.D 16.500
maddr<11>.Q maddr<11>.D 16.500
maddr<12>.Q maddr<12>.D 16.500
maddr<13>.Q maddr<13>.D 16.500
maddr<14>.Q maddr<14>.D 16.500
maddr<15>.Q maddr<15>.D 16.500
maddr<16>.Q maddr<16>.D 16.500
maddr<17>.Q maddr<17>.D 16.500
maddr<1>.Q maddr<1>.D 16.500
maddr<1>.Q maddr<3>.D 16.500
maddr<2>.Q maddr<2>.D 16.500
maddr<2>.Q maddr<3>.D 16.500
maddr<3>.Q maddr<3>.D 16.500
maddr<4>.Q maddr<4>.D 16.500
maddr<5>.Q maddr<5>.D 16.500
maddr<6>.Q maddr<6>.D 16.500
maddr<7>.Q maddr<7>.D 16.500
maddr<8>.Q maddr<8>.D 16.500
maddr<9>.Q maddr<9>.D 16.500
cfg_done.Q en_loc_bus.D 15.500
cfg_done.Q maddr<0>.D 15.500
crc<13>.Q crc<21>.D 15.500
crc<14>.Q crc<22>.D 15.500
crc<16>.Q crc<11>.D 15.500
crc<16>.Q crc<17>.D 15.500
crc<16>.Q crc<18>.D 15.500
crc<16>.Q crc<1>.D 15.500
crc<16>.Q crc<23>.D 15.500
crc<16>.Q crc<5>.D 15.500
crc<17>.Q crc<0>.D 15.500
crc<17>.Q crc<10>.D 15.500
crc<17>.Q crc<12>.D 15.500
crc<17>.Q crc<14>.D 15.500
crc<17>.Q crc<2>.D 15.500
crc<19>.Q crc<15>.D 15.500
crc<19>.Q crc<16>.D 15.500
crc<19>.Q crc<21>.D 15.500
crc<19>.Q crc<3>.D 15.500
crc<19>.Q crc<8>.D 15.500
crc<20>.Q crc<22>.D 15.500
crc<22>.Q crc<13>.D 15.500
crc<22>.Q crc<19>.D 15.500
crc<22>.Q crc<1>.D 15.500
crc<22>.Q crc<20>.D 15.500
crc<22>.Q crc<4>.D 15.500
crc<22>.Q crc<6>.D 15.500
crc<22>.Q crc<7>.D 15.500
crc<22>.Q crc<9>.D 15.500
crc<23>.Q crc<21>.D 15.500
crc<23>.Q crc<2>.D 15.500
en_conf.Q en_conf.D 15.500
en_conf.Q en_loc_bus.D 15.500
en_loc_bus.Q en_loc_bus.D 15.500
maddr<0>.Q en_conf.D 15.500
maddr<0>.Q maddr<10>.D 15.500
maddr<0>.Q maddr<11>.D 15.500
maddr<0>.Q maddr<12>.D 15.500
maddr<0>.Q maddr<13>.D 15.500
maddr<0>.Q maddr<14>.D 15.500
maddr<0>.Q maddr<15>.D 15.500
maddr<0>.Q maddr<16>.D 15.500
maddr<0>.Q maddr<17>.D 15.500
maddr<0>.Q maddr<2>.D 15.500
maddr<0>.Q maddr<4>.D 15.500
maddr<0>.Q maddr<5>.D 15.500
maddr<0>.Q maddr<6>.D 15.500
maddr<0>.Q maddr<7>.D 15.500
maddr<0>.Q maddr<8>.D 15.500
maddr<0>.Q maddr<9>.D 15.500
maddr<10>.Q en_conf.D 15.500
maddr<10>.Q maddr<11>.D 15.500
maddr<10>.Q maddr<12>.D 15.500
maddr<10>.Q maddr<13>.D 15.500
maddr<10>.Q maddr<14>.D 15.500
maddr<10>.Q maddr<15>.D 15.500
maddr<10>.Q maddr<16>.D 15.500
maddr<10>.Q maddr<17>.D 15.500
maddr<11>.Q en_conf.D 15.500
maddr<11>.Q maddr<12>.D 15.500
maddr<11>.Q maddr<13>.D 15.500
maddr<11>.Q maddr<14>.D 15.500
maddr<11>.Q maddr<15>.D 15.500
maddr<11>.Q maddr<16>.D 15.500
maddr<11>.Q maddr<17>.D 15.500
maddr<12>.Q en_conf.D 15.500
maddr<12>.Q maddr<13>.D 15.500
maddr<12>.Q maddr<14>.D 15.500
maddr<12>.Q maddr<15>.D 15.500
maddr<12>.Q maddr<16>.D 15.500
maddr<12>.Q maddr<17>.D 15.500
maddr<13>.Q en_conf.D 15.500
maddr<13>.Q maddr<14>.D 15.500
maddr<13>.Q maddr<15>.D 15.500
maddr<13>.Q maddr<16>.D 15.500
maddr<13>.Q maddr<17>.D 15.500
maddr<14>.Q en_conf.D 15.500
maddr<14>.Q maddr<15>.D 15.500
maddr<14>.Q maddr<16>.D 15.500
maddr<14>.Q maddr<17>.D 15.500
maddr<15>.Q en_conf.D 15.500
maddr<15>.Q en_loc_bus.D 15.500
maddr<15>.Q maddr<16>.D 15.500
maddr<15>.Q maddr<17>.D 15.500
maddr<16>.Q en_conf.D 15.500
maddr<16>.Q en_loc_bus.D 15.500
maddr<16>.Q maddr<17>.D 15.500
maddr<17>.Q en_conf.D 15.500
maddr<17>.Q en_loc_bus.D 15.500
maddr<17>.Q powerup.D 15.500
maddr<1>.Q en_conf.D 15.500
maddr<1>.Q maddr<10>.D 15.500
maddr<1>.Q maddr<11>.D 15.500
maddr<1>.Q maddr<12>.D 15.500
maddr<1>.Q maddr<13>.D 15.500
maddr<1>.Q maddr<14>.D 15.500
maddr<1>.Q maddr<15>.D 15.500
maddr<1>.Q maddr<16>.D 15.500
maddr<1>.Q maddr<17>.D 15.500
maddr<1>.Q maddr<2>.D 15.500
maddr<1>.Q maddr<4>.D 15.500
maddr<1>.Q maddr<5>.D 15.500
maddr<1>.Q maddr<6>.D 15.500
maddr<1>.Q maddr<7>.D 15.500
maddr<1>.Q maddr<8>.D 15.500
maddr<1>.Q maddr<9>.D 15.500
maddr<2>.Q en_conf.D 15.500
maddr<2>.Q maddr<10>.D 15.500
maddr<2>.Q maddr<11>.D 15.500
maddr<2>.Q maddr<12>.D 15.500
maddr<2>.Q maddr<13>.D 15.500
maddr<2>.Q maddr<14>.D 15.500
maddr<2>.Q maddr<15>.D 15.500
maddr<2>.Q maddr<16>.D 15.500
maddr<2>.Q maddr<17>.D 15.500
maddr<2>.Q maddr<4>.D 15.500
maddr<2>.Q maddr<5>.D 15.500
maddr<2>.Q maddr<6>.D 15.500
maddr<2>.Q maddr<7>.D 15.500
maddr<2>.Q maddr<8>.D 15.500
maddr<2>.Q maddr<9>.D 15.500
maddr<3>.Q en_conf.D 15.500
maddr<3>.Q maddr<10>.D 15.500
maddr<3>.Q maddr<11>.D 15.500
maddr<3>.Q maddr<12>.D 15.500
maddr<3>.Q maddr<13>.D 15.500
maddr<3>.Q maddr<14>.D 15.500
maddr<3>.Q maddr<15>.D 15.500
maddr<3>.Q maddr<16>.D 15.500
maddr<3>.Q maddr<17>.D 15.500
maddr<3>.Q maddr<4>.D 15.500
maddr<3>.Q maddr<5>.D 15.500
maddr<3>.Q maddr<6>.D 15.500
maddr<3>.Q maddr<7>.D 15.500
maddr<3>.Q maddr<8>.D 15.500
maddr<3>.Q maddr<9>.D 15.500
maddr<4>.Q en_conf.D 15.500
maddr<4>.Q maddr<10>.D 15.500
maddr<4>.Q maddr<11>.D 15.500
maddr<4>.Q maddr<12>.D 15.500
maddr<4>.Q maddr<13>.D 15.500
maddr<4>.Q maddr<14>.D 15.500
maddr<4>.Q maddr<15>.D 15.500
maddr<4>.Q maddr<16>.D 15.500
maddr<4>.Q maddr<17>.D 15.500
maddr<4>.Q maddr<5>.D 15.500
maddr<4>.Q maddr<6>.D 15.500
maddr<4>.Q maddr<7>.D 15.500
maddr<4>.Q maddr<8>.D 15.500
maddr<4>.Q maddr<9>.D 15.500
maddr<5>.Q en_conf.D 15.500
maddr<5>.Q maddr<10>.D 15.500
maddr<5>.Q maddr<11>.D 15.500
maddr<5>.Q maddr<12>.D 15.500
maddr<5>.Q maddr<13>.D 15.500
maddr<5>.Q maddr<14>.D 15.500
maddr<5>.Q maddr<15>.D 15.500
maddr<5>.Q maddr<16>.D 15.500
maddr<5>.Q maddr<17>.D 15.500
maddr<5>.Q maddr<6>.D 15.500
maddr<5>.Q maddr<7>.D 15.500
maddr<5>.Q maddr<8>.D 15.500
maddr<5>.Q maddr<9>.D 15.500
maddr<6>.Q en_conf.D 15.500
maddr<6>.Q maddr<10>.D 15.500
maddr<6>.Q maddr<11>.D 15.500
maddr<6>.Q maddr<12>.D 15.500
maddr<6>.Q maddr<13>.D 15.500
maddr<6>.Q maddr<14>.D 15.500
maddr<6>.Q maddr<15>.D 15.500
maddr<6>.Q maddr<16>.D 15.500
maddr<6>.Q maddr<17>.D 15.500
maddr<6>.Q maddr<7>.D 15.500
maddr<6>.Q maddr<8>.D 15.500
maddr<6>.Q maddr<9>.D 15.500
maddr<7>.Q en_conf.D 15.500
maddr<7>.Q maddr<10>.D 15.500
maddr<7>.Q maddr<11>.D 15.500
maddr<7>.Q maddr<12>.D 15.500
maddr<7>.Q maddr<13>.D 15.500
maddr<7>.Q maddr<14>.D 15.500
maddr<7>.Q maddr<15>.D 15.500
maddr<7>.Q maddr<16>.D 15.500
maddr<7>.Q maddr<17>.D 15.500
maddr<7>.Q maddr<8>.D 15.500
maddr<7>.Q maddr<9>.D 15.500
maddr<8>.Q en_conf.D 15.500
maddr<8>.Q maddr<10>.D 15.500
maddr<8>.Q maddr<11>.D 15.500
maddr<8>.Q maddr<12>.D 15.500
maddr<8>.Q maddr<13>.D 15.500
maddr<8>.Q maddr<14>.D 15.500
maddr<8>.Q maddr<15>.D 15.500
maddr<8>.Q maddr<16>.D 15.500
maddr<8>.Q maddr<17>.D 15.500
maddr<8>.Q maddr<9>.D 15.500
maddr<9>.Q en_conf.D 15.500
maddr<9>.Q maddr<10>.D 15.500
maddr<9>.Q maddr<11>.D 15.500
maddr<9>.Q maddr<12>.D 15.500
maddr<9>.Q maddr<13>.D 15.500
maddr<9>.Q maddr<14>.D 15.500
maddr<9>.Q maddr<15>.D 15.500
maddr<9>.Q maddr<16>.D 15.500
maddr<9>.Q maddr<17>.D 15.500
powerup.Q powerup.D 15.500
cfg_done.Q crc<0>.CE 10.000
cfg_done.Q crc<10>.CE 10.000
cfg_done.Q crc<11>.CE 10.000
cfg_done.Q crc<12>.CE 10.000
cfg_done.Q crc<13>.CE 10.000
cfg_done.Q crc<14>.CE 10.000
cfg_done.Q crc<15>.CE 10.000
cfg_done.Q crc<16>.CE 10.000
cfg_done.Q crc<17>.CE 10.000
cfg_done.Q crc<18>.CE 10.000
cfg_done.Q crc<19>.CE 10.000
cfg_done.Q crc<1>.CE 10.000
cfg_done.Q crc<20>.CE 10.000
cfg_done.Q crc<21>.CE 10.000
cfg_done.Q crc<22>.CE 10.000
cfg_done.Q crc<23>.CE 10.000
cfg_done.Q crc<2>.CE 10.000
cfg_done.Q crc<3>.CE 10.000
cfg_done.Q crc<4>.CE 10.000
cfg_done.Q crc<5>.CE 10.000
cfg_done.Q crc<6>.CE 10.000
cfg_done.Q crc<7>.CE 10.000
cfg_done.Q crc<8>.CE 10.000
cfg_done.Q crc<9>.CE 10.000
en_conf.Q crc<0>.CE 10.000
en_conf.Q crc<10>.CE 10.000
en_conf.Q crc<11>.CE 10.000
en_conf.Q crc<12>.CE 10.000
en_conf.Q crc<13>.CE 10.000
en_conf.Q crc<14>.CE 10.000
en_conf.Q crc<15>.CE 10.000
en_conf.Q crc<16>.CE 10.000
en_conf.Q crc<17>.CE 10.000
en_conf.Q crc<18>.CE 10.000
en_conf.Q crc<19>.CE 10.000
en_conf.Q crc<1>.CE 10.000
en_conf.Q crc<20>.CE 10.000
en_conf.Q crc<21>.CE 10.000
en_conf.Q crc<22>.CE 10.000
en_conf.Q crc<23>.CE 10.000
en_conf.Q crc<2>.CE 10.000
en_conf.Q crc<3>.CE 10.000
en_conf.Q crc<4>.CE 10.000
en_conf.Q crc<5>.CE 10.000
en_conf.Q crc<6>.CE 10.000
en_conf.Q crc<7>.CE 10.000
en_conf.Q crc<8>.CE 10.000
en_conf.Q crc<9>.CE 10.000
maddr<0>.Q cfg_done.CE 10.000
maddr<10>.Q cfg_done.CE 10.000
maddr<11>.Q cfg_done.CE 10.000
maddr<12>.Q cfg_done.CE 10.000
maddr<13>.Q cfg_done.CE 10.000
maddr<14>.Q cfg_done.CE 10.000
maddr<15>.Q cfg_done.CE 10.000
maddr<16>.Q cfg_done.CE 10.000
maddr<17>.Q cfg_done.CE 10.000
maddr<1>.Q cfg_done.CE 10.000
maddr<2>.Q cfg_done.CE 10.000
maddr<3>.Q cfg_done.CE 10.000
maddr<4>.Q cfg_done.CE 10.000
maddr<5>.Q cfg_done.CE 10.000
maddr<6>.Q cfg_done.CE 10.000
maddr<7>.Q cfg_done.CE 10.000
maddr<8>.Q cfg_done.CE 10.000
maddr<9>.Q cfg_done.CE 10.000


Pad to Pad List

Source Pad Destination Pad Delay
cclk_fb cclk_fbp 59.600
init_b cclk_fbp 59.600
ctrl_in<1> mdata<0> 24.200
ctrl_in<1> mdata<1> 24.200
ctrl_in<1> mdata<2> 24.200
ctrl_in<1> mdata<3> 24.200
ctrl_in<1> mdata<4> 24.200
ctrl_in<1> mdata<5> 24.200
ctrl_in<1> mdata<6> 24.200
ctrl_in<1> mdata<7> 24.200
done mdata<0> 24.200
done mdata<1> 24.200
done mdata<2> 24.200
done mdata<3> 24.200
done mdata<4> 24.200
done mdata<5> 24.200
done mdata<6> 24.200
done mdata<7> 24.200
loc_rw mdata<0> 24.200
loc_rw mdata<1> 24.200
loc_rw mdata<2> 24.200
loc_rw mdata<3> 24.200
loc_rw mdata<4> 24.200
loc_rw mdata<5> 24.200
loc_rw mdata<6> 24.200
loc_rw mdata<7> 24.200
ctrl_in<0> loc_bus<4> 21.000
ctrl_in<1> loc_bus<5> 21.000
ctrl_in<2> loc_bus<6> 21.000
done loc_bus<3> 21.000
init_b loc_bus<2> 21.000
loc_add<0> loc_bus<0> 21.000
loc_add<0> loc_bus<1> 21.000
loc_add<0> loc_bus<2> 21.000
loc_add<0> loc_bus<3> 21.000
loc_add<0> loc_bus<4> 21.000
loc_add<0> loc_bus<5> 21.000
loc_add<0> loc_bus<6> 21.000
loc_add<0> loc_bus<7> 21.000
loc_add<1> loc_bus<0> 21.000
loc_add<1> loc_bus<1> 21.000
loc_add<1> loc_bus<2> 21.000
loc_add<1> loc_bus<3> 21.000
loc_add<1> loc_bus<4> 21.000
loc_add<1> loc_bus<5> 21.000
loc_add<1> loc_bus<6> 21.000
loc_add<1> loc_bus<7> 21.000
loc_add<5> cclkp 21.000
loc_add<5> loc_bus<0> 21.000
loc_add<5> loc_bus<1> 21.000
loc_add<5> loc_bus<2> 21.000
loc_add<5> loc_bus<3> 21.000
loc_add<5> loc_bus<4> 21.000
loc_add<5> loc_bus<5> 21.000
loc_add<5> loc_bus<6> 21.000
loc_add<5> loc_bus<7> 21.000
loc_add<6> cclkp 21.000
loc_add<6> loc_bus<0> 21.000
loc_add<6> loc_bus<1> 21.000
loc_add<6> loc_bus<2> 21.000
loc_add<6> loc_bus<3> 21.000
loc_add<6> loc_bus<4> 21.000
loc_add<6> loc_bus<5> 21.000
loc_add<6> loc_bus<6> 21.000
loc_add<6> loc_bus<7> 21.000
loc_cs cclkp 21.000
loc_rw cclkp 21.000
ctrl_in<0> cclkp 20.000
ctrl_in<0> mce_b 20.000
ctrl_in<1> cclkp 20.000
ctrl_in<1> mce_b 20.000
ctrl_in<1> moe_b 20.000
ctrl_in<1> mwe_b 20.000
init_b cs_b 20.000
loc_add<0> loc_add_out<0> 20.000
loc_add<0> mce_b 20.000
loc_add<1> loc_add_out<1> 20.000
loc_add<1> mce_b 20.000
loc_add<2> loc_add_out<2> 20.000
loc_add<2> mce_b 20.000
loc_add<3> loc_add_out<3> 20.000
loc_add<3> mce_b 20.000
loc_add<4> loc_add_out<4> 20.000
loc_add<4> mce_b 20.000
loc_add<5> loc_add_out<5> 20.000
loc_add<5> mce_b 20.000
loc_add<6> loc_add_out<6> 20.000
loc_add<6> mce_b 20.000
loc_cs cs_b 20.000
loc_cs mce_b 20.000
loc_cs spare5 20.000
loc_rw moe_b 20.000
loc_rw mwe_b 20.000
loc_rw rdwr_b 20.000
mdata<0> loc_bus<0> 20.000
mdata<1> loc_bus<1> 20.000
mdata<2> loc_bus<2> 20.000
mdata<3> loc_bus<3> 20.000
mdata<4> loc_bus<4> 20.000
mdata<5> loc_bus<5> 20.000
mdata<6> loc_bus<6> 20.000
mdata<7> loc_bus<7> 20.000
loc_cs loc_bus<0> 11.000
loc_cs loc_bus<1> 11.000
loc_cs loc_bus<2> 11.000
loc_cs loc_bus<3> 11.000
loc_cs loc_bus<4> 11.000
loc_cs loc_bus<5> 11.000
loc_cs loc_bus<6> 11.000
loc_cs loc_bus<7> 11.000
loc_rw loc_bus<0> 11.000
loc_rw loc_bus<1> 11.000
loc_rw loc_bus<2> 11.000
loc_rw loc_bus<3> 11.000
loc_rw loc_bus<4> 11.000
loc_rw loc_bus<5> 11.000
loc_rw loc_bus<6> 11.000
loc_rw loc_bus<7> 11.000



Number of paths analyzed: 0
Number of Timing errors: 0
Analysis Completed: Wed Apr 25 11:07:03 2007