Signal Name | Total Pterms | Total Inputs | Function Block | Macrocell | Power Mode | Slew Rate | Pin Number | Pin Type | Pin Use | Reg Init State |
---|---|---|---|---|---|---|---|---|---|---|
mdata<4> | 2 | 3 | FB1 | MC2 | LOW | SLOW | 11 | I/O | I/O | RESET |
mdata<5> | 2 | 3 | FB1 | MC3 | LOW | SLOW | 12 | I/O | I/O | RESET |
cfg_fail | 3 | 21 | FB1 | MC4 | LOW | (b) | (b) | RESET | ||
mdata<6> | 2 | 3 | FB1 | MC5 | LOW | SLOW | 13 | I/O | I/O | RESET |
mdata<7> | 2 | 3 | FB1 | MC6 | LOW | SLOW | 14 | I/O | I/O | RESET |
$OpTx$mdata_and00004/mdata_and00004_D2_INV$34 | 2 | 3 | FB1 | MC7 | LOW | (b) | (b) | |||
mce_b | 3 | 12 | FB1 | MC8 | LOW | SLOW | 15 | I/O | O | |
maddr<10> | 6 | 18 | FB1 | MC9 | LOW | SLOW | 16 | I/O | O | RESET |
cfg_done | 2 | 20 | FB1 | MC10 | LOW | (b) | (b) | RESET | ||
moe_b | 2 | 3 | FB1 | MC11 | LOW | SLOW | 17 | I/O | O | |
rdwr_b | 1 | 2 | FB1 | MC12 | LOW | SLOW | 18 | I/O | O | |
wr_maddr | 2 | 8 | FB1 | MC13 | LOW | (b) | (b) | RESET | ||
powerup | 1 | 1 | FB1 | MC14 | LOW | 19 | I/O | (b) | SET | |
cs_b | 2 | 4 | FB1 | MC15 | LOW | SLOW | 20 | I/O | O | |
sel_byte<0> | 1 | 1 | FB1 | MC16 | LOW | (b) | (b) | RESET | ||
en_conf | 21 | 21 | FB1 | MC18 | LOW | (b) | (b) | RESET | ||
$OpTx$crc_17_xor0002/crc_17_xor0002_D2_INV$32 | 2 | 2 | FB2 | MC1 | LOW | (b) | (b) | |||
maddr<14> | 6 | 22 | FB2 | MC2 | LOW | SLOW | 99 | I/O/GSR | O | RESET |
$OpTx$crc_17_xor0002/crc_17_xor0002_D213__INV$37 | 2 | 2 | FB2 | MC3 | LOW | (b) | (b) | |||
$OpTx$crc_16_xor0001/crc_16_xor0001_D2_INV$31 | 2 | 2 | FB2 | MC4 | LOW | (b) | (b) | |||
maddr<13> | 6 | 21 | FB2 | MC5 | LOW | SLOW | 1 | I/O/GTS3 | O | RESET |
maddr<8> | 6 | 16 | FB2 | MC6 | LOW | SLOW | 2 | I/O/GTS4 | O | RESET |
crc<11> | 5 | 6 | FB2 | MC7 | LOW | (b) | (b) | RESET | ||
maddr<9> | 6 | 17 | FB2 | MC8 | LOW | SLOW | 3 | I/O/GTS1 | O | RESET |
maddr<11> | 6 | 19 | FB2 | MC9 | LOW | SLOW | 4 | I/O/GTS2 | O | RESET |
mdata<0> | 2 | 3 | FB2 | MC11 | LOW | SLOW | 6 | I/O | I/O | RESET |
crc<3> | 11 | 8 | FB2 | MC12 | LOW | 7 | I/O | (b) | RESET | |
mdata<1> | 2 | 3 | FB2 | MC14 | LOW | SLOW | 8 | I/O | I/O | RESET |
mdata<2> | 2 | 3 | FB2 | MC15 | LOW | SLOW | 9 | I/O | I/O | RESET |
crc<0> | 11 | 8 | FB2 | MC16 | LOW | (b) | (b) | RESET | ||
mdata<3> | 2 | 3 | FB2 | MC17 | LOW | SLOW | 10 | I/O | I/O | RESET |
sel_byte<1> | 1 | 1 | FB3 | MC1 | LOW | (b) | (b) | RESET | ||
cclkp | 5 | 10 | FB3 | MC2 | LOW | SLOW | 23 | I/O/GCK2 | O | |
div<0> | 1 | 1 | FB3 | MC3 | LOW | (b) | (b) | RESET | ||
crc_10_or0000/crc_10_or0000_D2__$INT | 1 | 2 | FB3 | MC4 | LOW | (b) | (b) | |||
$OpTx$crc_7_xor0001/crc_7_xor0001_D2_INV$33 | 2 | 2 | FB3 | MC5 | LOW | 24 | I/O | I | ||
cclk_fbp | 1 | 1 | FB3 | MC6 | LOW | SLOW | 25 | I/O | O | |
$OpTx$crc_13_xor0001/crc_13_xor0001_D2_INV$30 | 2 | 2 | FB3 | MC7 | LOW | (b) | (b) | |||
$OpTx$crc_12_xor0001/crc_12_xor0001_D2_INV$29 | 2 | 2 | FB3 | MC8 | LOW | 27 | I/O/GCK3 | GCK/I | ||
$OpTx$crc_10_xor0003/crc_10_xor0003_D2_INV$28 | 2 | 2 | FB3 | MC9 | LOW | 28 | I/O | I | ||
$OpTx$crc_10_xor0003/crc_10_xor0003_D210__INV$35 | 2 | 2 | FB3 | MC10 | LOW | (b) | (b) | |||
$OpTx$crc_10_xor0001/crc_10_xor0001_D214__INV$38 | 2 | 2 | FB3 | MC11 | LOW | 29 | I/O | I | ||
$OpTx$crc_10_xor0001/crc_10_xor0001_D211__INV$36 | 2 | 2 | FB3 | MC12 | LOW | 30 | I/O | I | ||
ring_os<0> | 4 | 6 | FB3 | MC13 | LOW | (b) | (b) | |||
crc<22> | 4 | 5 | FB3 | MC14 | LOW | 32 | I/O | I | RESET | |
crc<2> | 5 | 6 | FB3 | MC15 | LOW | 33 | I/O | I | RESET | |
crc<21> | 5 | 6 | FB3 | MC16 | LOW | (b) | (b) | RESET | ||
crc<1> | 5 | 6 | FB3 | MC17 | LOW | 34 | I/O | (b) | RESET | |
crc<7> | 11 | 8 | FB3 | MC18 | LOW | (b) | (b) | RESET | ||
crc<12> | 5 | 6 | FB4 | MC1 | LOW | (b) | (b) | RESET | ||
maddr<4> | 6 | 12 | FB4 | MC2 | LOW | SLOW | 87 | I/O | O | RESET |
crc<10> | 11 | 8 | FB4 | MC3 | LOW | (b) | (b) | RESET | ||
maddr<5> | 6 | 13 | FB4 | MC5 | LOW | SLOW | 89 | I/O | O | RESET |
maddr<6> | 6 | 14 | FB4 | MC6 | LOW | SLOW | 90 | I/O | O | RESET |
en_loc_bus | 3 | 6 | FB4 | MC7 | LOW | (b) | (b) | RESET | ||
maddr<7> | 6 | 15 | FB4 | MC8 | LOW | SLOW | 91 | I/O | O | RESET |
maddr<12> | 6 | 20 | FB4 | MC9 | LOW | SLOW | 92 | I/O | O | RESET |
maddr<15> | 6 | 23 | FB4 | MC11 | LOW | SLOW | 93 | I/O | O | RESET |
maddr<16> | 6 | 24 | FB4 | MC12 | LOW | SLOW | 94 | I/O | O | RESET |
crc<18> | 7 | 7 | FB4 | MC13 | LOW | (b) | (b) | RESET | ||
maddr<18> | 0 | 0 | FB4 | MC14 | LOW | SLOW | 95 | I/O | O | |
mwe_b | 2 | 3 | FB4 | MC15 | LOW | SLOW | 96 | I/O | O | |
crc<14> | 11 | 8 | FB4 | MC16 | LOW | (b) | (b) | RESET | ||
maddr<17> | 6 | 25 | FB4 | MC17 | LOW | SLOW | 97 | I/O | O | RESET |
crc<17> | 7 | 7 | FB5 | MC1 | LOW | (b) | (b) | RESET | ||
loc_mode | 2 | 10 | FB5 | MC2 | LOW | 35 | I/O | I | RESET | |
crc<9> | 11 | 8 | FB5 | MC5 | LOW | 36 | I/O | I | RESET | |
crc<8> | 11 | 8 | FB5 | MC6 | LOW | 37 | I/O | I | RESET | |
loc_bus<0> | 9 | 14 | FB5 | MC9 | LOW | SLOW | 40 | I/O | I/O | |
crc<6> | 11 | 8 | FB5 | MC11 | LOW | 41 | I/O | (b) | RESET | |
loc_bus<1> | 9 | 14 | FB5 | MC12 | LOW | SLOW | 42 | I/O | I/O | |
prog | 2 | 10 | FB5 | MC14 | LOW | 43 | I/O | (b) | RESET | |
crc<23> | 11 | 8 | FB5 | MC16 | LOW | (b) | (b) | RESET | ||
crc<16> | 11 | 8 | FB5 | MC17 | LOW | 49 | I/O | (b) | RESET | |
crc<19> | 7 | 7 | FB6 | MC1 | LOW | (b) | (b) | RESET | ||
loc_add_out<4> | 1 | 1 | FB6 | MC2 | LOW | SLOW | 74 | I/O | O | RESET |
crc<4> | 7 | 7 | FB6 | MC3 | LOW | (b) | (b) | RESET | ||
crc<20> | 7 | 7 | FB6 | MC4 | LOW | (b) | (b) | RESET | ||
loc_add_out<3> | 1 | 1 | FB6 | MC5 | LOW | SLOW | 76 | I/O | O | RESET |
loc_add_out<2> | 1 | 1 | FB6 | MC6 | LOW | SLOW | 77 | I/O | O | RESET |
crc<5> | 11 | 8 | FB6 | MC7 | LOW | (b) | (b) | RESET | ||
loc_add_out<1> | 1 | 1 | FB6 | MC8 | LOW | SLOW | 78 | I/O | O | RESET |
loc_add_out<0> | 1 | 1 | FB6 | MC9 | LOW | SLOW | 79 | I/O | O | RESET |
maddr<3> | 6 | 11 | FB6 | MC12 | LOW | SLOW | 81 | I/O | O | RESET |
crc<15> | 11 | 8 | FB6 | MC13 | LOW | (b) | (b) | RESET | ||
maddr<2> | 6 | 10 | FB6 | MC14 | LOW | SLOW | 82 | I/O | O | RESET |
maddr<1> | 6 | 9 | FB6 | MC15 | LOW | SLOW | 85 | I/O | O | RESET |
maddr<0> | 6 | 8 | FB6 | MC17 | LOW | SLOW | 86 | I/O | O | RESET |
crc<13> | 5 | 6 | FB6 | MC18 | LOW | (b) | (b) | RESET | ||
loc_bus<2> | 9 | 13 | FB7 | MC2 | LOW | SLOW | 50 | I/O | I/O | |
loc_bus<3> | 9 | 14 | FB7 | MC5 | LOW | SLOW | 52 | I/O | I/O | |
spare3 | 1 | 2 | FB7 | MC6 | LOW | SLOW | 53 | I/O | O | |
loc_bus<4> | 9 | 14 | FB7 | MC8 | LOW | SLOW | 54 | I/O | I/O | |
loc_bus<5> | 9 | 14 | FB7 | MC11 | LOW | SLOW | 56 | I/O | I/O | |
spare5 | 1 | 2 | FB7 | MC12 | LOW | SLOW | 58 | I/O | O | |
loc_bus<6> | 9 | 14 | FB7 | MC14 | LOW | SLOW | 59 | I/O | I/O | |
loc_bus<7> | 8 | 13 | FB7 | MC17 | LOW | SLOW | 61 | I/O | I/O | |
prog_b | 1 | 2 | FB8 | MC2 | LOW | SLOW | 63 | I/O | O | |
ring_os<2> | 1 | 1 | FB8 | MC11 | LOW | 68 | I/O | I | ||
ring_os<1> | 1 | 1 | FB8 | MC12 | LOW | 70 | I/O | I | ||
div<4> | 1 | 1 | FB8 | MC13 | LOW | (b) | (b) | RESET | ||
loc_add_out<6> | 1 | 1 | FB8 | MC14 | LOW | SLOW | 71 | I/O | O | RESET |
loc_add_out<5> | 1 | 1 | FB8 | MC15 | LOW | SLOW | 72 | I/O | O | RESET |
div<3> | 1 | 1 | FB8 | MC16 | LOW | (b) | (b) | RESET | ||
div<2> | 1 | 1 | FB8 | MC17 | LOW | 73 | I/O | (b) | RESET | |
div<1> | 1 | 1 | FB8 | MC18 | LOW | (b) | (b) | RESET |