cpldfit:  version J.40                              Xilinx Inc.
                                  Fitter Report
Design Name: oslb_cpld                           Date:  1-30-2008,  4:41PM
Device Used: XC95144XL-10-TQ100
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
106/144 ( 74%) 494 /720  ( 69%) 303/432 ( 70%)   72 /144 ( 50%) 68 /81  ( 84%)

** Function Block Resources **

Function    Mcells      FB Inps     Pterms      IO          
Block       Used/Tot    Used/Tot    Used/Tot    Used/Tot    
FB1          16/18       44/54       54/90       9/11
FB2          15/18       43/54       71/90       9/10
FB3          18/18*      32/54       57/90       2/10
FB4          15/18       44/54       87/90      10/10*
FB5          10/18       42/54       84/90       2/10
FB6          15/18       36/54       77/90       9/10
FB7           8/18       52/54       55/90       8/10
FB8           9/18       10/54        9/90       3/10
             -----       -----       -----      -----    
            106/144     303/432     494/720     52/81 

* - Resource is exhausted

** Global Control Resources **

Signal 'cclk' mapped onto global clock net GCK1.
Signal 'loc_cs' mapped onto global clock net GCK3.
Global output enable net(s) unused.
Global set/reset net(s) unused.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :   14          14    |  I/O              :    60      73
Output        :   36          36    |  GCK/IO           :     3       3
Bidirectional :   16          16    |  GTS/IO           :     4       4
GCK           :    2           2    |  GSR/IO           :     1       1
GTS           :    0           0    |
GSR           :    0           0    |
                 ----        ----
        Total     68          68

** Power Data **

There are 0 macrocells in high performance mode (MCHP).
There are 106 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
*************************  Summary of Mapped Logic  ************************

** 52 Outputs **

Signal                                            Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
Name                                              Pts   Inps          No.  Type    Use     Mode Rate State
mdata<4>                                          2     3     FB1_2   11   I/O     I/O     LOW  SLOW RESET
mdata<5>                                          2     3     FB1_3   12   I/O     I/O     LOW  SLOW RESET
mdata<6>                                          2     3     FB1_5   13   I/O     I/O     LOW  SLOW RESET
mdata<7>                                          2     3     FB1_6   14   I/O     I/O     LOW  SLOW RESET
mce_b                                             3     12    FB1_8   15   I/O     O       LOW  SLOW 
maddr<10>                                         6     18    FB1_9   16   I/O     O       LOW  SLOW RESET
moe_b                                             2     3     FB1_11  17   I/O     O       LOW  SLOW 
rdwr_b                                            1     2     FB1_12  18   I/O     O       LOW  SLOW 
cs_b                                              2     4     FB1_15  20   I/O     O       LOW  SLOW 
maddr<14>                                         6     22    FB2_2   99   GSR/I/O O       LOW  SLOW RESET
maddr<13>                                         6     21    FB2_5   1    GTS/I/O O       LOW  SLOW RESET
maddr<8>                                          6     16    FB2_6   2    GTS/I/O O       LOW  SLOW RESET
maddr<9>                                          6     17    FB2_8   3    GTS/I/O O       LOW  SLOW RESET
maddr<11>                                         6     19    FB2_9   4    GTS/I/O O       LOW  SLOW RESET
mdata<0>                                          2     3     FB2_11  6    I/O     I/O     LOW  SLOW RESET
mdata<1>                                          2     3     FB2_14  8    I/O     I/O     LOW  SLOW RESET
mdata<2>                                          2     3     FB2_15  9    I/O     I/O     LOW  SLOW RESET
mdata<3>                                          2     3     FB2_17  10   I/O     I/O     LOW  SLOW RESET
cclkp                                             5     10    FB3_2   23   GCK/I/O O       LOW  SLOW 
cclk_fbp                                          1     1     FB3_6   25   I/O     O       LOW  SLOW 
maddr<4>                                          6     12    FB4_2   87   I/O     O       LOW  SLOW RESET
maddr<5>                                          6     13    FB4_5   89   I/O     O       LOW  SLOW RESET
maddr<6>                                          6     14    FB4_6   90   I/O     O       LOW  SLOW RESET
maddr<7>                                          6     15    FB4_8   91   I/O     O       LOW  SLOW RESET
maddr<12>                                         6     20    FB4_9   92   I/O     O       LOW  SLOW RESET
maddr<15>                                         6     23    FB4_11  93   I/O     O       LOW  SLOW RESET
maddr<16>                                         6     24    FB4_12  94   I/O     O       LOW  SLOW RESET
maddr<18>                                         0     0     FB4_14  95   I/O     O       LOW  SLOW 
mwe_b                                             2     3     FB4_15  96   I/O     O       LOW  SLOW 
maddr<17>                                         6     25    FB4_17  97   I/O     O       LOW  SLOW RESET
loc_bus<0>                                        9     14    FB5_9   40   I/O     I/O     LOW  SLOW 
loc_bus<1>                                        9     14    FB5_12  42   I/O     I/O     LOW  SLOW 
loc_add_out<4>                                    1     1     FB6_2   74   I/O     O       LOW  SLOW RESET
loc_add_out<3>                                    1     1     FB6_5   76   I/O     O       LOW  SLOW RESET
loc_add_out<2>                                    1     1     FB6_6   77   I/O     O       LOW  SLOW RESET
loc_add_out<1>                                    1     1     FB6_8   78   I/O     O       LOW  SLOW RESET
loc_add_out<0>                                    1     1     FB6_9   79   I/O     O       LOW  SLOW RESET
maddr<3>                                          6     11    FB6_12  81   I/O     O       LOW  SLOW RESET
maddr<2>                                          6     10    FB6_14  82   I/O     O       LOW  SLOW RESET
maddr<1>                                          6     9     FB6_15  85   I/O     O       LOW  SLOW RESET

Signal                                            Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
Name                                              Pts   Inps          No.  Type    Use     Mode Rate State
maddr<0>                                          6     8     FB6_17  86   I/O     O       LOW  SLOW RESET
loc_bus<2>                                        9     13    FB7_2   50   I/O     I/O     LOW  SLOW 
loc_bus<3>                                        9     14    FB7_5   52   I/O     I/O     LOW  SLOW 
spare3                                            1     2     FB7_6   53   I/O     O       LOW  SLOW 
loc_bus<4>                                        9     14    FB7_8   54   I/O     I/O     LOW  SLOW 
loc_bus<5>                                        9     14    FB7_11  56   I/O     I/O     LOW  SLOW 
spare5                                            1     2     FB7_12  58   I/O     O       LOW  SLOW 
loc_bus<6>                                        9     14    FB7_14  59   I/O     I/O     LOW  SLOW 
loc_bus<7>                                        8     13    FB7_17  61   I/O     I/O     LOW  SLOW 
prog_b                                            1     2     FB8_2   63   I/O     O       LOW  SLOW 
loc_add_out<6>                                    1     1     FB8_14  71   I/O     O       LOW  SLOW RESET
loc_add_out<5>                                    1     1     FB8_15  72   I/O     O       LOW  SLOW RESET

** 54 Buried Nodes **

Signal                                            Total Total Loc     Pwr  Reg Init
Name                                              Pts   Inps          Mode State
cfg_fail                                          3     21    FB1_4   LOW  RESET
$OpTx$mdata_and00004/mdata_and00004_D2_INV$34     2     3     FB1_7   LOW  
cfg_done                                          2     20    FB1_10  LOW  RESET
wr_maddr                                          2     8     FB1_13  LOW  RESET
powerup                                           1     1     FB1_14  LOW  SET
sel_byte<0>                                       1     1     FB1_16  LOW  RESET
en_conf                                           21    21    FB1_18  LOW  RESET
$OpTx$crc_17_xor0002/crc_17_xor0002_D2_INV$32     2     2     FB2_1   LOW  
$OpTx$crc_17_xor0002/crc_17_xor0002_D213__INV$37  2     2     FB2_3   LOW  
$OpTx$crc_16_xor0001/crc_16_xor0001_D2_INV$31     2     2     FB2_4   LOW  
crc<11>                                           5     6     FB2_7   LOW  RESET
crc<3>                                            11    8     FB2_12  LOW  RESET
crc<0>                                            11    8     FB2_16  LOW  RESET
sel_byte<1>                                       1     1     FB3_1   LOW  RESET
div<0>                                            1     1     FB3_3   LOW  RESET
crc_10_or0000/crc_10_or0000_D2__$INT              1     2     FB3_4   LOW  
$OpTx$crc_7_xor0001/crc_7_xor0001_D2_INV$33       2     2     FB3_5   LOW  
$OpTx$crc_13_xor0001/crc_13_xor0001_D2_INV$30     2     2     FB3_7   LOW  
$OpTx$crc_12_xor0001/crc_12_xor0001_D2_INV$29     2     2     FB3_8   LOW  
$OpTx$crc_10_xor0003/crc_10_xor0003_D2_INV$28     2     2     FB3_9   LOW  
$OpTx$crc_10_xor0003/crc_10_xor0003_D210__INV$35  2     2     FB3_10  LOW  
$OpTx$crc_10_xor0001/crc_10_xor0001_D214__INV$38  2     2     FB3_11  LOW  
$OpTx$crc_10_xor0001/crc_10_xor0001_D211__INV$36  2     2     FB3_12  LOW  
ring_os<0>                                        4     6     FB3_13  LOW  
crc<22>                                           4     5     FB3_14  LOW  RESET
crc<2>                                            5     6     FB3_15  LOW  RESET
crc<21>                                           5     6     FB3_16  LOW  RESET
crc<1>                                            5     6     FB3_17  LOW  RESET
crc<7>                                            11    8     FB3_18  LOW  RESET
crc<12>                                           5     6     FB4_1   LOW  RESET
crc<10>                                           11    8     FB4_3   LOW  RESET
en_loc_bus                                        3     6     FB4_7   LOW  RESET
crc<18>                                           7     7     FB4_13  LOW  RESET
crc<14>                                           11    8     FB4_16  LOW  RESET
crc<17>                                           7     7     FB5_1   LOW  RESET
loc_mode                                          2     10    FB5_2   LOW  RESET
crc<9>                                            11    8     FB5_5   LOW  RESET
crc<8>                                            11    8     FB5_6   LOW  RESET
crc<6>                                            11    8     FB5_11  LOW  RESET
prog                                              2     10    FB5_14  LOW  RESET

Signal                                            Total Total Loc     Pwr  Reg Init
Name                                              Pts   Inps          Mode State
crc<23>                                           11    8     FB5_16  LOW  RESET
crc<16>                                           11    8     FB5_17  LOW  RESET
crc<19>                                           7     7     FB6_1   LOW  RESET
crc<4>                                            7     7     FB6_3   LOW  RESET
crc<20>                                           7     7     FB6_4   LOW  RESET
crc<5>                                            11    8     FB6_7   LOW  RESET
crc<15>                                           11    8     FB6_13  LOW  RESET
crc<13>                                           5     6     FB6_18  LOW  RESET
ring_os<2>                                        1     1     FB8_11  LOW  
ring_os<1>                                        1     1     FB8_12  LOW  
div<4>                                            1     1     FB8_13  LOW  RESET
div<3>                                            1     1     FB8_16  LOW  RESET
div<2>                                            1     1     FB8_17  LOW  RESET
div<1>                                            1     1     FB8_18  LOW  RESET

** 16 Inputs **

Signal                                            Loc     Pin  Pin     Pin     
Name                                                      No.  Type    Use     
cclk                                              FB1_17  22   GCK/I/O GCK
cclk_fb                                           FB3_5   24   I/O     I
loc_cs                                            FB3_8   27   GCK/I/O GCK/I
loc_rw                                            FB3_9   28   I/O     I
loc_add<0>                                        FB3_11  29   I/O     I
loc_add<1>                                        FB3_12  30   I/O     I
loc_add<2>                                        FB3_14  32   I/O     I
loc_add<3>                                        FB3_15  33   I/O     I
loc_add<4>                                        FB5_2   35   I/O     I
loc_add<5>                                        FB5_5   36   I/O     I
loc_add<6>                                        FB5_6   37   I/O     I
init_b                                            FB8_6   65   I/O     I
done                                              FB8_8   66   I/O     I
ctrl_in<2>                                        FB8_9   67   I/O     I
ctrl_in<0>                                        FB8_11  68   I/O     I
ctrl_in<1>                                        FB8_12  70   I/O     I

Legend:
Pin No. - ~ - User Assigned
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X            - Signal used as input to the macrocell logic.
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
Number of function block inputs used/remaining:               44/10
Number of signals used by logic mapping into function block:  44
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0   /\5   0     FB1_1         (b)     (b)
mdata<4>              2       0   /\3   0     FB1_2   11    I/O     I/O
mdata<5>              2       0     0   3     FB1_3   12    I/O     I/O
cfg_fail              3       0     0   2     FB1_4         (b)     (b)
mdata<6>              2       0     0   3     FB1_5   13    I/O     I/O
mdata<7>              2       0     0   3     FB1_6   14    I/O     I/O
$OpTx$mdata_and00004/mdata_and00004_D2_INV$34
                      2       0     0   3     FB1_7         (b)     (b)
mce_b                 3       0   \/1   1     FB1_8   15    I/O     O
maddr<10>             6       1<-   0   0     FB1_9   16    I/O     O
cfg_done              2       0     0   3     FB1_10        (b)     (b)
moe_b                 2       0     0   3     FB1_11  17    I/O     O
rdwr_b                1       0     0   4     FB1_12  18    I/O     O
wr_maddr              2       0     0   3     FB1_13        (b)     (b)
powerup               1       0     0   4     FB1_14  19    I/O     (b)
cs_b                  2       0     0   3     FB1_15  20    I/O     O
sel_byte<0>           1       0   \/3   1     FB1_16        (b)     (b)
(unused)              0       0   \/5   0     FB1_17  22    GCK/I/O GCK
en_conf              21      16<-   0   0     FB1_18        (b)     (b)

Signals Used by Logic in Function Block
  1: $OpTx$mdata_and00004/mdata_and00004_D2_INV$34  16: loc_add<4>        31: maddr<1> 
  2: loc_bus<5>.PIN                                 17: loc_add<5>        32: maddr<2> 
  3: loc_bus<4>.PIN                                 18: loc_add<6>        33: maddr<3> 
  4: loc_bus<7>.PIN                                 19: loc_cs            34: maddr<4> 
  5: loc_bus<6>.PIN                                 20: loc_mode          35: maddr<5> 
  6: cfg_done                                       21: loc_rw            36: maddr<6> 
  7: ctrl_in<0>                                     22: maddr<0>          37: maddr<7> 
  8: ctrl_in<1>                                     23: maddr<10>         38: maddr<8> 
  9: done                                           24: maddr<11>         39: maddr<9> 
 10: en_conf                                        25: maddr<12>         40: mdata<2> 
 11: init_b                                         26: maddr<13>         41: prog 
 12: loc_add<0>                                     27: maddr<14>         42: sel_byte<0> 
 13: loc_add<1>                                     28: maddr<15>         43: sel_byte<1> 
 14: loc_add<2>                                     29: maddr<16>         44: wr_maddr 
 15: loc_add<3>                                     30: maddr<17>        

Signal                        1         2         3         4         5 FB
Name                0----+----0----+----0----+----0----+----0----+----0 Inputs
mdata<4>             X.X.................X............................. 3
mdata<5>             XX..................X............................. 3
cfg_fail             .....X...X...........XXXXXXXXXXXXXXXXXX.X......... 21
mdata<6>             X...X...............X............................. 3
mdata<7>             X..X................X............................. 3
$OpTx$mdata_and00004/mdata_and00004_D2_INV$34 
                     .......XX..........X.............................. 3
mce_b                .....XXX...XXXXXXXXX.............................. 12
maddr<10>            .....X.X.............XX.......XXXXXXXXXXXXXX...... 18
cfg_done             ........X............XXXXXXXXXXXXXXXXXX.X......... 20
moe_b                .....X.X............X............................. 3
rdwr_b               .....X..............X............................. 2
wr_maddr             .....X.X.....XXXXX..X............................. 8
powerup              .................................X................ 1
cs_b                 .....X...XX.......X............................... 4
sel_byte<0>          ...........X...................................... 1
en_conf              .........X.........X.XXXXXXXXXXXXXXXXXX.X......... 21
                    0----+----1----+----2----+----3----+----4----+----5
                              0         0         0         0         0
*********************************** FB2  ***********************************
Number of function block inputs used/remaining:               43/11
Number of signals used by logic mapping into function block:  43
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
$OpTx$crc_17_xor0002/crc_17_xor0002_D2_INV$32
                      2       0   \/1   2     FB2_1         (b)     (b)
maddr<14>             6       1<-   0   0     FB2_2   99    GSR/I/O O
$OpTx$crc_17_xor0002/crc_17_xor0002_D213__INV$37
                      2       0     0   3     FB2_3         (b)     (b)
$OpTx$crc_16_xor0001/crc_16_xor0001_D2_INV$31
                      2       0   \/2   1     FB2_4         (b)     (b)
maddr<13>             6       2<- \/1   0     FB2_5   1     GTS/I/O O
maddr<8>              6       1<-   0   0     FB2_6   2     GTS/I/O O
crc<11>               5       0     0   0     FB2_7         (b)     (b)
maddr<9>              6       1<-   0   0     FB2_8   3     GTS/I/O O
maddr<11>             6       2<- /\1   0     FB2_9   4     GTS/I/O O
(unused)              0       0   /\2   3     FB2_10        (b)     (b)
mdata<0>              2       0   \/3   0     FB2_11  6     I/O     I/O
crc<3>               11       6<-   0   0     FB2_12  7     I/O     (b)
(unused)              0       0   /\3   2     FB2_13        (b)     (b)
mdata<1>              2       0     0   3     FB2_14  8     I/O     I/O
mdata<2>              2       0   \/3   0     FB2_15  9     I/O     I/O
crc<0>               11       6<-   0   0     FB2_16        (b)     (b)
mdata<3>              2       0   /\3   0     FB2_17  10    I/O     I/O
(unused)              0       0     0   5     FB2_18        (b)     

Signals Used by Logic in Function Block
  1: $OpTx$crc_10_xor0001/crc_10_xor0001_D214__INV$38  16: crc_10_or0000/crc_10_or0000_D2__$INT  30: maddr<5> 
  2: $OpTx$crc_12_xor0001/crc_12_xor0001_D2_INV$29     17: ctrl_in<1>                            31: maddr<6> 
  3: $OpTx$mdata_and00004/mdata_and00004_D2_INV$34     18: en_conf                               32: maddr<7> 
  4: loc_bus<3>.PIN                                    19: loc_rw                                33: maddr<8> 
  5: loc_bus<2>.PIN                                    20: maddr<0>                              34: maddr<9> 
  6: loc_bus<1>.PIN                                    21: maddr<10>                             35: mdata<0> 
  7: loc_bus<0>.PIN                                    22: maddr<11>                             36: mdata<1> 
  8: mdata<3>.PIN                                      23: maddr<12>                             37: mdata<3> 
  9: mdata<0>.PIN                                      24: maddr<13>                             38: mdata<5> 
 10: cfg_done                                          25: maddr<14>                             39: mdata<6> 
 11: crc<16>                                           26: maddr<1>                              40: prog 
 12: crc<18>                                           27: maddr<2>                              41: sel_byte<0> 
 13: crc<19>                                           28: maddr<3>                              42: sel_byte<1> 
 14: crc<20>                                           29: maddr<4>                              43: wr_maddr 
 15: crc<3>                                           

Signal                        1         2         3         4         5 FB
Name                0----+----0----+----0----+----0----+----0----+----0 Inputs
$OpTx$crc_17_xor0002/crc_17_xor0002_D2_INV$32 
                     ..........XX...................................... 2
maddr<14>            .........X......X..XXXXXXXXXXXXXXX....XXXXX....... 22
$OpTx$crc_17_xor0002/crc_17_xor0002_D213__INV$37 
                     ..........XX...................................... 2
$OpTx$crc_16_xor0001/crc_16_xor0001_D2_INV$31 
                     ............XX.................................... 2
maddr<13>            .........X......X..XXXXX.XXXXXXXXX...X.XXXX....... 21
maddr<8>             .........X......X..X.....XXXXXXXX.X....XXXX....... 16
crc<11>              .........XX..XXX.X................................ 6
maddr<9>             .........X......X..X.....XXXXXXXXX.X...XXXX....... 17
maddr<11>            .........X......X..XXX...XXXXXXXXX..X..XXXX....... 19
mdata<0>             ..X...X...........X............................... 3
crc<3>               .X.....X.XX.XX.X.X................................ 8
mdata<1>             ..X..X............X............................... 3
mdata<2>             ..X.X.............X............................... 3
crc<0>               XX......XX.XX..X.X................................ 8
mdata<3>             ..XX..............X............................... 3
                    0----+----1----+----2----+----3----+----4----+----5
                              0         0         0         0         0
*********************************** FB3  ***********************************
Number of function block inputs used/remaining:               32/22
Number of signals used by logic mapping into function block:  32
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
sel_byte<1>           1       1<- /\5   0     FB3_1         (b)     (b)
cclkp                 5       1<- /\1   0     FB3_2   23    GCK/I/O O
div<0>                1       0   /\1   3     FB3_3         (b)     (b)
crc_10_or0000/crc_10_or0000_D2__$INT
                      1       0     0   4     FB3_4         (b)     (b)
$OpTx$crc_7_xor0001/crc_7_xor0001_D2_INV$33
                      2       0     0   3     FB3_5   24    I/O     I
cclk_fbp              1       0     0   4     FB3_6   25    I/O     O
$OpTx$crc_13_xor0001/crc_13_xor0001_D2_INV$30
                      2       0     0   3     FB3_7         (b)     (b)
$OpTx$crc_12_xor0001/crc_12_xor0001_D2_INV$29
                      2       0     0   3     FB3_8   27    GCK/I/O GCK/I
$OpTx$crc_10_xor0003/crc_10_xor0003_D2_INV$28
                      2       0     0   3     FB3_9   28    I/O     I
$OpTx$crc_10_xor0003/crc_10_xor0003_D210__INV$35
                      2       0     0   3     FB3_10        (b)     (b)
$OpTx$crc_10_xor0001/crc_10_xor0001_D214__INV$38
                      2       0     0   3     FB3_11  29    I/O     I
$OpTx$crc_10_xor0001/crc_10_xor0001_D211__INV$36
                      2       0     0   3     FB3_12  30    I/O     I
ring_os<0>            4       0     0   1     FB3_13        (b)     (b)
crc<22>               4       0   \/1   0     FB3_14  32    I/O     I
crc<2>                5       1<- \/1   0     FB3_15  33    I/O     I
crc<21>               5       1<- \/1   0     FB3_16        (b)     (b)
crc<1>                5       1<- \/1   0     FB3_17  34    I/O     (b)
crc<7>               11       6<-   0   0     FB3_18        (b)     (b)

Signals Used by Logic in Function Block
  1: $OpTx$crc_10_xor0003/crc_10_xor0003_D2_INV$28  12: crc<17>                               23: en_conf 
  2: $OpTx$crc_7_xor0001/crc_7_xor0001_D2_INV$33    13: crc<18>                               24: loc_add<1> 
  3: mdata<7>.PIN                                   14: crc<19>                               25: loc_add<5> 
  4: mdata<2>.PIN                                   15: crc<20>                               26: loc_add<6> 
  5: mdata<1>.PIN                                   16: crc<21>                               27: loc_cs 
  6: cclk_fb                                        17: crc<22>                               28: loc_mode 
  7: cfg_done                                       18: crc<23>                               29: loc_rw 
  8: cfg_fail                                       19: crc_10_or0000/crc_10_or0000_D2__$INT  30: powerup 
  9: crc<13>                                        20: ctrl_in<0>                            31: prog 
 10: crc<14>                                        21: ctrl_in<1>                            32: ring_os<2> 
 11: crc<16>                                        22: div<4>                               

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
sel_byte<1>          .......................X................ 1
cclkp                ......X............XXX..XXXXX.X......... 10
div<0>               .....X.................................. 1
crc_10_or0000/crc_10_or0000_D2__$INT 
                     .............................XX......... 2
$OpTx$crc_7_xor0001/crc_7_xor0001_D2_INV$33 
                     ...............XX....................... 2
cclk_fbp             ...............................X........ 1
$OpTx$crc_13_xor0001/crc_13_xor0001_D2_INV$30 
                     ............X...X....................... 2
$OpTx$crc_12_xor0001/crc_12_xor0001_D2_INV$29 
                     ...........X...X........................ 2
$OpTx$crc_10_xor0003/crc_10_xor0003_D2_INV$28 
                     ............X....X...................... 2
$OpTx$crc_10_xor0003/crc_10_xor0003_D210__INV$35 
                     ............X....X...................... 2
$OpTx$crc_10_xor0001/crc_10_xor0001_D214__INV$38 
                     ..........X...X......................... 2
$OpTx$crc_10_xor0001/crc_10_xor0001_D211__INV$36 
                     ..........X...X......................... 2
ring_os<0>           .....XXX............XX.....X............ 6
crc<22>              ......X..X....X...X...X................. 5
crc<2>               ...X..X....X.....XX...X................. 6
crc<21>              ......X.X....X...XX...X................. 6
crc<1>               ....X.X...X.....X.X...X................. 6
crc<7>               XXX...X...X...X...X...X................. 8
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB4  ***********************************
Number of function block inputs used/remaining:               44/10
Number of signals used by logic mapping into function block:  44
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
crc<12>               5       0     0   0     FB4_1         (b)     (b)
maddr<4>              6       1<-   0   0     FB4_2   87    I/O     O
crc<10>              11       7<- /\1   0     FB4_3         (b)     (b)
(unused)              0       0   /\5   0     FB4_4         (b)     (b)
maddr<5>              6       3<- /\2   0     FB4_5   89    I/O     O
maddr<6>              6       4<- /\3   0     FB4_6   90    I/O     O
en_loc_bus            3       2<- /\4   0     FB4_7         (b)     (b)
maddr<7>              6       3<- /\2   0     FB4_8   91    I/O     O
maddr<12>             6       4<- /\3   0     FB4_9   92    I/O     O
(unused)              0       0   /\4   1     FB4_10        (b)     (b)
maddr<15>             6       1<-   0   0     FB4_11  93    I/O     O
maddr<16>             6       2<- /\1   0     FB4_12  94    I/O     O
crc<18>               7       4<- /\2   0     FB4_13        (b)     (b)
maddr<18>             0       0   /\4   1     FB4_14  95    I/O     O
mwe_b                 2       0   \/3   0     FB4_15  96    I/O     O
crc<14>              11       6<-   0   0     FB4_16        (b)     (b)
maddr<17>             6       4<- /\3   0     FB4_17  97    I/O     O
(unused)              0       0   /\4   1     FB4_18        (b)     (b)

Signals Used by Logic in Function Block
  1: $OpTx$crc_10_xor0001/crc_10_xor0001_D211__INV$36  16: loc_rw            31: maddr<6> 
  2: $OpTx$crc_10_xor0003/crc_10_xor0003_D210__INV$35  17: maddr<0>          32: maddr<7> 
  3: cfg_done                                          18: maddr<10>         33: maddr<8> 
  4: crc<10>                                           19: maddr<11>         34: maddr<9> 
  5: crc<16>                                           20: maddr<12>         35: mdata<0> 
  6: crc<17>                                           21: maddr<13>         36: mdata<1> 
  7: crc<20>                                           22: maddr<14>         37: mdata<4> 
  8: crc<21>                                           23: maddr<15>         38: mdata<5> 
  9: crc<2>                                            24: maddr<16>         39: mdata<6> 
 10: crc<4>                                            25: maddr<17>         40: mdata<7> 
 11: crc<6>                                            26: maddr<1>          41: prog 
 12: crc_10_or0000/crc_10_or0000_D2__$INT              27: maddr<2>          42: sel_byte<0> 
 13: ctrl_in<1>                                        28: maddr<3>          43: sel_byte<1> 
 14: en_conf                                           29: maddr<4>          44: wr_maddr 
 15: en_loc_bus                                        30: maddr<5>         

Signal                        1         2         3         4         5 FB
Name                0----+----0----+----0----+----0----+----0----+----0 Inputs
crc<12>              ..X..X.X.X.X.X.................................... 6
maddr<4>             ..X.........X...X........XXXX.......X...XXXX...... 12
crc<10>              .XX.XXX.X..X.X.................................... 8
maddr<5>             ..X.........X...X........XXXXX.......X..XXXX...... 13
maddr<6>             ..X.........X...X........XXXXXX.......X.XXXX...... 14
en_loc_bus           ..X..........XX.......XXX......................... 6
maddr<7>             ..X.........X...X........XXXXXXX.......XXXXX...... 15
maddr<12>            ..X.........X...XXXX.....XXXXXXXXX..X...XXXX...... 20
maddr<15>            ..X.........X...XXXXXXX..XXXXXXXXX.....XXXXX...... 23
maddr<16>            ..X.........X...XXXXXXXX.XXXXXXXXXX.....XXXX...... 24
crc<18>              ..XXX.XX...X.X.................................... 7
maddr<18>            .................................................. 0
mwe_b                ..X.........X..X.................................. 3
crc<14>              XXX..X.X..XX.X.................................... 8
maddr<17>            ..X.........X...XXXXXXXXXXXXXXXXXX.X....XXXX...... 25
                    0----+----1----+----2----+----3----+----4----+----5
                              0         0         0         0         0
*********************************** FB5  ***********************************
Number of function block inputs used/remaining:               42/12
Number of signals used by logic mapping into function block:  42
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
crc<17>               7       2<-   0   0     FB5_1         (b)     (b)
loc_mode              2       0   /\2   1     FB5_2   35    I/O     I
(unused)              0       0   \/2   3     FB5_3         (b)     (b)
(unused)              0       0   \/5   0     FB5_4         (b)     (b)
crc<9>               11       7<- \/1   0     FB5_5   36    I/O     I
crc<8>               11       6<-   0   0     FB5_6   37    I/O     I
(unused)              0       0   /\5   0     FB5_7         (b)     (b)
(unused)              0       0   \/4   1     FB5_8   39    I/O     (b)
loc_bus<0>            9       4<-   0   0     FB5_9   40    I/O     I/O
(unused)              0       0   \/5   0     FB5_10        (b)     (b)
crc<6>               11       6<-   0   0     FB5_11  41    I/O     (b)
loc_bus<1>            9       5<- /\1   0     FB5_12  42    I/O     I/O
(unused)              0       0   /\5   0     FB5_13        (b)     (b)
prog                  2       0   \/2   1     FB5_14  43    I/O     (b)
(unused)              0       0   \/5   0     FB5_15  46    I/O     (b)
crc<23>              11       7<- \/1   0     FB5_16        (b)     (b)
crc<16>              11       6<-   0   0     FB5_17  49    I/O     (b)
(unused)              0       0   /\5   0     FB5_18        (b)     (b)

Signals Used by Logic in Function Block
  1: $OpTx$crc_16_xor0001/crc_16_xor0001_D2_INV$31     15: crc<19>                               29: loc_add<3> 
  2: $OpTx$crc_17_xor0002/crc_17_xor0002_D213__INV$37  16: crc<1>                                30: loc_add<4> 
  3: $OpTx$crc_7_xor0001/crc_7_xor0001_D2_INV$33       17: crc<20>                               31: loc_add<5> 
  4: mdata<6>.PIN                                      18: crc<21>                               32: loc_add<6> 
  5: loc_bus<1>.PIN                                    19: crc<22>                               33: loc_cs 
  6: loc_bus<0>.PIN                                    20: crc<23>                               34: loc_mode 
  7: mdata<1>.PIN                                      21: crc<8>                                35: loc_rw 
  8: mdata<0>.PIN                                      22: crc<9>                                36: maddr<0> 
  9: cfg_done                                          23: crc_10_or0000/crc_10_or0000_D2__$INT  37: maddr<16> 
 10: crc<0>                                            24: en_conf                               38: maddr<17> 
 11: crc<15>                                           25: en_loc_bus                            39: maddr<1> 
 12: crc<16>                                           26: loc_add<0>                            40: maddr<8> 
 13: crc<17>                                           27: loc_add<1>                            41: maddr<9> 
 14: crc<18>                                           28: loc_add<2>                            42: prog 

Signal                        1         2         3         4         5 FB
Name                0----+----0----+----0----+----0----+----0----+----0 Inputs
crc<17>              ........X..X.X.....X.XXX.......................... 7
loc_mode             .....X..................XXXXXXXX..X............... 10
crc<9>               ........X....X.XX.XX..XX.......................... 8
crc<8>               ..X.....XX..X.X....X..XX.......................... 8
loc_bus<0>           .......X.X.X........X....XX...XXXXXXX..X.......... 14
crc<6>               ...X....X..X.X...XX...XX.......................... 8
loc_bus<1>           ......X.....X..X.....X...XX...XXX.X..XX.XX........ 14
prog                 ....X...................XXXXXXXX..X............... 10
crc<23>              .X......X.X.X.X.X.....XX.......................... 8
crc<16>              X.......X....X....XXX.XX.......................... 8
                    0----+----1----+----2----+----3----+----4----+----5
                              0         0         0         0         0
*********************************** FB6  ***********************************
Number of function block inputs used/remaining:               36/18
Number of signals used by logic mapping into function block:  36
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
crc<19>               7       3<- /\1   0     FB6_1         (b)     (b)
loc_add_out<4>        1       0   /\3   1     FB6_2   74    I/O     O
crc<4>                7       2<-   0   0     FB6_3         (b)     (b)
crc<20>               7       4<- /\2   0     FB6_4         (b)     (b)
loc_add_out<3>        1       0   /\4   0     FB6_5   76    I/O     O
loc_add_out<2>        1       0   \/2   2     FB6_6   77    I/O     O
crc<5>               11       6<-   0   0     FB6_7         (b)     (b)
loc_add_out<1>        1       0   /\4   0     FB6_8   78    I/O     O
loc_add_out<0>        1       0     0   4     FB6_9   79    I/O     O
(unused)              0       0     0   5     FB6_10        (b)     
(unused)              0       0   \/5   0     FB6_11  80    I/O     (b)
maddr<3>              6       5<- \/4   0     FB6_12  81    I/O     O
crc<15>              11       6<-   0   0     FB6_13        (b)     (b)
maddr<2>              6       3<- /\2   0     FB6_14  82    I/O     O
maddr<1>              6       4<- /\3   0     FB6_15  85    I/O     O
(unused)              0       0   /\4   1     FB6_16        (b)     (b)
maddr<0>              6       1<-   0   0     FB6_17  86    I/O     O
crc<13>               5       1<- /\1   0     FB6_18        (b)     (b)

Signals Used by Logic in Function Block
  1: $OpTx$crc_13_xor0001/crc_13_xor0001_D2_INV$30  13: crc<22>                               25: maddr<0> 
  2: $OpTx$crc_17_xor0002/crc_17_xor0002_D2_INV$32  14: crc<23>                               26: maddr<1> 
  3: mdata<5>.PIN                                   15: crc<5>                                27: maddr<2> 
  4: mdata<4>.PIN                                   16: crc<7>                                28: maddr<3> 
  5: cfg_done                                       17: crc_10_or0000/crc_10_or0000_D2__$INT  29: mdata<0> 
  6: crc<11>                                        18: ctrl_in<1>                            30: mdata<1> 
  7: crc<12>                                        19: en_conf                               31: mdata<2> 
  8: crc<16>                                        20: loc_add<0>                            32: mdata<3> 
  9: crc<17>                                        21: loc_add<1>                            33: prog 
 10: crc<18>                                        22: loc_add<2>                            34: sel_byte<0> 
 11: crc<19>                                        23: loc_add<3>                            35: sel_byte<1> 
 12: crc<21>                                        24: loc_add<4>                            36: wr_maddr 

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
crc<19>              ....XX..X..XX...X.X..................... 7
loc_add_out<4>       .......................X................ 1
crc<4>               ...XX..X..X.X...X.X..................... 7
crc<20>              ....X.X..X..XX..X.X..................... 7
loc_add_out<3>       ......................X................. 1
loc_add_out<2>       .....................X.................. 1
crc<5>               .XX.X.....XX.X..X.X..................... 8
loc_add_out<1>       ....................X................... 1
loc_add_out<0>       ...................X.................... 1
maddr<3>             ....X............X......XXXX...XXXXX.... 11
crc<15>              X...X...X.XX...XX.X..................... 8
maddr<2>             ....X............X......XXX...X.XXXX.... 10
maddr<1>             ....X............X......XX...X..XXXX.... 9
maddr<0>             ....X............X......X...X...XXXX.... 8
crc<13>              ....X....X..X.X.X.X..................... 6
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB7  ***********************************
Number of function block inputs used/remaining:               52/2
Number of signals used by logic mapping into function block:  52
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0   \/2   3     FB7_1         (b)     (b)
loc_bus<2>            9       4<-   0   0     FB7_2   50    I/O     I/O
(unused)              0       0   /\2   3     FB7_3         (b)     (b)
(unused)              0       0   \/2   3     FB7_4         (b)     (b)
loc_bus<3>            9       4<-   0   0     FB7_5   52    I/O     I/O
spare3                1       0   /\2   2     FB7_6   53    I/O     O
(unused)              0       0   \/2   3     FB7_7         (b)     (b)
loc_bus<4>            9       4<-   0   0     FB7_8   54    I/O     I/O
(unused)              0       0   /\2   3     FB7_9   55    I/O     (b)
(unused)              0       0   \/2   3     FB7_10        (b)     (b)
loc_bus<5>            9       4<-   0   0     FB7_11  56    I/O     I/O
spare5                1       0   /\2   2     FB7_12  58    I/O     O
(unused)              0       0   \/2   3     FB7_13        (b)     (b)
loc_bus<6>            9       4<-   0   0     FB7_14  59    I/O     I/O
(unused)              0       0   /\2   3     FB7_15  60    I/O     (b)
(unused)              0       0   \/2   3     FB7_16        (b)     (b)
loc_bus<7>            8       3<-   0   0     FB7_17  61    I/O     I/O
(unused)              0       0   /\1   4     FB7_18        (b)     (b)

Signals Used by Logic in Function Block
  1: mdata<7>.PIN      19: crc<22>           36: loc_add<1> 
  2: mdata<6>.PIN      20: crc<23>           37: loc_add<5> 
  3: mdata<5>.PIN      21: crc<2>            38: loc_add<6> 
  4: mdata<4>.PIN      22: crc<3>            39: loc_cs 
  5: mdata<3>.PIN      23: crc<4>            40: loc_rw 
  6: mdata<2>.PIN      24: crc<5>            41: maddr<10> 
  7: cfg_done          25: crc<6>            42: maddr<11> 
  8: cfg_fail          26: crc<7>            43: maddr<12> 
  9: crc<10>           27: ctrl_in<0>        44: maddr<13> 
 10: crc<11>           28: ctrl_in<1>        45: maddr<14> 
 11: crc<12>           29: ctrl_in<2>        46: maddr<15> 
 12: crc<13>           30: div<4>            47: maddr<2> 
 13: crc<14>           31: done              48: maddr<3> 
 14: crc<15>           32: en_conf           49: maddr<4> 
 15: crc<18>           33: en_loc_bus        50: maddr<5> 
 16: crc<19>           34: init_b            51: maddr<6> 
 17: crc<20>           35: loc_add<0>        52: maddr<7> 
 18: crc<21>          

Signal                        1         2         3         4         5         6 FB
Name                0----+----0----+----0----+----0----+----0----+----0----+----0 Inputs
loc_bus<2>           .....X..X.....X.....X............XXXXXXXX.....X............. 13
loc_bus<3>           ....X..X.X.....X.....X........X...XXXXXX.X.....X............ 14
spare3               ......X......................X.............................. 2
loc_bus<4>           ...X...X..X.....X.....X...X.......XXXXXX..X.....X........... 14
loc_bus<5>           ..X...X....X.....X.....X...X......XXXXXX...X.....X.......... 14
spare5               ......X...............................X..................... 2
loc_bus<6>           .X..........X.....X.....X...X...X.XXXXXX....X.....X......... 14
loc_bus<7>           X............X.....X.....X.....X..XXXXXX.....X.....X........ 13
                    0----+----1----+----2----+----3----+----4----+----5----+----6
                              0         0         0         0         0         0
*********************************** FB8  ***********************************
Number of function block inputs used/remaining:               10/44
Number of signals used by logic mapping into function block:  10
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB8_1         (b)     
prog_b                1       0     0   4     FB8_2   63    I/O     O
(unused)              0       0     0   5     FB8_3         (b)     
(unused)              0       0     0   5     FB8_4         (b)     
(unused)              0       0     0   5     FB8_5   64    I/O     
(unused)              0       0     0   5     FB8_6   65    I/O     I
(unused)              0       0     0   5     FB8_7         (b)     
(unused)              0       0     0   5     FB8_8   66    I/O     I
(unused)              0       0     0   5     FB8_9   67    I/O     I
(unused)              0       0     0   5     FB8_10        (b)     
ring_os<2>            1       0     0   4     FB8_11  68    I/O     I
ring_os<1>            1       0     0   4     FB8_12  70    I/O     I
div<4>                1       0     0   4     FB8_13        (b)     (b)
loc_add_out<6>        1       0     0   4     FB8_14  71    I/O     O
loc_add_out<5>        1       0     0   4     FB8_15  72    I/O     O
div<3>                1       0     0   4     FB8_16        (b)     (b)
div<2>                1       0     0   4     FB8_17  73    I/O     (b)
div<1>                1       0     0   4     FB8_18        (b)     (b)

Signals Used by Logic in Function Block
  1: div<0>             5: loc_add<5>         8: prog 
  2: div<1>             6: loc_add<6>         9: ring_os<0> 
  3: div<2>             7: powerup           10: ring_os<1> 
  4: div<3>           

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
prog_b               ......XX................................ 2
ring_os<2>           .........X.............................. 1
ring_os<1>           ........X............................... 1
div<4>               ...X.................................... 1
loc_add_out<6>       .....X.................................. 1
loc_add_out<5>       ....X................................... 1
div<3>               ..X..................................... 1
div<2>               .X...................................... 1
div<1>               X....................................... 1
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*******************************  Equations  ********************************

********** Mapped Logic **********


$OpTx$crc_10_xor0001/crc_10_xor0001_D211__INV$36 <= NOT (crc(16)
	 XOR 
$OpTx$crc_10_xor0001/crc_10_xor0001_D211__INV$36 <= NOT (crc(20));


$OpTx$crc_10_xor0001/crc_10_xor0001_D214__INV$38 <= NOT (crc(16)
	 XOR 
$OpTx$crc_10_xor0001/crc_10_xor0001_D214__INV$38 <= NOT (crc(20));


$OpTx$crc_10_xor0003/crc_10_xor0003_D210__INV$35 <= NOT (crc(18)
	 XOR 
$OpTx$crc_10_xor0003/crc_10_xor0003_D210__INV$35 <= NOT (crc(23));


$OpTx$crc_10_xor0003/crc_10_xor0003_D2_INV$28 <= NOT (crc(18)
	 XOR 
$OpTx$crc_10_xor0003/crc_10_xor0003_D2_INV$28 <= NOT (crc(23));


$OpTx$crc_12_xor0001/crc_12_xor0001_D2_INV$29 <= NOT (crc(17)
	 XOR 
$OpTx$crc_12_xor0001/crc_12_xor0001_D2_INV$29 <= NOT (crc(21));


$OpTx$crc_13_xor0001/crc_13_xor0001_D2_INV$30 <= NOT (crc(22)
	 XOR 
$OpTx$crc_13_xor0001/crc_13_xor0001_D2_INV$30 <= NOT (crc(18));


$OpTx$crc_16_xor0001/crc_16_xor0001_D2_INV$31 <= NOT (crc(19)
	 XOR 
$OpTx$crc_16_xor0001/crc_16_xor0001_D2_INV$31 <= NOT (crc(20));


$OpTx$crc_17_xor0002/crc_17_xor0002_D213__INV$37 <= NOT (crc(16)
	 XOR 
$OpTx$crc_17_xor0002/crc_17_xor0002_D213__INV$37 <= NOT (crc(18));


$OpTx$crc_17_xor0002/crc_17_xor0002_D2_INV$32 <= NOT (crc(16)
	 XOR 
$OpTx$crc_17_xor0002/crc_17_xor0002_D2_INV$32 <= NOT (crc(18));


$OpTx$crc_7_xor0001/crc_7_xor0001_D2_INV$33 <= NOT (crc(22)
	 XOR 
$OpTx$crc_7_xor0001/crc_7_xor0001_D2_INV$33 <= NOT (crc(21));


$OpTx$mdata_and00004/mdata_and00004_D2_INV$34 <= ((done AND NOT ctrl_in(1))
	OR (NOT done AND NOT loc_mode));
























































cclk_fbp <= ring_os(2);


cclkp <= NOT (((prog)
	OR (div(0).EXP)
	OR (cfg_done AND NOT ctrl_in(0))
	OR (ctrl_in(1) AND NOT loc_cs AND cfg_done)
	OR (NOT cfg_done AND NOT loc_mode AND div(4))));

FDCPE_cfg_done: FDCPE port map (cfg_done,'1',cclk,prog,'0',cfg_done_CE);
cfg_done_CE <= (done AND maddr(0) AND maddr(8) AND NOT maddr(15) AND 
	maddr(1) AND NOT maddr(3) AND maddr(5) AND maddr(11) AND maddr(13) AND 
	NOT maddr(4) AND NOT maddr(9) AND maddr(16) AND maddr(2) AND NOT maddr(6) AND 
	maddr(10) AND maddr(12) AND NOT maddr(14) AND maddr(17) AND maddr(7));

FDCPE_cfg_fail: FDCPE port map (cfg_fail,cfg_fail_D,cclk,prog,'0',cfg_fail_CE);
cfg_fail_D <= (en_conf AND NOT cfg_done);
cfg_fail_CE <= (maddr(0) AND maddr(8) AND maddr(15) AND maddr(1) AND 
	maddr(3) AND maddr(5) AND maddr(11) AND maddr(13) AND maddr(4) AND 
	maddr(9) AND maddr(16) AND maddr(2) AND maddr(6) AND maddr(10) AND 
	maddr(12) AND maddr(14) AND maddr(17) AND maddr(7));

FDCPE_crc0: FDCPE port map (crc(0),crc_D(0),cclk,'0',NOT crc_10_or0000/crc_10_or0000_D2__$INT,crc_CE(0));
crc_D(0) <= crc(19)
	 XOR 
crc_D(0) <= ((w_data(2).EXP)
	OR (w_data(3).EXP)
	OR (crc(18) AND mdata(0).PIN AND 
	$OpTx$crc_10_xor0001/crc_10_xor0001_D214__INV$38 AND $OpTx$crc_12_xor0001/crc_12_xor0001_D2_INV$29)
	OR (crc(18) AND mdata(0).PIN AND 
	NOT $OpTx$crc_10_xor0001/crc_10_xor0001_D214__INV$38 AND NOT $OpTx$crc_12_xor0001/crc_12_xor0001_D2_INV$29));
crc_CE(0) <= (en_conf AND NOT cfg_done);

FDCPE_crc1: FDCPE port map (crc(1),crc_D(1),cclk,'0',NOT crc_10_or0000/crc_10_or0000_D2__$INT,crc_CE(1));
crc_D(1) <= crc(22)
	 XOR 
crc_D(1) <= ((crc(21).EXP)
	OR (crc(16) AND mdata(1).PIN));
crc_CE(1) <= (en_conf AND NOT cfg_done);

FDCPE_crc2: FDCPE port map (crc(2),crc_D(2),cclk,'0',NOT crc_10_or0000/crc_10_or0000_D2__$INT,crc_CE(2));
crc_D(2) <= crc(17)
	 XOR 
crc_D(2) <= ((crc(22).EXP)
	OR (crc(23) AND mdata(2).PIN));
crc_CE(2) <= (en_conf AND NOT cfg_done);

FDCPE_crc3: FDCPE port map (crc(3),crc_D(3),cclk,'0',NOT crc_10_or0000/crc_10_or0000_D2__$INT,crc_CE(3));
crc_D(3) <= crc(19)
	 XOR 
crc_D(3) <= ((w_data(0).EXP)
	OR (EXP13_.EXP)
	OR (crc(16) AND crc(20) AND mdata(3).PIN AND 
	NOT $OpTx$crc_12_xor0001/crc_12_xor0001_D2_INV$29)
	OR (crc(16) AND crc(20) AND NOT mdata(3).PIN AND 
	$OpTx$crc_12_xor0001/crc_12_xor0001_D2_INV$29));
crc_CE(3) <= (en_conf AND NOT cfg_done);

FDCPE_crc4: FDCPE port map (crc(4),crc_D(4),cclk,'0',NOT crc_10_or0000/crc_10_or0000_D2__$INT,crc_CE(4));
crc_D(4) <= crc(22)
	 XOR 
crc_D(4) <= ((crc(20).EXP)
	OR (crc(19) AND crc(16) AND NOT mdata(4).PIN)
	OR (crc(19) AND NOT crc(16) AND mdata(4).PIN));
crc_CE(4) <= (en_conf AND NOT cfg_done);

FDCPE_crc5: FDCPE port map (crc(5),crc_D(5),cclk,'0',NOT crc_10_or0000/crc_10_or0000_D2__$INT,crc_CE(5));
crc_D(5) <= crc(19)
	 XOR 
crc_D(5) <= ((loc_add_out_2.EXP)
	OR (loc_add_out_1.EXP)
	OR (crc(21) AND crc(23) AND mdata(5).PIN AND 
	NOT $OpTx$crc_17_xor0002/crc_17_xor0002_D2_INV$32)
	OR (crc(21) AND crc(23) AND NOT mdata(5).PIN AND 
	$OpTx$crc_17_xor0002/crc_17_xor0002_D2_INV$32));
crc_CE(5) <= (en_conf AND NOT cfg_done);

FDCPE_crc6: FDCPE port map (crc(6),crc_D(6),cclk,'0',NOT crc_10_or0000/crc_10_or0000_D2__$INT,crc_CE(6));
crc_D(6) <= crc(22)
	 XOR 
crc_D(6) <= ((EXP21_.EXP)
	OR (r_data(1).EXP)
	OR (crc(16) AND crc(18) AND crc(21) AND mdata(6).PIN)
	OR (crc(16) AND crc(18) AND NOT crc(21) AND NOT mdata(6).PIN));
crc_CE(6) <= (en_conf AND NOT cfg_done);

FDCPE_crc7: FDCPE port map (crc(7),crc_D(7),cclk,'0',NOT crc_10_or0000/crc_10_or0000_D2__$INT,crc_CE(7));
crc_D(7) <= crc(16)
	 XOR 
crc_D(7) <= ((sel_byte(1).EXP)
	OR (crc(1).EXP)
	OR (crc(20) AND mdata(7).PIN AND 
	$OpTx$crc_10_xor0003/crc_10_xor0003_D2_INV$28 AND $OpTx$crc_7_xor0001/crc_7_xor0001_D2_INV$33)
	OR (crc(20) AND mdata(7).PIN AND 
	NOT $OpTx$crc_10_xor0003/crc_10_xor0003_D2_INV$28 AND NOT $OpTx$crc_7_xor0001/crc_7_xor0001_D2_INV$33));
crc_CE(7) <= (en_conf AND NOT cfg_done);

FDCPE_crc8: FDCPE port map (crc(8),crc_D(8),cclk,'0',NOT crc_10_or0000/crc_10_or0000_D2__$INT,crc_CE(8));
crc_D(8) <= crc(19)
	 XOR 
crc_D(8) <= ((crc(9).EXP)
	OR (EXP19_.EXP)
	OR (crc(17) AND crc(23) AND crc(0) AND 
	NOT $OpTx$crc_7_xor0001/crc_7_xor0001_D2_INV$33)
	OR (crc(17) AND crc(23) AND NOT crc(0) AND 
	$OpTx$crc_7_xor0001/crc_7_xor0001_D2_INV$33));
crc_CE(8) <= (en_conf AND NOT cfg_done);

FDCPE_crc9: FDCPE port map (crc(9),crc_D(9),cclk,'0',NOT crc_10_or0000/crc_10_or0000_D2__$INT,crc_CE(9));
crc_D(9) <= crc(22)
	 XOR 
crc_D(9) <= ((EXP18_.EXP)
	OR (crc(18) AND crc(20) AND crc(23) AND crc(1)));
crc_CE(9) <= (en_conf AND NOT cfg_done);

FDCPE_crc10: FDCPE port map (crc(10),crc_D(10),cclk,'0',NOT crc_10_or0000/crc_10_or0000_D2__$INT,crc_CE(10));
crc_D(10) <= crc(16)
	 XOR 
crc_D(10) <= ((EXP14_.EXP)
	OR (crc(17) AND crc(20) AND crc(2) AND 
	NOT $OpTx$crc_10_xor0003/crc_10_xor0003_D210__INV$35));
crc_CE(10) <= (en_conf AND NOT cfg_done);

FDCPE_crc11: FDCPE port map (crc(11),crc_D(11),cclk,'0',NOT crc_10_or0000/crc_10_or0000_D2__$INT,crc_CE(11));
crc_D(11) <= crc(16)
	 XOR 
crc_D(11) <= ((crc(20) AND crc(3))
	OR (NOT crc(20) AND NOT crc(3)));
crc_CE(11) <= (en_conf AND NOT cfg_done);

FDCPE_crc12: FDCPE port map (crc(12),crc_D(12),cclk,'0',NOT crc_10_or0000/crc_10_or0000_D2__$INT,crc_CE(12));
crc_D(12) <= crc(17)
	 XOR 
crc_D(12) <= ((crc(21) AND crc(4))
	OR (NOT crc(21) AND NOT crc(4)));
crc_CE(12) <= (en_conf AND NOT cfg_done);

FDCPE_crc13: FDCPE port map (crc(13),crc_D(13),cclk,'0',NOT crc_10_or0000/crc_10_or0000_D2__$INT,crc_CE(13));
crc_D(13) <= crc(22)
	 XOR 
crc_D(13) <= ((crc(19).EXP)
	OR (crc(18) AND crc(5)));
crc_CE(13) <= (en_conf AND NOT cfg_done);

FDCPE_crc14: FDCPE port map (crc(14),crc_D(14),cclk,'0',NOT crc_10_or0000/crc_10_or0000_D2__$INT,crc_CE(14));
crc_D(14) <= crc(17)
	 XOR 
crc_D(14) <= ((mwe_b_OBUF.EXP)
	OR (maddr_cntr(17).EXP)
	OR (crc(21) AND crc(6) AND 
	$OpTx$crc_10_xor0003/crc_10_xor0003_D210__INV$35 AND $OpTx$crc_10_xor0001/crc_10_xor0001_D211__INV$36)
	OR (crc(21) AND crc(6) AND 
	NOT $OpTx$crc_10_xor0003/crc_10_xor0003_D210__INV$35 AND NOT $OpTx$crc_10_xor0001/crc_10_xor0001_D211__INV$36));
crc_CE(14) <= (en_conf AND NOT cfg_done);

FDCPE_crc15: FDCPE port map (crc(15),crc_D(15),cclk,'0',NOT crc_10_or0000/crc_10_or0000_D2__$INT,crc_CE(15));
crc_D(15) <= crc(19)
	 XOR 
crc_D(15) <= ((maddr_cntr(3).EXP)
	OR (maddr_cntr(2).EXP)
	OR (crc(17) AND crc(21) AND crc(7) AND 
	NOT $OpTx$crc_13_xor0001/crc_13_xor0001_D2_INV$30)
	OR (crc(17) AND crc(21) AND NOT crc(7) AND 
	$OpTx$crc_13_xor0001/crc_13_xor0001_D2_INV$30));
crc_CE(15) <= (en_conf AND NOT cfg_done);

FDCPE_crc16: FDCPE port map (crc(16),crc_D(16),cclk,'0',NOT crc_10_or0000/crc_10_or0000_D2__$INT,crc_CE(16));
crc_D(16) <= crc(22)
	 XOR 
crc_D(16) <= ((crc(23).EXP)
	OR (EXP24_.EXP)
	OR (crc(18) AND crc(23) AND crc(8) AND 
	NOT $OpTx$crc_16_xor0001/crc_16_xor0001_D2_INV$31)
	OR (crc(18) AND crc(23) AND NOT crc(8) AND 
	$OpTx$crc_16_xor0001/crc_16_xor0001_D2_INV$31));
crc_CE(16) <= (en_conf AND NOT cfg_done);

FTCPE_crc17: FTCPE port map (crc(17),crc_T(17),cclk,'0',NOT crc_10_or0000/crc_10_or0000_D2__$INT,crc_CE(17));
crc_T(17) <= crc(16)
	 XOR 
crc_T(17) <= ((loc_mode.EXP)
	OR (crc(18) AND crc(23) AND NOT crc(9))
	OR (crc(18) AND NOT crc(23) AND crc(9)));
crc_CE(17) <= (en_conf AND NOT cfg_done);

FDCPE_crc18: FDCPE port map (crc(18),crc_D(18),cclk,'0',NOT crc_10_or0000/crc_10_or0000_D2__$INT,crc_CE(18));
crc_D(18) <= crc(16)
	 XOR 
crc_D(18) <= maddr_18_OBUF$BUF0.EXP;
crc_CE(18) <= (en_conf AND NOT cfg_done);

FDCPE_crc19: FDCPE port map (crc(19),crc_D(19),cclk,'0',NOT crc_10_or0000/crc_10_or0000_D2__$INT,crc_CE(19));
crc_D(19) <= crc(22)
	 XOR 
crc_D(19) <= ((loc_add_out_4.EXP)
	OR (crc(17) AND crc(21) AND NOT crc(11)));
crc_CE(19) <= (en_conf AND NOT cfg_done);

FDCPE_crc20: FDCPE port map (crc(20),crc_D(20),cclk,'0',NOT crc_10_or0000/crc_10_or0000_D2__$INT,crc_CE(20));
crc_D(20) <= crc(22)
	 XOR 
crc_D(20) <= loc_add_out_3.EXP;
crc_CE(20) <= (en_conf AND NOT cfg_done);

FDCPE_crc21: FDCPE port map (crc(21),crc_D(21),cclk,'0',NOT crc_10_or0000/crc_10_or0000_D2__$INT,crc_CE(21));
crc_D(21) <= crc(19)
	 XOR 
crc_D(21) <= ((crc(2).EXP)
	OR (crc(23) AND crc(13)));
crc_CE(21) <= (en_conf AND NOT cfg_done);

FDCPE_crc22: FDCPE port map (crc(22),crc_D(22),cclk,'0',NOT crc_10_or0000/crc_10_or0000_D2__$INT,crc_CE(22));
crc_D(22) <= crc(20)
	 XOR 
crc_D(22) <= crc(14);
crc_CE(22) <= (en_conf AND NOT cfg_done);

FDCPE_crc23: FDCPE port map (crc(23),crc_D(23),cclk,'0',NOT crc_10_or0000/crc_10_or0000_D2__$INT,crc_CE(23));
crc_D(23) <= crc(19)
	 XOR 
crc_D(23) <= ((EXP23_.EXP)
	OR (crc(17) AND crc(20) AND crc(15) AND 
	NOT $OpTx$crc_17_xor0002/crc_17_xor0002_D213__INV$37));
crc_CE(23) <= (en_conf AND NOT cfg_done);


crc_10_or0000/crc_10_or0000_D2__$INT <= (NOT prog AND NOT powerup);


cs_b <= NOT (((NOT loc_cs AND cfg_done)
	OR (en_conf AND NOT cfg_done AND init_b)));

FTCPE_div0: FTCPE port map (div(0),'1',cclk_fb,'0','0');

FTCPE_div1: FTCPE port map (div(1),'1',NOT div(0),'0','0');

FTCPE_div2: FTCPE port map (div(2),'1',NOT div(1),'0','0');

FTCPE_div3: FTCPE port map (div(3),'1',NOT div(2),'0','0');

FTCPE_div4: FTCPE port map (div(4),'1',NOT div(3),'0','0');

FDCPE_en_conf: FDCPE port map (en_conf,en_conf_D,cclk,en_conf_CLR,en_conf_PRE);
en_conf_D <= ((EXP10_.EXP)
	OR (EXP11_.EXP)
	OR (NOT maddr(0) AND en_conf)
	OR (NOT maddr(1) AND en_conf)
	OR (NOT maddr(3) AND en_conf));
en_conf_CLR <= (prog AND NOT loc_mode);
en_conf_PRE <= (prog AND loc_mode);

FDCPE_en_loc_bus: FDCPE port map (en_loc_bus,maddr_cntr(7).EXP,cclk,'0','0',NOT en_loc_bus);

FDCPE_loc_add_out0: FDCPE port map (loc_add_out(0),loc_add(0),NOT loc_cs,'0','0');

FDCPE_loc_add_out1: FDCPE port map (loc_add_out(1),loc_add(1),NOT loc_cs,'0','0');

FDCPE_loc_add_out2: FDCPE port map (loc_add_out(2),loc_add(2),NOT loc_cs,'0','0');

FDCPE_loc_add_out3: FDCPE port map (loc_add_out(3),loc_add(3),NOT loc_cs,'0','0');

FDCPE_loc_add_out4: FDCPE port map (loc_add_out(4),loc_add(4),NOT loc_cs,'0','0');

FDCPE_loc_add_out5: FDCPE port map (loc_add_out(5),loc_add(5),NOT loc_cs,'0','0');

FDCPE_loc_add_out6: FDCPE port map (loc_add_out(6),loc_add(6),NOT loc_cs,'0','0');


loc_bus_I(0) <= ((EXP20_.EXP)
	OR (NOT loc_add(6) AND mdata(0).PIN)
	OR (loc_add(5) AND NOT loc_add(1) AND NOT loc_add(0) AND 
	loc_add(6) AND maddr(0))
	OR (NOT loc_add(5) AND loc_add(1) AND NOT loc_add(0) AND 
	loc_add(6) AND crc(16))
	OR (NOT loc_add(5) AND NOT loc_add(1) AND NOT loc_add(0) AND 
	loc_add(6) AND crc(0)));
loc_bus(0) <= loc_bus_I(0) when loc_bus_OE(0) = '1' else 'Z';
loc_bus_OE(0) <= (NOT loc_cs AND loc_rw);


loc_bus_I(1) <= ((EXP22_.EXP)
	OR (NOT loc_add(6) AND mdata(1).PIN)
	OR (loc_add(5) AND NOT loc_add(1) AND NOT loc_add(0) AND 
	loc_add(6) AND maddr(1))
	OR (NOT loc_add(5) AND NOT loc_add(1) AND NOT loc_add(0) AND 
	loc_add(6) AND crc(1)));
loc_bus(1) <= loc_bus_I(1) when loc_bus_OE(1) = '1' else 'Z';
loc_bus_OE(1) <= (NOT loc_cs AND loc_rw);


loc_bus_I(2) <= ((EXP27_.EXP)
	OR (EXP28_.EXP)
	OR (NOT loc_add(6) AND mdata(2).PIN)
	OR (loc_add(5) AND loc_add(1) AND loc_add(0) AND 
	loc_add(6))
	OR (loc_add(5) AND loc_add(0) AND loc_add(6) AND 
	maddr(10))
	OR (loc_add(1) AND loc_add(0) AND loc_add(6) AND init_b));
loc_bus(2) <= loc_bus_I(2) when loc_bus_OE(2) = '1' else 'Z';
loc_bus_OE(2) <= (NOT loc_cs AND loc_rw);


loc_bus_I(3) <= ((EXP29_.EXP)
	OR (spare3_OBUF.EXP)
	OR (NOT loc_add(6) AND mdata(3).PIN)
	OR (loc_add(5) AND NOT loc_add(1) AND NOT loc_add(0) AND 
	loc_add(6) AND maddr(3))
	OR (NOT loc_add(5) AND loc_add(1) AND NOT loc_add(0) AND 
	loc_add(6) AND crc(19))
	OR (NOT loc_add(5) AND NOT loc_add(1) AND NOT loc_add(0) AND 
	loc_add(6) AND crc(3)));
loc_bus(3) <= loc_bus_I(3) when loc_bus_OE(3) = '1' else 'Z';
loc_bus_OE(3) <= (NOT loc_cs AND loc_rw);


loc_bus_I(4) <= ((EXP30_.EXP)
	OR (EXP31_.EXP)
	OR (NOT loc_add(6) AND mdata(4).PIN)
	OR (loc_add(5) AND NOT loc_add(1) AND NOT loc_add(0) AND 
	loc_add(6) AND maddr(4))
	OR (NOT loc_add(5) AND loc_add(1) AND NOT loc_add(0) AND 
	loc_add(6) AND crc(20))
	OR (NOT loc_add(5) AND NOT loc_add(1) AND NOT loc_add(0) AND 
	loc_add(6) AND crc(4)));
loc_bus(4) <= loc_bus_I(4) when loc_bus_OE(4) = '1' else 'Z';
loc_bus_OE(4) <= (NOT loc_cs AND loc_rw);


loc_bus_I(5) <= ((EXP32_.EXP)
	OR (spare5_OBUF.EXP)
	OR (NOT loc_add(6) AND mdata(5).PIN)
	OR (loc_add(5) AND NOT loc_add(1) AND NOT loc_add(0) AND 
	loc_add(6) AND maddr(5))
	OR (NOT loc_add(5) AND loc_add(1) AND NOT loc_add(0) AND 
	loc_add(6) AND crc(21))
	OR (NOT loc_add(5) AND NOT loc_add(1) AND NOT loc_add(0) AND 
	loc_add(6) AND crc(5)));
loc_bus(5) <= loc_bus_I(5) when loc_bus_OE(5) = '1' else 'Z';
loc_bus_OE(5) <= (NOT loc_cs AND loc_rw);


loc_bus_I(6) <= ((EXP33_.EXP)
	OR (EXP34_.EXP)
	OR (NOT loc_add(6) AND mdata(6).PIN)
	OR (loc_add(5) AND NOT loc_add(1) AND NOT loc_add(0) AND 
	loc_add(6) AND maddr(6))
	OR (NOT loc_add(5) AND loc_add(1) AND NOT loc_add(0) AND 
	loc_add(6) AND crc(22))
	OR (NOT loc_add(5) AND NOT loc_add(1) AND NOT loc_add(0) AND 
	loc_add(6) AND crc(6)));
loc_bus(6) <= loc_bus_I(6) when loc_bus_OE(6) = '1' else 'Z';
loc_bus_OE(6) <= (NOT loc_cs AND loc_rw);


loc_bus_I(7) <= ((EXP35_.EXP)
	OR (EXP36_.EXP)
	OR (NOT loc_add(6) AND mdata(7).PIN)
	OR (loc_add(5) AND NOT loc_add(1) AND NOT loc_add(0) AND 
	loc_add(6) AND maddr(7))
	OR (NOT loc_add(5) AND loc_add(1) AND NOT loc_add(0) AND 
	loc_add(6) AND crc(23))
	OR (NOT loc_add(5) AND NOT loc_add(1) AND NOT loc_add(0) AND 
	loc_add(6) AND crc(7)));
loc_bus(7) <= loc_bus_I(7) when loc_bus_OE(7) = '1' else 'Z';
loc_bus_OE(7) <= (NOT loc_cs AND loc_rw);

FDCPE_loc_mode: FDCPE port map (loc_mode,loc_bus(0).PIN,NOT loc_cs,'0','0',loc_mode_CE);
loc_mode_CE <= (NOT loc_add(5) AND NOT loc_add(4) AND NOT loc_add(3) AND 
	NOT loc_add(2) AND loc_add(1) AND loc_add(0) AND loc_add(6) AND NOT loc_rw AND 
	en_loc_bus);

FTCPE_maddr0: FTCPE port map (maddr(0),maddr_T(0),cclk,prog,'0');
maddr_T(0) <= ((NOT cfg_done)
	OR (crc(13).EXP)
	OR (NOT ctrl_in(1) AND NOT wr_maddr)
	OR (maddr(0) AND NOT mdata(0) AND wr_maddr AND NOT sel_byte(0) AND 
	NOT sel_byte(1))
	OR (NOT maddr(0) AND mdata(0) AND wr_maddr AND NOT sel_byte(0) AND 
	NOT sel_byte(1)));

FTCPE_maddr1: FTCPE port map (maddr(1),maddr_T(1),cclk,prog,'0');
maddr_T(1) <= ((EXP26_.EXP)
	OR (maddr(0) AND NOT cfg_done));

FTCPE_maddr2: FTCPE port map (maddr(2),maddr_T(2),cclk,prog,'0');
maddr_T(2) <= ((maddr_cntr(1).EXP)
	OR (maddr(0) AND maddr(1) AND NOT cfg_done)
	OR (NOT ctrl_in(1) AND maddr(0) AND maddr(1) AND NOT wr_maddr));

FTCPE_maddr3: FTCPE port map (maddr(3),EXP25_.EXP,cclk,prog,'0');

FTCPE_maddr4: FTCPE port map (maddr(4),maddr_T(4),cclk,prog,'0');
maddr_T(4) <= ((crc(10).EXP)
	OR (maddr(0) AND maddr(1) AND maddr(3) AND maddr(2) AND 
	NOT cfg_done)
	OR (maddr(4) AND cfg_done AND wr_maddr AND sel_byte(0) AND 
	sel_byte(1))
	OR (NOT ctrl_in(1) AND maddr(0) AND maddr(1) AND maddr(3) AND 
	maddr(2) AND NOT wr_maddr)
	OR (NOT maddr(4) AND mdata(4) AND cfg_done AND wr_maddr AND 
	NOT sel_byte(0) AND NOT sel_byte(1)));

FTCPE_maddr5: FTCPE port map (maddr(5),maddr_T(5),cclk,prog,'0');
maddr_T(5) <= ((maddr_cntr(6).EXP)
	OR (maddr(0) AND maddr(1) AND maddr(3) AND maddr(4) AND 
	maddr(2) AND NOT cfg_done)
	OR (NOT ctrl_in(1) AND maddr(0) AND maddr(1) AND maddr(3) AND 
	maddr(4) AND maddr(2) AND NOT wr_maddr));

FTCPE_maddr6: FTCPE port map (maddr(6),maddr_T(6),cclk,prog,'0');
maddr_T(6) <= ((en_loc_bus.EXP)
	OR (maddr(0) AND maddr(1) AND maddr(3) AND maddr(5) AND 
	maddr(4) AND maddr(2) AND NOT cfg_done));

FTCPE_maddr7: FTCPE port map (maddr(7),maddr_T(7),cclk,prog,'0');
maddr_T(7) <= ((maddr_cntr(12).EXP)
	OR (maddr(0) AND maddr(1) AND maddr(3) AND maddr(5) AND 
	maddr(4) AND maddr(2) AND maddr(6) AND NOT cfg_done)
	OR (NOT ctrl_in(1) AND maddr(0) AND maddr(1) AND maddr(3) AND 
	maddr(5) AND maddr(4) AND maddr(2) AND maddr(6) AND NOT wr_maddr));

FTCPE_maddr8: FTCPE port map (maddr(8),maddr_T(8),cclk,prog,'0');
maddr_T(8) <= ((maddr_cntr(13).EXP)
	OR (maddr(8) AND NOT mdata(0) AND cfg_done AND wr_maddr AND 
	sel_byte(0))
	OR (NOT maddr(8) AND mdata(0) AND cfg_done AND wr_maddr AND 
	sel_byte(0) AND NOT sel_byte(1))
	OR (maddr(0) AND maddr(1) AND maddr(3) AND maddr(5) AND 
	maddr(4) AND maddr(2) AND maddr(6) AND maddr(7) AND NOT cfg_done)
	OR (NOT ctrl_in(1) AND maddr(0) AND maddr(1) AND maddr(3) AND 
	maddr(5) AND maddr(4) AND maddr(2) AND maddr(6) AND maddr(7) AND 
	NOT wr_maddr));

FTCPE_maddr9: FTCPE port map (maddr(9),maddr_T(9),cclk,prog,'0');
maddr_T(9) <= ((maddr_cntr(11).EXP)
	OR (maddr(9) AND NOT mdata(1) AND cfg_done AND wr_maddr AND 
	sel_byte(0))
	OR (NOT maddr(9) AND mdata(1) AND cfg_done AND wr_maddr AND 
	sel_byte(0) AND NOT sel_byte(1))
	OR (maddr(0) AND maddr(8) AND maddr(1) AND maddr(3) AND 
	maddr(5) AND maddr(4) AND maddr(2) AND maddr(6) AND maddr(7) AND 
	NOT cfg_done)
	OR (NOT ctrl_in(1) AND maddr(0) AND maddr(8) AND maddr(1) AND 
	maddr(3) AND maddr(5) AND maddr(4) AND maddr(2) AND maddr(6) AND 
	maddr(7) AND NOT wr_maddr));

FTCPE_maddr10: FTCPE port map (maddr(10),maddr_T(10),cclk,prog,'0');
maddr_T(10) <= ((mce_b_OBUF.EXP)
	OR (maddr(10) AND NOT mdata(2) AND cfg_done AND wr_maddr AND 
	sel_byte(0))
	OR (NOT maddr(10) AND mdata(2) AND cfg_done AND wr_maddr AND 
	sel_byte(0) AND NOT sel_byte(1))
	OR (maddr(0) AND maddr(8) AND maddr(1) AND maddr(3) AND 
	maddr(5) AND maddr(4) AND maddr(9) AND maddr(2) AND maddr(6) AND 
	maddr(7) AND NOT cfg_done)
	OR (NOT ctrl_in(1) AND maddr(0) AND maddr(8) AND maddr(1) AND 
	maddr(3) AND maddr(5) AND maddr(4) AND maddr(9) AND maddr(2) AND 
	maddr(6) AND maddr(7) AND NOT wr_maddr));

FTCPE_maddr11: FTCPE port map (maddr(11),maddr_T(11),cclk,prog,'0');
maddr_T(11) <= ((EXP12_.EXP)
	OR (NOT maddr(11) AND mdata(3) AND cfg_done AND wr_maddr AND 
	sel_byte(0) AND NOT sel_byte(1))
	OR (maddr(0) AND maddr(8) AND maddr(1) AND maddr(3) AND 
	maddr(5) AND maddr(4) AND maddr(9) AND maddr(2) AND maddr(6) AND 
	maddr(10) AND maddr(7) AND NOT cfg_done)
	OR (NOT ctrl_in(1) AND maddr(0) AND maddr(8) AND maddr(1) AND 
	maddr(3) AND maddr(5) AND maddr(4) AND maddr(9) AND maddr(2) AND 
	maddr(6) AND maddr(10) AND maddr(7) AND NOT wr_maddr));

FTCPE_maddr12: FTCPE port map (maddr(12),maddr_T(12),cclk,prog,'0');
maddr_T(12) <= ((EXP15_.EXP)
	OR (maddr(0) AND maddr(8) AND maddr(1) AND maddr(3) AND 
	maddr(5) AND maddr(11) AND maddr(4) AND maddr(9) AND maddr(2) AND 
	maddr(6) AND maddr(10) AND maddr(7) AND NOT cfg_done));

FTCPE_maddr13: FTCPE port map (maddr(13),maddr_T(13),cclk,prog,'0');
maddr_T(13) <= (($OpTx$crc_16_xor0001/crc_16_xor0001_D2_INV$31.EXP)
	OR (NOT maddr(13) AND mdata(5) AND cfg_done AND wr_maddr AND 
	sel_byte(0) AND NOT sel_byte(1))
	OR (maddr(0) AND maddr(8) AND maddr(1) AND maddr(3) AND 
	maddr(5) AND maddr(11) AND maddr(4) AND maddr(9) AND maddr(2) AND 
	maddr(6) AND maddr(10) AND maddr(12) AND maddr(7) AND NOT cfg_done)
	OR (NOT ctrl_in(1) AND maddr(0) AND maddr(8) AND maddr(1) AND 
	maddr(3) AND maddr(5) AND maddr(11) AND maddr(4) AND maddr(9) AND 
	maddr(2) AND maddr(6) AND maddr(10) AND maddr(12) AND maddr(7) AND 
	NOT wr_maddr));

FTCPE_maddr14: FTCPE port map (maddr(14),maddr_T(14),cclk,prog,'0');
maddr_T(14) <= (($OpTx$crc_17_xor0002/crc_17_xor0002_D2_INV$32.EXP)
	OR (maddr(14) AND NOT mdata(6) AND cfg_done AND wr_maddr AND 
	sel_byte(0))
	OR (NOT maddr(14) AND mdata(6) AND cfg_done AND wr_maddr AND 
	sel_byte(0) AND NOT sel_byte(1))
	OR (maddr(0) AND maddr(8) AND maddr(1) AND maddr(3) AND 
	maddr(5) AND maddr(11) AND maddr(13) AND maddr(4) AND maddr(9) AND 
	maddr(2) AND maddr(6) AND maddr(10) AND maddr(12) AND maddr(7) AND 
	NOT cfg_done)
	OR (NOT ctrl_in(1) AND maddr(0) AND maddr(8) AND maddr(1) AND 
	maddr(3) AND maddr(5) AND maddr(11) AND maddr(13) AND maddr(4) AND 
	maddr(9) AND maddr(2) AND maddr(6) AND maddr(10) AND maddr(12) AND 
	maddr(7) AND NOT wr_maddr));

FTCPE_maddr15: FTCPE port map (maddr(15),maddr_T(15),cclk,prog,'0');
maddr_T(15) <= ((maddr_cntr(16).EXP)
	OR (maddr(15) AND NOT mdata(7) AND cfg_done AND wr_maddr AND 
	sel_byte(0))
	OR (NOT maddr(15) AND mdata(7) AND cfg_done AND wr_maddr AND 
	sel_byte(0) AND NOT sel_byte(1))
	OR (maddr(0) AND maddr(8) AND maddr(1) AND maddr(3) AND 
	maddr(5) AND maddr(11) AND maddr(13) AND maddr(4) AND maddr(9) AND 
	maddr(2) AND maddr(6) AND maddr(10) AND maddr(12) AND maddr(14) AND 
	maddr(7) AND NOT cfg_done)
	OR (NOT ctrl_in(1) AND maddr(0) AND maddr(8) AND maddr(1) AND 
	maddr(3) AND maddr(5) AND maddr(11) AND maddr(13) AND maddr(4) AND 
	maddr(9) AND maddr(2) AND maddr(6) AND maddr(10) AND maddr(12) AND 
	maddr(14) AND maddr(7) AND NOT wr_maddr));

FTCPE_maddr16: FTCPE port map (maddr(16),maddr_T(16),cclk,prog,'0');
maddr_T(16) <= ((crc(18).EXP)
	OR (NOT maddr(16) AND mdata(0) AND cfg_done AND wr_maddr AND 
	NOT sel_byte(0) AND sel_byte(1))
	OR (maddr(0) AND maddr(8) AND maddr(15) AND maddr(1) AND 
	maddr(3) AND maddr(5) AND maddr(11) AND maddr(13) AND maddr(4) AND 
	maddr(9) AND maddr(2) AND maddr(6) AND maddr(10) AND maddr(12) AND 
	maddr(14) AND maddr(7) AND NOT cfg_done)
	OR (NOT ctrl_in(1) AND maddr(0) AND maddr(8) AND maddr(15) AND 
	maddr(1) AND maddr(3) AND maddr(5) AND maddr(11) AND maddr(13) AND 
	maddr(4) AND maddr(9) AND maddr(2) AND maddr(6) AND maddr(10) AND 
	maddr(12) AND maddr(14) AND maddr(7) AND NOT wr_maddr));

FTCPE_maddr17: FTCPE port map (maddr(17),maddr_T(17),cclk,prog,'0');
maddr_T(17) <= ((EXP16_.EXP)
	OR (maddr(0) AND maddr(8) AND maddr(15) AND maddr(1) AND 
	maddr(3) AND maddr(5) AND maddr(11) AND maddr(13) AND maddr(4) AND 
	maddr(9) AND maddr(16) AND maddr(2) AND maddr(6) AND maddr(10) AND 
	maddr(12) AND maddr(14) AND maddr(7) AND NOT cfg_done));


maddr(18) <= '0';


mce_b <= NOT (((NOT ctrl_in(0))
	OR (NOT cfg_done AND NOT loc_mode)
	OR (loc_add(5) AND ctrl_in(1) AND NOT loc_cs AND NOT loc_add(4) AND 
	NOT loc_add(3) AND NOT loc_add(2) AND NOT loc_add(1) AND NOT loc_add(0) AND 
	NOT loc_add(6))));

FDCPE_mdata0: FDCPE port map (mdata_I(0),loc_bus(0).PIN,NOT loc_cs,'0','0');
mdata(0) <= mdata_I(0) when mdata_OE(0) = '1' else 'Z';
mdata_OE(0) <= (NOT loc_rw AND 
	NOT $OpTx$mdata_and00004/mdata_and00004_D2_INV$34);

FDCPE_mdata1: FDCPE port map (mdata_I(1),loc_bus(1).PIN,NOT loc_cs,'0','0');
mdata(1) <= mdata_I(1) when mdata_OE(1) = '1' else 'Z';
mdata_OE(1) <= (NOT loc_rw AND 
	NOT $OpTx$mdata_and00004/mdata_and00004_D2_INV$34);

FDCPE_mdata2: FDCPE port map (mdata_I(2),loc_bus(2).PIN,NOT loc_cs,'0','0');
mdata(2) <= mdata_I(2) when mdata_OE(2) = '1' else 'Z';
mdata_OE(2) <= (NOT loc_rw AND 
	NOT $OpTx$mdata_and00004/mdata_and00004_D2_INV$34);

FDCPE_mdata3: FDCPE port map (mdata_I(3),loc_bus(3).PIN,NOT loc_cs,'0','0');
mdata(3) <= mdata_I(3) when mdata_OE(3) = '1' else 'Z';
mdata_OE(3) <= (NOT loc_rw AND 
	NOT $OpTx$mdata_and00004/mdata_and00004_D2_INV$34);

FDCPE_mdata4: FDCPE port map (mdata_I(4),loc_bus(4).PIN,NOT loc_cs,'0','0');
mdata(4) <= mdata_I(4) when mdata_OE(4) = '1' else 'Z';
mdata_OE(4) <= (NOT loc_rw AND 
	NOT $OpTx$mdata_and00004/mdata_and00004_D2_INV$34);

FDCPE_mdata5: FDCPE port map (mdata_I(5),loc_bus(5).PIN,NOT loc_cs,'0','0');
mdata(5) <= mdata_I(5) when mdata_OE(5) = '1' else 'Z';
mdata_OE(5) <= (NOT loc_rw AND 
	NOT $OpTx$mdata_and00004/mdata_and00004_D2_INV$34);

FDCPE_mdata6: FDCPE port map (mdata_I(6),loc_bus(6).PIN,NOT loc_cs,'0','0');
mdata(6) <= mdata_I(6) when mdata_OE(6) = '1' else 'Z';
mdata_OE(6) <= (NOT loc_rw AND 
	NOT $OpTx$mdata_and00004/mdata_and00004_D2_INV$34);

FDCPE_mdata7: FDCPE port map (mdata_I(7),loc_bus(7).PIN,NOT loc_cs,'0','0');
mdata(7) <= mdata_I(7) when mdata_OE(7) = '1' else 'Z';
mdata_OE(7) <= (NOT loc_rw AND 
	NOT $OpTx$mdata_and00004/mdata_and00004_D2_INV$34);


moe_b <= ((NOT ctrl_in(1) AND cfg_done)
	OR (NOT loc_rw AND cfg_done));


mwe_b <= ((NOT cfg_done)
	OR (ctrl_in(1) AND loc_rw));

FDCPE_powerup: FDCPE port map (powerup,'0',cclk,'0','0',maddr(4));

FDCPE_prog: FDCPE port map (prog,loc_bus(1).PIN,NOT loc_cs,'0','0',prog_CE);
prog_CE <= (NOT loc_add(5) AND NOT loc_add(4) AND NOT loc_add(3) AND 
	NOT loc_add(2) AND loc_add(1) AND loc_add(0) AND loc_add(6) AND NOT loc_rw AND 
	en_loc_bus);


prog_b_I <= '0';
prog_b <= prog_b_I when prog_b_OE = '1' else 'Z';
prog_b_OE <= NOT ((NOT prog AND NOT powerup));


rdwr_b <= (loc_rw AND cfg_done);


ring_os(0) <= ((cfg_fail)
	OR (NOT cclk_fb)
	OR (loc_mode)
	OR (ctrl_in(1) AND cfg_done AND NOT div(4)));


ring_os(1) <= ring_os(0);


ring_os(2) <= ring_os(1);

FDCPE_sel_byte0: FDCPE port map (sel_byte(0),loc_add(0),NOT loc_cs,'0','0');

FDCPE_sel_byte1: FDCPE port map (sel_byte(1),cclkp_OBUF.EXP,NOT loc_cs,'0','0');


spare3 <= NOT ((cfg_done AND NOT div(4)));


spare5 <= NOT ((NOT loc_cs AND cfg_done));

FDCPE_wr_maddr: FDCPE port map (wr_maddr,wr_maddr_D,NOT loc_cs,NOT ctrl_in(1),'0');
wr_maddr_D <= (loc_add(5) AND NOT loc_add(4) AND NOT loc_add(3) AND 
	NOT loc_add(2) AND loc_add(6) AND NOT loc_rw AND cfg_done);

Register Legend:
 FDCPE (Q,D,C,CLR,PRE,CE); 
 FTCPE (Q,D,C,CLR,PRE,CE); 
 LDCP  (Q,D,G,CLR,PRE); 

******************************  Device Pin Out *****************************

Device : XC95144XL-10-TQ100


   --------------------------------------------------  
  /100 98  96  94  92  90  88  86  84  82  80  78  76  \
 |   99  97  95  93  91  89  87  85  83  81  79  77    |
 | 1                                               75  | 
 | 2                                               74  | 
 | 3                                               73  | 
 | 4                                               72  | 
 | 5                                               71  | 
 | 6                                               70  | 
 | 7                                               69  | 
 | 8                                               68  | 
 | 9                                               67  | 
 | 10                                              66  | 
 | 11                                              65  | 
 | 12                                              64  | 
 | 13              XC95144XL-10-TQ100              63  | 
 | 14                                              62  | 
 | 15                                              61  | 
 | 16                                              60  | 
 | 17                                              59  | 
 | 18                                              58  | 
 | 19                                              57  | 
 | 20                                              56  | 
 | 21                                              55  | 
 | 22                                              54  | 
 | 23                                              53  | 
 | 24                                              52  | 
 | 25                                              51  | 
 |   27  29  31  33  35  37  39  41  43  45  47  49    |
  \26  28  30  32  34  36  38  40  42  44  46  48  50  /
   --------------------------------------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 maddr<13>                        51 VCC                           
  2 maddr<8>                         52 loc_bus<3>                    
  3 maddr<9>                         53 spare3                        
  4 maddr<11>                        54 loc_bus<4>                    
  5 VCC                              55 PGND                          
  6 mdata<0>                         56 loc_bus<5>                    
  7 PGND                             57 VCC                           
  8 mdata<1>                         58 spare5                        
  9 mdata<2>                         59 loc_bus<6>                    
 10 mdata<3>                         60 PGND                          
 11 mdata<4>                         61 loc_bus<7>                    
 12 mdata<5>                         62 GND                           
 13 mdata<6>                         63 prog_b                        
 14 mdata<7>                         64 PGND                          
 15 mce_b                            65 init_b                        
 16 maddr<10>                        66 done                          
 17 moe_b                            67 ctrl_in<2>                    
 18 rdwr_b                           68 ctrl_in<0>                    
 19 PGND                             69 GND                           
 20 cs_b                             70 ctrl_in<1>                    
 21 GND                              71 loc_add_out<6>                
 22 cclk                             72 loc_add_out<5>                
 23 cclkp                            73 PGND                          
 24 cclk_fb                          74 loc_add_out<4>                
 25 cclk_fbp                         75 GND                           
 26 VCC                              76 loc_add_out<3>                
 27 loc_cs                           77 loc_add_out<2>                
 28 loc_rw                           78 loc_add_out<1>                
 29 loc_add<0>                       79 loc_add_out<0>                
 30 loc_add<1>                       80 PGND                          
 31 GND                              81 maddr<3>                      
 32 loc_add<2>                       82 maddr<2>                      
 33 loc_add<3>                       83 TDO                           
 34 PGND                             84 GND                           
 35 loc_add<4>                       85 maddr<1>                      
 36 loc_add<5>                       86 maddr<0>                      
 37 loc_add<6>                       87 maddr<4>                      
 38 VCC                              88 VCC                           
 39 PGND                             89 maddr<5>                      
 40 loc_bus<0>                       90 maddr<6>                      
 41 PGND                             91 maddr<7>                      
 42 loc_bus<1>                       92 maddr<12>                     
 43 PGND                             93 maddr<15>                     
 44 GND                              94 maddr<16>                     
 45 TDI                              95 maddr<18>                     
 46 PGND                             96 mwe_b                         
 47 TMS                              97 maddr<17>                     
 48 TCK                              98 VCC                           
 49 PGND                             99 maddr<14>                     
 50 loc_bus<2>                      100 GND                           


Legend :  NC  = Not Connected, unbonded pin
         PGND = Unused I/O configured as additional Ground pin
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         KPR  = Unused I/O with weak keeper (leave unconnected)
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc95144xl-10-TQ100
Optimization Method                         : SPEED
Multi-Level Logic Optimization              : OFF
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : SLOW
Power Mode                                  : LOW
Ground on Unused IOs                        : ON
Set I/O Pin Termination                     : KEEPER
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
Input Limit                                 : 54
Pterm Limit                                 : 25