cpldfit: version J.33 Xilinx Inc. Fitter Report Design Name: HTR_SLB Date: 4-25-2007, 11:06AM Device Used: XC95144XL-10-TQ100 Fitting Status: Successful ************************* Mapped Resource Summary ************************** Macrocells Product Terms Function Block Registers Pins Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot 102/144 ( 71%) 463 /720 ( 64%) 292/432 ( 68%) 64 /144 ( 44%) 67 /81 ( 83%) ** Function Block Resources ** Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot FB1 15/18 41/54 34/90 9/11 FB2 15/18 40/54 50/90 9/10 FB3 15/18 36/54 83/90 2/10 FB4 10/18 32/54 50/90 10/10* FB5 7/18 38/54 81/90 2/10 FB6 15/18 35/54 79/90 9/10 FB7 7/18 49/54 48/90 7/10 FB8 18/18* 21/54 38/90 3/10 ----- ----- ----- ----- 102/144 292/432 463/720 51/81 * - Resource is exhausted ** Global Control Resources ** Signal 'cclk' mapped onto global clock net GCK1. Signal 'loc_cs' mapped onto global clock net GCK3. Global output enable net(s) unused. Global set/reset net(s) unused. ** Pin Resources ** Signal Type Required Mapped | Pin Type Used Total ------------------------------------|------------------------------------ Input : 14 14 | I/O : 59 73 Output : 35 35 | GCK/IO : 3 3 Bidirectional : 16 16 | GTS/IO : 4 4 GCK : 2 2 | GSR/IO : 1 1 GTS : 0 0 | GSR : 0 0 | ---- ---- Total 67 67 ** Power Data ** There are 0 macrocells in high performance mode (MCHP). There are 102 macrocells in low power mode (MCLP). End of Mapped Resource Summary ************************* Summary of Mapped Logic ************************ ** 51 Outputs ** Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init Name Pts Inps No. Type Use Mode Rate State mdata<4> 2 2 FB1_2 11 I/O I/O LOW SLOW RESET mdata<5> 2 2 FB1_3 12 I/O I/O LOW SLOW RESET mdata<6> 2 2 FB1_5 13 I/O I/O LOW SLOW RESET mdata<7> 2 2 FB1_6 14 I/O I/O LOW SLOW RESET mce_b 3 12 FB1_8 15 I/O O LOW SLOW maddr<10> 6 19 FB1_9 16 I/O O LOW SLOW RESET moe_b 2 3 FB1_11 17 I/O O LOW SLOW rdwr_b 1 2 FB1_12 18 I/O O LOW SLOW cs_b 2 4 FB1_15 20 I/O O LOW SLOW maddr<14> 6 23 FB2_2 99 GSR/I/O O LOW SLOW RESET maddr<13> 6 22 FB2_5 1 GTS/I/O O LOW SLOW RESET maddr<8> 6 17 FB2_6 2 GTS/I/O O LOW SLOW RESET maddr<9> 6 18 FB2_8 3 GTS/I/O O LOW SLOW RESET maddr<11> 6 20 FB2_9 4 GTS/I/O O LOW SLOW RESET mdata<0> 2 2 FB2_11 6 I/O I/O LOW SLOW RESET mdata<1> 2 2 FB2_14 8 I/O I/O LOW SLOW RESET mdata<2> 2 2 FB2_15 9 I/O I/O LOW SLOW RESET mdata<3> 2 2 FB2_17 10 I/O I/O LOW SLOW RESET cclkp 4 9 FB3_2 23 GCK/I/O O LOW SLOW cclk_fbp 1 1 FB3_6 25 I/O O LOW SLOW maddr<4> 6 13 FB4_2 87 I/O O LOW SLOW RESET maddr<5> 6 14 FB4_5 89 I/O O LOW SLOW RESET maddr<6> 6 15 FB4_6 90 I/O O LOW SLOW RESET maddr<7> 6 16 FB4_8 91 I/O O LOW SLOW RESET maddr<12> 6 21 FB4_9 92 I/O O LOW SLOW RESET maddr<15> 6 24 FB4_11 93 I/O O LOW SLOW RESET maddr<16> 6 25 FB4_12 94 I/O O LOW SLOW RESET maddr<18> 0 0 FB4_14 95 I/O O LOW SLOW mwe_b 2 3 FB4_15 96 I/O O LOW SLOW maddr<17> 6 26 FB4_17 97 I/O O LOW SLOW RESET loc_bus<0> 9 15 FB5_9 40 I/O I/O LOW SLOW loc_bus<1> 9 15 FB5_12 42 I/O I/O LOW SLOW loc_add_out<4> 1 1 FB6_2 74 I/O O LOW SLOW loc_add_out<3> 1 1 FB6_5 76 I/O O LOW SLOW loc_add_out<2> 1 1 FB6_6 77 I/O O LOW SLOW loc_add_out<1> 1 1 FB6_8 78 I/O O LOW SLOW loc_add_out<0> 1 1 FB6_9 79 I/O O LOW SLOW maddr<3> 6 12 FB6_12 81 I/O O LOW SLOW RESET maddr<2> 6 11 FB6_14 82 I/O O LOW SLOW RESET maddr<1> 6 10 FB6_15 85 I/O O LOW SLOW RESET Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init Name Pts Inps No. Type Use Mode Rate State maddr<0> 6 9 FB6_17 86 I/O O LOW SLOW RESET loc_bus<2> 8 14 FB7_2 50 I/O I/O LOW SLOW loc_bus<3> 8 14 FB7_5 52 I/O I/O LOW SLOW loc_bus<4> 8 14 FB7_8 54 I/O I/O LOW SLOW loc_bus<5> 8 14 FB7_11 56 I/O I/O LOW SLOW spare5 1 2 FB7_12 58 I/O O LOW SLOW loc_bus<6> 8 14 FB7_14 59 I/O I/O LOW SLOW loc_bus<7> 7 13 FB7_17 61 I/O I/O LOW SLOW prog_b 1 2 FB8_2 63 I/O O LOW SLOW loc_add_out<6> 1 1 FB8_14 71 I/O O LOW SLOW loc_add_out<5> 1 1 FB8_15 72 I/O O LOW SLOW ** 51 Buried Nodes ** Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State sel_byte<1> 1 1 FB1_10 LOW RESET sel_byte<0> 1 1 FB1_13 LOW RESET wr_maddr 2 8 FB1_14 LOW RESET prog 2 10 FB1_16 LOW RESET loc_mode 2 10 FB1_17 LOW RESET crc<22> 4 6 FB1_18 LOW RESET powerup 1 2 FB2_7 LOW RESET en_conf 1 19 FB2_10 LOW SET en_loc_bus 2 6 FB2_12 LOW SET div<0> 2 3 FB2_13 LOW RESET cfg_done 2 21 FB2_16 LOW RESET ring_os<0> 4 5 FB2_18 LOW crc<18> 7 8 FB3_1 LOW RESET crc<21> 5 7 FB3_4 LOW RESET crc<1> 5 7 FB3_5 LOW RESET crc<13> 5 7 FB3_7 LOW RESET crc<12> 5 7 FB3_8 LOW RESET crc<11> 5 7 FB3_9 LOW RESET crc<5> 7 8 FB3_10 LOW RESET crc<4> 7 8 FB3_12 LOW RESET crc<19> 7 8 FB3_13 LOW RESET crc<2> 5 7 FB3_14 LOW RESET w_data<6>/w_data<6>_TRST 2 4 FB3_15 LOW crc<16> 7 8 FB3_16 LOW RESET crc<7> 11 9 FB3_17 LOW RESET crc<6> 11 9 FB5_4 LOW RESET crc<15> 11 9 FB5_5 LOW RESET crc<0> 11 9 FB5_8 LOW RESET crc<3> 19 10 FB5_14 LOW RESET crc<9> 11 9 FB5_18 LOW RESET crc<23> 7 8 FB6_3 LOW RESET crc<20> 7 8 FB6_4 LOW RESET crc<17> 7 8 FB6_7 LOW RESET crc<10> 7 8 FB6_10 LOW RESET crc<8> 11 9 FB6_13 LOW RESET crc<14> 11 9 FB6_18 LOW RESET ring_os<2> 1 1 FB8_1 LOW ring_os<1> 1 1 FB8_3 LOW div<4> 2 3 FB8_4 LOW RESET div<3> 2 3 FB8_5 LOW RESET Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State div<2> 2 3 FB8_6 LOW RESET div<1> 2 3 FB8_7 LOW RESET crc_7_xor0001/crc_7_xor0001_D 2 2 FB8_8 LOW crc_13_xor0001/crc_13_xor0001_D 2 2 FB8_9 LOW crc_7_xor0002/crc_7_xor0002_D 3 3 FB8_10 LOW crc_20_xor0001/crc_20_xor0001_D 3 3 FB8_11 LOW crc_14_xor0001/crc_14_xor0001_D 3 3 FB8_12 LOW crc_0_xor0001/crc_0_xor0001_D 3 3 FB8_13 LOW Mxor_crc_5_xor0000__xor0000/Mxor_crc_5_xor0000__xor0000_D 3 3 FB8_16 LOW Mxor_crc_23_xor0000__xor0000/Mxor_crc_23_xor0000__xor0000_D 3 3 FB8_17 LOW Mxor_crc_10_xor0000__xor0000/Mxor_crc_10_xor0000__xor0000_D 3 3 FB8_18 LOW ** 16 Inputs ** Signal Loc Pin Pin Pin Name No. Type Use cclk FB1_17 22 GCK/I/O GCK cclk_fb FB3_5 24 I/O I loc_cs FB3_8 27 GCK/I/O GCK/I loc_rw FB3_9 28 I/O I loc_add<0> FB3_11 29 I/O I loc_add<1> FB3_12 30 I/O I loc_add<2> FB3_14 32 I/O I loc_add<3> FB3_15 33 I/O I loc_add<4> FB5_2 35 I/O I loc_add<5> FB5_5 36 I/O I loc_add<6> FB5_6 37 I/O I init_b FB8_6 65 I/O I done FB8_8 66 I/O I ctrl_in<2> FB8_9 67 I/O I ctrl_in<0> FB8_11 68 I/O I ctrl_in<1> FB8_12 70 I/O I Legend: Pin No. - ~ - User Assigned ************************** Function Block Details ************************ Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X - Signal used as input to the macrocell logic. Pin No. - ~ - User Assigned *********************************** FB1 *********************************** Number of function block inputs used/remaining: 41/13 Number of signals used by logic mapping into function block: 41 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB1_1 (b) mdata<4> 2 0 0 3 FB1_2 11 I/O I/O mdata<5> 2 0 0 3 FB1_3 12 I/O I/O (unused) 0 0 0 5 FB1_4 (b) mdata<6> 2 0 0 3 FB1_5 13 I/O I/O mdata<7> 2 0 0 3 FB1_6 14 I/O I/O (unused) 0 0 0 5 FB1_7 (b) mce_b 3 0 \/1 1 FB1_8 15 I/O O maddr<10> 6 1<- 0 0 FB1_9 16 I/O O sel_byte<1> 1 0 0 4 FB1_10 (b) (b) moe_b 2 0 0 3 FB1_11 17 I/O O rdwr_b 1 0 0 4 FB1_12 18 I/O O sel_byte<0> 1 0 0 4 FB1_13 (b) (b) wr_maddr 2 0 0 3 FB1_14 19 I/O (b) cs_b 2 0 0 3 FB1_15 20 I/O O prog 2 0 0 3 FB1_16 (b) (b) loc_mode 2 0 0 3 FB1_17 22 GCK/I/O GCK crc<22> 4 0 0 1 FB1_18 (b) (b) Signals Used by Logic in Function Block 1: loc_bus<5>.PIN 15: loc_add<0> 29: maddr<3> 2: loc_bus<4>.PIN 16: loc_add<1> 30: maddr<4> 3: loc_bus<1>.PIN 17: loc_add<2> 31: maddr<5> 4: loc_bus<0>.PIN 18: loc_add<3> 32: maddr<6> 5: loc_bus<7>.PIN 19: loc_add<4> 33: maddr<7> 6: loc_bus<6>.PIN 20: loc_add<5> 34: maddr<8> 7: cfg_done 21: loc_add<6> 35: maddr<9> 8: crc<14> 22: loc_cs 36: mdata<2> 9: crc<20> 23: loc_mode 37: powerup 10: ctrl_in<0> 24: loc_rw 38: sel_byte<0> 11: ctrl_in<1> 25: maddr<0> 39: sel_byte<1> 12: en_conf 26: maddr<10> 40: w_data<6>/w_data<6>_TRST 13: en_loc_bus 27: maddr<1> 41: wr_maddr 14: init_b 28: maddr<2> Signal 1 2 3 4 5 FB Name 0----+----0----+----0----+----0----+----0----+----0 Inputs mdata<4> .X.....................................X.......... 2 mdata<5> X......................................X.......... 2 mdata<6> .....X.................................X.......... 2 mdata<7> ....X..................................X.......... 2 mce_b ......X..XX...XXXXXXXXX........................... 12 maddr<10> ......X...X..X..........XXXXXXXXXXXXXXX.X......... 19 sel_byte<1> ...............X.................................. 1 moe_b ......X...X............X.......................... 3 rdwr_b ......X................X.......................... 2 sel_byte<0> ..............X................................... 1 wr_maddr ......X...X.....XXXXX..X.......................... 8 cs_b ......X....X.X.......X............................ 4 prog ..X.........X.XXXXXXX..X.......................... 10 loc_mode ...X........X.XXXXXXX..X.......................... 10 crc<22> ......XXX..X.X......................X............. 6 0----+----1----+----2----+----3----+----4----+----5 0 0 0 0 0 *********************************** FB2 *********************************** Number of function block inputs used/remaining: 40/14 Number of signals used by logic mapping into function block: 40 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 \/1 4 FB2_1 (b) (b) maddr<14> 6 1<- 0 0 FB2_2 99 GSR/I/O O (unused) 0 0 0 5 FB2_3 (b) (unused) 0 0 \/2 3 FB2_4 (b) (b) maddr<13> 6 2<- \/1 0 FB2_5 1 GTS/I/O O maddr<8> 6 1<- 0 0 FB2_6 2 GTS/I/O O powerup 1 0 \/1 3 FB2_7 (b) (b) maddr<9> 6 1<- 0 0 FB2_8 3 GTS/I/O O maddr<11> 6 1<- 0 0 FB2_9 4 GTS/I/O O en_conf 1 0 /\1 3 FB2_10 (b) (b) mdata<0> 2 0 0 3 FB2_11 6 I/O I/O en_loc_bus 2 0 0 3 FB2_12 7 I/O (b) div<0> 2 0 0 3 FB2_13 (b) (b) mdata<1> 2 0 0 3 FB2_14 8 I/O I/O mdata<2> 2 0 0 3 FB2_15 9 I/O I/O cfg_done 2 0 0 3 FB2_16 (b) (b) mdata<3> 2 0 0 3 FB2_17 10 I/O I/O ring_os<0> 4 0 0 1 FB2_18 (b) (b) Signals Used by Logic in Function Block 1: loc_bus<3>.PIN 15: maddr<11> 28: maddr<7> 2: loc_bus<2>.PIN 16: maddr<12> 29: maddr<8> 3: loc_bus<1>.PIN 17: maddr<13> 30: maddr<9> 4: loc_bus<0>.PIN 18: maddr<14> 31: mdata<0> 5: cclk_fb 19: maddr<15> 32: mdata<1> 6: cfg_done 20: maddr<16> 33: mdata<3> 7: ctrl_in<1> 21: maddr<17> 34: mdata<5> 8: done 22: maddr<1> 35: mdata<6> 9: en_conf 23: maddr<2> 36: powerup 10: en_loc_bus 24: maddr<3> 37: sel_byte<0> 11: init_b 25: maddr<4> 38: sel_byte<1> 12: loc_mode 26: maddr<5> 39: w_data<6>/w_data<6>_TRST 13: maddr<0> 27: maddr<6> 40: wr_maddr 14: maddr<10> Signal 1 2 3 4 5 FB Name 0----+----0----+----0----+----0----+----0----+----0 Inputs maddr<14> .....XX...X.XXXXXX...XXXXXXXXX....XXXX.X.......... 23 maddr<13> .....XX...X.XXXXX....XXXXXXXXX...X.XXX.X.......... 22 maddr<8> .....XX...X.X........XXXXXXXX.X....XXX.X.......... 17 powerup ....................X..............X.............. 2 maddr<9> .....XX...X.X........XXXXXXXXX.X...XXX.X.......... 18 maddr<11> .....XX...X.XXX......XXXXXXXXX..X..XXX.X.......... 20 en_conf ........X...XXXXXXXXXXXXXXXXXX.................... 19 mdata<0> ...X..................................X........... 2 en_loc_bus .....X..XX........XXX............................. 6 div<0> ....X.....X........................X.............. 3 mdata<1> ..X...................................X........... 2 mdata<2> .X....................................X........... 2 cfg_done .......X..X.XXXXXXXXXXXXXXXXXX.....X.............. 21 mdata<3> X.....................................X........... 2 ring_os<0> ....XX....XX.......................X.............. 5 0----+----1----+----2----+----3----+----4----+----5 0 0 0 0 0 *********************************** FB3 *********************************** Number of function block inputs used/remaining: 36/18 Number of signals used by logic mapping into function block: 36 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use crc<18> 7 2<- 0 0 FB3_1 (b) (b) cclkp 4 1<- /\2 0 FB3_2 23 GCK/I/O O (unused) 0 0 /\1 4 FB3_3 (b) (b) crc<21> 5 0 0 0 FB3_4 (b) (b) crc<1> 5 0 0 0 FB3_5 24 I/O I cclk_fbp 1 0 \/2 2 FB3_6 25 I/O O crc<13> 5 2<- \/2 0 FB3_7 (b) (b) crc<12> 5 2<- \/2 0 FB3_8 27 GCK/I/O GCK/I crc<11> 5 2<- \/2 0 FB3_9 28 I/O I crc<5> 7 2<- 0 0 FB3_10 (b) (b) (unused) 0 0 \/4 1 FB3_11 29 I/O I crc<4> 7 4<- \/2 0 FB3_12 30 I/O I crc<19> 7 2<- 0 0 FB3_13 (b) (b) crc<2> 5 0 0 0 FB3_14 32 I/O I w_data<6>/w_data<6>_TRST 2 0 \/3 0 FB3_15 33 I/O I crc<16> 7 3<- \/1 0 FB3_16 (b) (b) crc<7> 11 6<- 0 0 FB3_17 34 I/O (b) (unused) 0 0 /\5 0 FB3_18 (b) (b) Signals Used by Logic in Function Block 1: Mxor_crc_5_xor0000__xor0000/Mxor_crc_5_xor0000__xor0000_D 13: crc<19> 25: ctrl_in<1> 2: mdata<7>.PIN 14: crc<20> 26: div<4> 3: mdata<4>.PIN 15: crc<21> 27: done 4: mdata<2>.PIN 16: crc<22> 28: en_conf 5: mdata<1>.PIN 17: crc<23> 29: init_b 6: cfg_done 18: crc<3> 30: loc_add<5> 7: crc<10> 19: crc<4> 31: loc_add<6> 8: crc<11> 20: crc<5> 32: loc_cs 9: crc<13> 21: crc<8> 33: loc_mode 10: crc<16> 22: crc_20_xor0001/crc_20_xor0001_D 34: loc_rw 11: crc<17> 23: crc_7_xor0002/crc_7_xor0002_D 35: powerup 12: crc<18> 24: ctrl_in<0> 36: ring_os<2> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs crc<18> .....XX..X...XX............XX.....X..... 8 cclkp .....X.................XXX...XXXXX...... 9 crc<21> .....X..X...X...X..........XX.....X..... 7 crc<1> ....XX...X.....X...........XX.....X..... 7 cclk_fbp ...................................X.... 1 crc<13> .....X.....X...X...X.......XX.....X..... 7 crc<12> .....X....X...X...X........XX.....X..... 7 crc<11> .....X...X...X...X.........XX.....X..... 7 crc<5> X....X...X.X..X............XX.....X..... 8 crc<4> ..X..X...X..X..X...........XX.....X..... 8 crc<19> .....X.X..X...XX...........XX.....X..... 8 crc<2> ...X.X....X.....X..........XX.....X..... 7 w_data<6>/w_data<6>_TRST ........................X.X.....XX...... 4 crc<16> .....X......XX......XX.....XX.....X..... 8 crc<7> .X...X...X....XX......X....XX.....X..... 9 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB4 *********************************** Number of function block inputs used/remaining: 32/22 Number of signals used by logic mapping into function block: 32 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 \/1 4 FB4_1 (b) (b) maddr<4> 6 1<- 0 0 FB4_2 87 I/O O (unused) 0 0 0 5 FB4_3 (b) (unused) 0 0 \/2 3 FB4_4 (b) (b) maddr<5> 6 2<- \/1 0 FB4_5 89 I/O O maddr<6> 6 1<- 0 0 FB4_6 90 I/O O (unused) 0 0 \/1 4 FB4_7 (b) (b) maddr<7> 6 1<- 0 0 FB4_8 91 I/O O maddr<12> 6 1<- 0 0 FB4_9 92 I/O O (unused) 0 0 /\1 4 FB4_10 (b) (b) maddr<15> 6 1<- 0 0 FB4_11 93 I/O O maddr<16> 6 2<- /\1 0 FB4_12 94 I/O O (unused) 0 0 /\2 3 FB4_13 (b) (b) maddr<18> 0 0 0 5 FB4_14 95 I/O O mwe_b 2 0 0 3 FB4_15 96 I/O O (unused) 0 0 \/1 4 FB4_16 (b) (b) maddr<17> 6 1<- 0 0 FB4_17 97 I/O O (unused) 0 0 0 5 FB4_18 (b) Signals Used by Logic in Function Block 1: cfg_done 12: maddr<16> 23: mdata<0> 2: ctrl_in<1> 13: maddr<17> 24: mdata<1> 3: init_b 14: maddr<1> 25: mdata<4> 4: loc_rw 15: maddr<2> 26: mdata<5> 5: maddr<0> 16: maddr<3> 27: mdata<6> 6: maddr<10> 17: maddr<4> 28: mdata<7> 7: maddr<11> 18: maddr<5> 29: powerup 8: maddr<12> 19: maddr<6> 30: sel_byte<0> 9: maddr<13> 20: maddr<7> 31: sel_byte<1> 10: maddr<14> 21: maddr<8> 32: wr_maddr 11: maddr<15> 22: maddr<9> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs maddr<4> XXX.X........XXXX.......X...XXXX........ 13 maddr<5> XXX.X........XXXXX.......X..XXXX........ 14 maddr<6> XXX.X........XXXXXX.......X.XXXX........ 15 maddr<7> XXX.X........XXXXXXX.......XXXXX........ 16 maddr<12> XXX.XXXX.....XXXXXXXXX..X...XXXX........ 21 maddr<15> XXX.XXXXXXX..XXXXXXXXX.....XXXXX........ 24 maddr<16> XXX.XXXXXXXX.XXXXXXXXXX.....XXXX........ 25 maddr<18> ........................................ 0 mwe_b XX.X.................................... 3 maddr<17> XXX.XXXXXXXXXXXXXXXXXX.X....XXXX........ 26 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB5 *********************************** Number of function block inputs used/remaining: 38/16 Number of signals used by logic mapping into function block: 38 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 /\1 4 FB5_1 (b) (b) (unused) 0 0 \/2 3 FB5_2 35 I/O I (unused) 0 0 \/5 0 FB5_3 (b) (b) crc<6> 11 7<- \/1 0 FB5_4 (b) (b) crc<15> 11 6<- 0 0 FB5_5 36 I/O I (unused) 0 0 /\5 0 FB5_6 37 I/O I (unused) 0 0 \/5 0 FB5_7 (b) (b) crc<0> 11 6<- 0 0 FB5_8 39 I/O (b) loc_bus<0> 9 5<- /\1 0 FB5_9 40 I/O I/O (unused) 0 0 /\5 0 FB5_10 (b) (b) (unused) 0 0 \/4 1 FB5_11 41 I/O (b) loc_bus<1> 9 4<- 0 0 FB5_12 42 I/O I/O (unused) 0 0 \/5 0 FB5_13 (b) (b) crc<3> 19 14<- 0 0 FB5_14 43 I/O (b) (unused) 0 0 /\5 0 FB5_15 46 I/O (b) (unused) 0 0 /\4 1 FB5_16 (b) (b) (unused) 0 0 \/5 0 FB5_17 49 I/O (b) crc<9> 11 6<- 0 0 FB5_18 (b) (b) Signals Used by Logic in Function Block 1: mdata<6>.PIN 14: crc<22> 27: loc_add<6> 2: mdata<3>.PIN 15: crc<23> 28: loc_cs 3: mdata<1>.PIN 16: crc<7> 29: loc_mode 4: mdata<0>.PIN 17: crc<8> 30: loc_rw 5: cfg_done 18: crc<9> 31: maddr<0> 6: crc<0> 19: crc_0_xor0001/crc_0_xor0001_D 32: maddr<16> 7: crc<16> 20: crc_13_xor0001/crc_13_xor0001_D 33: maddr<17> 8: crc<17> 21: en_conf 34: maddr<1> 9: crc<18> 22: en_loc_bus 35: maddr<8> 10: crc<19> 23: init_b 36: maddr<9> 11: crc<1> 24: loc_add<0> 37: powerup 12: crc<20> 25: loc_add<1> 38: prog 13: crc<21> 26: loc_add<5> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs crc<6> X...X.X.X...XX......X.X.............X... 9 crc<15> ....X..X.X..X..X...XX.X.............X... 9 crc<0> ...XX..XX...X.....X.X.X.............X... 9 loc_bus<0> ...X.XX.........X....X.XXXXXXXXX..X..... 15 loc_bus<1> ..X....X..X......X...X.XXXXX.X..XX.X.X.. 15 crc<3> .X..X.XX.X.XX.......X.X.............X... 10 crc<9> ....X...X.XX.XX.....X.X.............X... 9 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB6 *********************************** Number of function block inputs used/remaining: 35/19 Number of signals used by logic mapping into function block: 35 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 /\5 0 FB6_1 (b) (b) loc_add_out<4> 1 0 /\2 2 FB6_2 74 I/O O crc<23> 7 2<- 0 0 FB6_3 (b) (b) crc<20> 7 4<- /\2 0 FB6_4 (b) (b) loc_add_out<3> 1 0 /\4 0 FB6_5 76 I/O O loc_add_out<2> 1 0 \/1 3 FB6_6 77 I/O O crc<17> 7 2<- 0 0 FB6_7 (b) (b) loc_add_out<1> 1 0 /\1 3 FB6_8 78 I/O O loc_add_out<0> 1 0 \/2 2 FB6_9 79 I/O O crc<10> 7 2<- 0 0 FB6_10 (b) (b) (unused) 0 0 \/5 0 FB6_11 80 I/O (b) maddr<3> 6 5<- \/4 0 FB6_12 81 I/O O crc<8> 11 6<- 0 0 FB6_13 (b) (b) maddr<2> 6 3<- /\2 0 FB6_14 82 I/O O maddr<1> 6 4<- /\3 0 FB6_15 85 I/O O (unused) 0 0 /\4 1 FB6_16 (b) (b) maddr<0> 6 1<- 0 0 FB6_17 86 I/O O crc<14> 11 7<- /\1 0 FB6_18 (b) (b) Signals Used by Logic in Function Block 1: Mxor_crc_10_xor0000__xor0000/Mxor_crc_10_xor0000__xor0000_D 13: crc<9> 25: maddr<1> 2: Mxor_crc_23_xor0000__xor0000/Mxor_crc_23_xor0000__xor0000_D 14: crc_14_xor0001/crc_14_xor0001_D 26: maddr<2> 3: cfg_done 15: crc_7_xor0001/crc_7_xor0001_D 27: maddr<3> 4: crc<0> 16: ctrl_in<1> 28: mdata<0> 5: crc<12> 17: en_conf 29: mdata<1> 6: crc<16> 18: init_b 30: mdata<2> 7: crc<17> 19: loc_add<0> 31: mdata<3> 8: crc<18> 20: loc_add<1> 32: powerup 9: crc<19> 21: loc_add<2> 33: sel_byte<0> 10: crc<22> 22: loc_add<3> 34: sel_byte<1> 11: crc<23> 23: loc_add<4> 35: wr_maddr 12: crc<6> 24: maddr<0> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs loc_add_out<4> ......................X................. 1 crc<23> .XX..XXX........XX.............X........ 8 crc<20> ..X.X..X.XX.....XX.............X........ 8 loc_add_out<3> .....................X.................. 1 loc_add_out<2> ....................X................... 1 crc<17> ..X..X.X..X.X...XX.............X........ 8 loc_add_out<1> ...................X.................... 1 loc_add_out<0> ..................X..................... 1 crc<10> X.X...XX..X.....XX.............X........ 8 maddr<3> ..X............X.X.....XXXX...XXXXX..... 12 crc<8> ..XX..X.X.X...X.XX.............X........ 9 maddr<2> ..X............X.X.....XXX...X.XXXX..... 11 maddr<1> ..X............X.X.....XX...X..XXXX..... 10 maddr<0> ..X............X.X.....X...X...XXXX..... 9 crc<14> ..X...XX..XX.X..XX.............X........ 9 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB7 *********************************** Number of function block inputs used/remaining: 49/5 Number of signals used by logic mapping into function block: 49 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 \/2 3 FB7_1 (b) (b) loc_bus<2> 8 3<- 0 0 FB7_2 50 I/O I/O (unused) 0 0 /\1 4 FB7_3 (b) (b) (unused) 0 0 \/2 3 FB7_4 (b) (b) loc_bus<3> 8 3<- 0 0 FB7_5 52 I/O I/O (unused) 0 0 /\1 4 FB7_6 53 I/O (b) (unused) 0 0 \/2 3 FB7_7 (b) (b) loc_bus<4> 8 3<- 0 0 FB7_8 54 I/O I/O (unused) 0 0 /\1 4 FB7_9 55 I/O (b) (unused) 0 0 \/2 3 FB7_10 (b) (b) loc_bus<5> 8 3<- 0 0 FB7_11 56 I/O I/O spare5 1 0 /\1 3 FB7_12 58 I/O O (unused) 0 0 \/2 3 FB7_13 (b) (b) loc_bus<6> 8 3<- 0 0 FB7_14 59 I/O I/O (unused) 0 0 /\1 4 FB7_15 60 I/O (b) (unused) 0 0 \/1 4 FB7_16 (b) (b) loc_bus<7> 7 2<- 0 0 FB7_17 61 I/O I/O (unused) 0 0 /\1 4 FB7_18 (b) (b) Signals Used by Logic in Function Block 1: mdata<7>.PIN 18: crc<22> 34: loc_add<5> 2: mdata<6>.PIN 19: crc<23> 35: loc_add<6> 3: mdata<5>.PIN 20: crc<2> 36: loc_cs 4: mdata<4>.PIN 21: crc<3> 37: loc_rw 5: mdata<3>.PIN 22: crc<4> 38: maddr<10> 6: mdata<2>.PIN 23: crc<5> 39: maddr<11> 7: cfg_done 24: crc<6> 40: maddr<12> 8: crc<10> 25: crc<7> 41: maddr<13> 9: crc<11> 26: ctrl_in<0> 42: maddr<14> 10: crc<12> 27: ctrl_in<1> 43: maddr<15> 11: crc<13> 28: ctrl_in<2> 44: maddr<2> 12: crc<14> 29: done 45: maddr<3> 13: crc<15> 30: en_loc_bus 46: maddr<4> 14: crc<18> 31: init_b 47: maddr<5> 15: crc<19> 32: loc_add<0> 48: maddr<6> 16: crc<20> 33: loc_add<1> 49: maddr<7> 17: crc<21> Signal 1 2 3 4 5 FB Name 0----+----0----+----0----+----0----+----0----+----0 Inputs loc_bus<2> .....X.X.....X.....X.........XXXXXXXXX.....X...... 14 loc_bus<3> ....X...X.....X.....X.......XX.XXXXXX.X.....X..... 14 loc_bus<4> ...X.....X.....X.....X...X...X.XXXXXX..X.....X.... 14 loc_bus<5> ..X.......X.....X.....X...X..X.XXXXXX...X.....X... 14 spare5 ......X............................X.............. 2 loc_bus<6> .X.........X.....X.....X...X.X.XXXXXX....X.....X.. 14 loc_bus<7> X...........X.....X.....X....X.XXXXXX.....X.....X. 13 0----+----1----+----2----+----3----+----4----+----5 0 0 0 0 0 *********************************** FB8 *********************************** Number of function block inputs used/remaining: 21/33 Number of signals used by logic mapping into function block: 21 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use ring_os<2> 1 0 0 4 FB8_1 (b) (b) prog_b 1 0 0 4 FB8_2 63 I/O O ring_os<1> 1 0 0 4 FB8_3 (b) (b) div<4> 2 0 0 3 FB8_4 (b) (b) div<3> 2 0 0 3 FB8_5 64 I/O (b) div<2> 2 0 0 3 FB8_6 65 I/O I div<1> 2 0 0 3 FB8_7 (b) (b) crc_7_xor0001/crc_7_xor0001_D 2 0 0 3 FB8_8 66 I/O I crc_13_xor0001/crc_13_xor0001_D 2 0 0 3 FB8_9 67 I/O I crc_7_xor0002/crc_7_xor0002_D 3 0 0 2 FB8_10 (b) (b) crc_20_xor0001/crc_20_xor0001_D 3 0 0 2 FB8_11 68 I/O I crc_14_xor0001/crc_14_xor0001_D 3 0 0 2 FB8_12 70 I/O I crc_0_xor0001/crc_0_xor0001_D 3 0 0 2 FB8_13 (b) (b) loc_add_out<6> 1 0 0 4 FB8_14 71 I/O O loc_add_out<5> 1 0 0 4 FB8_15 72 I/O O Mxor_crc_5_xor0000__xor0000/Mxor_crc_5_xor0000__xor0000_D 3 0 0 2 FB8_16 (b) (b) Mxor_crc_23_xor0000__xor0000/Mxor_crc_23_xor0000__xor0000_D 3 0 0 2 FB8_17 73 I/O (b) Mxor_crc_10_xor0000__xor0000/Mxor_crc_10_xor0000__xor0000_D 3 0 0 2 FB8_18 (b) (b) Signals Used by Logic in Function Block 1: mdata<5>.PIN 8: crc<22> 15: init_b 2: crc<15> 9: crc<23> 16: loc_add<5> 3: crc<16> 10: crc<2> 17: loc_add<6> 4: crc<18> 11: div<0> 18: powerup 5: crc<19> 12: div<1> 19: prog 6: crc<20> 13: div<2> 20: ring_os<0> 7: crc<21> 14: div<3> 21: ring_os<1> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs ring_os<2> ....................X................... 1 prog_b .................XX..................... 2 ring_os<1> ...................X.................... 1 div<4> .............XX..X...................... 3 div<3> ............X.X..X...................... 3 div<2> ...........X..X..X...................... 3 div<1> ..........X...X..X...................... 3 crc_7_xor0001/crc_7_xor0001_D ......XX................................ 2 crc_13_xor0001/crc_13_xor0001_D ...X...X................................ 2 crc_7_xor0002/crc_7_xor0002_D ...X.X..X............................... 3 crc_20_xor0001/crc_20_xor0001_D ...X...XX............................... 3 crc_14_xor0001/crc_14_xor0001_D ..X..XX................................. 3 crc_0_xor0001/crc_0_xor0001_D ..X.XX.................................. 3 loc_add_out<6> ................X....................... 1 loc_add_out<5> ...............X........................ 1 Mxor_crc_5_xor0000__xor0000/Mxor_crc_5_xor0000__xor0000_D X...X...X............................... 3 Mxor_crc_23_xor0000__xor0000/Mxor_crc_23_xor0000__xor0000_D .X..XX.................................. 3 Mxor_crc_10_xor0000__xor0000/Mxor_crc_10_xor0000__xor0000_D ..X..X...X.............................. 3 0----+----1----+----2----+----3----+----4 0 0 0 0 ******************************* Equations ******************************** ********** Mapped Logic ********** Mxor_crc_10_xor0000__xor0000/Mxor_crc_10_xor0000__xor0000_D <= NOT (crc(16) XOR Mxor_crc_10_xor0000__xor0000/Mxor_crc_10_xor0000__xor0000_D <= NOT (((crc(20) AND crc(2)) OR (NOT crc(20) AND NOT crc(2)))); Mxor_crc_23_xor0000__xor0000/Mxor_crc_23_xor0000__xor0000_D <= NOT (crc(19) XOR Mxor_crc_23_xor0000__xor0000/Mxor_crc_23_xor0000__xor0000_D <= NOT (((crc(20) AND crc(15)) OR (NOT crc(20) AND NOT crc(15)))); Mxor_crc_5_xor0000__xor0000/Mxor_crc_5_xor0000__xor0000_D <= NOT (crc(19) XOR Mxor_crc_5_xor0000__xor0000/Mxor_crc_5_xor0000__xor0000_D <= NOT (((crc(23) AND mdata(5).PIN) OR (NOT crc(23) AND NOT mdata(5).PIN))); cclk_fbp <= ring_os(2); cclkp <= NOT (((EXP12_.EXP) OR (cfg_done AND NOT ctrl_in(0)) OR (NOT loc_cs AND cfg_done AND ctrl_in(1)) OR (NOT cfg_done AND NOT loc_mode AND div(4)))); FDCPE_cfg_done: FDCPE port map (cfg_done,'1',cclk,cfg_done_CLR,'0',cfg_done_CE); cfg_done_CLR <= (NOT init_b AND NOT powerup); cfg_done_CE <= (done AND maddr(0) AND NOT maddr(15) AND maddr(16) AND maddr(17) AND maddr(1) AND maddr(2) AND NOT maddr(3) AND NOT maddr(4) AND maddr(5) AND NOT maddr(6) AND maddr(8) AND maddr(10) AND maddr(11) AND maddr(12) AND maddr(13) AND NOT maddr(14) AND maddr(7) AND NOT maddr(9)); FDCPE_crc0: FDCPE port map (crc(0),crc_D(0),cclk,'0',crc_PRE(0),crc_CE(0)); crc_D(0) <= crc(17) XOR crc_D(0) <= ((EXP25_.EXP) OR (r_data(0).EXP) OR (crc(18) AND crc(21) AND mdata(0).PIN AND crc_0_xor0001/crc_0_xor0001_D) OR (crc(18) AND crc(21) AND NOT mdata(0).PIN AND NOT crc_0_xor0001/crc_0_xor0001_D)); crc_PRE(0) <= (NOT init_b AND NOT powerup); crc_CE(0) <= (NOT cfg_done AND en_conf); FDCPE_crc1: FDCPE port map (crc(1),crc_D(1),cclk,'0',crc_PRE(1),crc_CE(1)); crc_D(1) <= crc(22) XOR crc_D(1) <= ((crc(16) AND mdata(1).PIN) OR (NOT crc(16) AND NOT mdata(1).PIN)); crc_PRE(1) <= (NOT init_b AND NOT powerup); crc_CE(1) <= (NOT cfg_done AND en_conf); FDCPE_crc2: FDCPE port map (crc(2),crc_D(2),cclk,'0',crc_PRE(2),crc_CE(2)); crc_D(2) <= crc(17) XOR crc_D(2) <= ((crc(23) AND mdata(2).PIN) OR (NOT crc(23) AND NOT mdata(2).PIN)); crc_PRE(2) <= (NOT init_b AND NOT powerup); crc_CE(2) <= (NOT cfg_done AND en_conf); FDCPE_crc3: FDCPE port map (crc(3),crc_D(3),cclk,'0',crc_PRE(3),crc_CE(3)); crc_D(3) <= crc(19) XOR crc_D(3) <= ((EXP28_.EXP) OR (EXP29_.EXP) OR (crc(16) AND crc(17) AND crc(20) AND crc(21) AND NOT mdata(3).PIN) OR (crc(16) AND crc(17) AND crc(20) AND NOT crc(21) AND mdata(3).PIN)); crc_PRE(3) <= (NOT init_b AND NOT powerup); crc_CE(3) <= (NOT cfg_done AND en_conf); FDCPE_crc4: FDCPE port map (crc(4),crc_D(4),cclk,'0',crc_PRE(4),crc_CE(4)); crc_D(4) <= crc(22) XOR crc_D(4) <= EXP13_.EXP; crc_PRE(4) <= (NOT init_b AND NOT powerup); crc_CE(4) <= (NOT cfg_done AND en_conf); FDCPE_crc5: FDCPE port map (crc(5),crc_D(5),cclk,'0',crc_PRE(5),crc_CE(5)); crc_D(5) <= crc(16) XOR crc_D(5) <= ((crc(11).EXP) OR (crc(18) AND crc(21) AND NOT Mxor_crc_5_xor0000__xor0000/Mxor_crc_5_xor0000__xor0000_D) OR (crc(18) AND NOT crc(21) AND Mxor_crc_5_xor0000__xor0000/Mxor_crc_5_xor0000__xor0000_D)); crc_PRE(5) <= (NOT init_b AND NOT powerup); crc_CE(5) <= (NOT cfg_done AND en_conf); FDCPE_crc6: FDCPE port map (crc(6),crc_D(6),cclk,'0',crc_PRE(6),crc_CE(6)); crc_D(6) <= crc(22) XOR crc_D(6) <= ((EXP23_.EXP) OR (crc(16) AND crc(18) AND crc(21) AND mdata(6).PIN)); crc_PRE(6) <= (NOT init_b AND NOT powerup); crc_CE(6) <= (NOT cfg_done AND en_conf); FDCPE_crc7: FDCPE port map (crc(7),crc_D(7),cclk,'0',crc_PRE(7),crc_CE(7)); crc_D(7) <= crc(22) XOR crc_D(7) <= ((crc(16).EXP) OR (EXP14_.EXP) OR (crc(16) AND crc(21) AND mdata(7).PIN AND crc_7_xor0002/crc_7_xor0002_D) OR (crc(16) AND crc(21) AND NOT mdata(7).PIN AND NOT crc_7_xor0002/crc_7_xor0002_D)); crc_PRE(7) <= (NOT init_b AND NOT powerup); crc_CE(7) <= (NOT cfg_done AND en_conf); FDCPE_crc8: FDCPE port map (crc(8),crc_D(8),cclk,'0',crc_PRE(8),crc_CE(8)); crc_D(8) <= crc(19) XOR crc_D(8) <= ((maddr_cntr(3).EXP) OR (maddr_cntr(2).EXP) OR (crc(17) AND crc(23) AND crc(0) AND crc_7_xor0001/crc_7_xor0001_D) OR (crc(17) AND crc(23) AND NOT crc(0) AND NOT crc_7_xor0001/crc_7_xor0001_D)); crc_PRE(8) <= (NOT init_b AND NOT powerup); crc_CE(8) <= (NOT cfg_done AND en_conf); FDCPE_crc9: FDCPE port map (crc(9),crc_D(9),cclk,'0',crc_PRE(9),crc_CE(9)); crc_D(9) <= crc(22) XOR crc_D(9) <= ((EXP21_.EXP) OR (EXP31_.EXP) OR (crc(18) AND crc(20) AND crc(23) AND crc(1)) OR (crc(18) AND crc(20) AND NOT crc(23) AND NOT crc(1))); crc_PRE(9) <= (NOT init_b AND NOT powerup); crc_CE(9) <= (NOT cfg_done AND en_conf); FDCPE_crc10: FDCPE port map (crc(10),crc_D(10),cclk,'0',crc_PRE(10),crc_CE(10)); crc_D(10) <= crc(17) XOR crc_D(10) <= ((loc_add_out_0_OBUF$BUF0.EXP) OR (crc(18) AND crc(23) AND NOT Mxor_crc_10_xor0000__xor0000/Mxor_crc_10_xor0000__xor0000_D) OR (crc(18) AND NOT crc(23) AND Mxor_crc_10_xor0000__xor0000/Mxor_crc_10_xor0000__xor0000_D)); crc_PRE(10) <= (NOT init_b AND NOT powerup); crc_CE(10) <= (NOT cfg_done AND en_conf); FDCPE_crc11: FDCPE port map (crc(11),crc_D(11),cclk,'0',crc_PRE(11),crc_CE(11)); crc_D(11) <= crc(16) XOR crc_D(11) <= crc(12).EXP; crc_PRE(11) <= (NOT init_b AND NOT powerup); crc_CE(11) <= (NOT cfg_done AND en_conf); FDCPE_crc12: FDCPE port map (crc(12),crc_D(12),cclk,'0',crc_PRE(12),crc_CE(12)); crc_D(12) <= crc(17) XOR crc_D(12) <= crc(13).EXP; crc_PRE(12) <= (NOT init_b AND NOT powerup); crc_CE(12) <= (NOT cfg_done AND en_conf); FDCPE_crc13: FDCPE port map (crc(13),crc_D(13),cclk,'0',crc_PRE(13),crc_CE(13)); crc_D(13) <= crc(22) XOR crc_D(13) <= ring_os(3).EXP; crc_PRE(13) <= (NOT init_b AND NOT powerup); crc_CE(13) <= (NOT cfg_done AND en_conf); FDCPE_crc14: FDCPE port map (crc(14),crc_D(14),cclk,'0',crc_PRE(14),crc_CE(14)); crc_D(14) <= crc(17) XOR crc_D(14) <= ((EXP32_.EXP) OR (crc(18) AND crc(23) AND crc(6) AND crc_14_xor0001/crc_14_xor0001_D)); crc_PRE(14) <= (NOT init_b AND NOT powerup); crc_CE(14) <= (NOT cfg_done AND en_conf); FDCPE_crc15: FDCPE port map (crc(15),crc_D(15),cclk,'0',crc_PRE(15),crc_CE(15)); crc_D(15) <= crc(19) XOR crc_D(15) <= ((crc(6).EXP) OR (EXP24_.EXP) OR (crc(17) AND crc(21) AND crc(7) AND crc_13_xor0001/crc_13_xor0001_D) OR (crc(17) AND crc(21) AND NOT crc(7) AND NOT crc_13_xor0001/crc_13_xor0001_D)); crc_PRE(15) <= (NOT init_b AND NOT powerup); crc_CE(15) <= (NOT cfg_done AND en_conf); FDCPE_crc16: FDCPE port map (crc(16),crc_D(16),cclk,'0',crc_PRE(16),crc_CE(16)); crc_D(16) <= crc(19) XOR crc_D(16) <= ((w_data(6)/w_data(6)_TRST.EXP) OR (crc(20) AND crc(8) AND NOT crc_20_xor0001/crc_20_xor0001_D)); crc_PRE(16) <= (NOT init_b AND NOT powerup); crc_CE(16) <= (NOT cfg_done AND en_conf); FTCPE_crc17: FTCPE port map (crc(17),crc_T(17),cclk,'0',crc_PRE(17),crc_CE(17)); crc_T(17) <= crc(16) XOR crc_T(17) <= ((loc_add_out_2_OBUF$BUF0.EXP) OR (loc_add_out_1_OBUF$BUF0.EXP) OR (crc(18) AND crc(23) AND NOT crc(9)) OR (crc(18) AND NOT crc(23) AND crc(9))); crc_PRE(17) <= (NOT init_b AND NOT powerup); crc_CE(17) <= (NOT cfg_done AND en_conf); FDCPE_crc18: FDCPE port map (crc(18),crc_D(18),cclk,'0',crc_PRE(18),crc_CE(18)); crc_D(18) <= crc(16) XOR crc_D(18) <= ((cclkp_OBUF.EXP) OR (crc(20) AND crc(21) AND NOT crc(10)) OR (crc(20) AND NOT crc(21) AND crc(10))); crc_PRE(18) <= (NOT init_b AND NOT powerup); crc_CE(18) <= (NOT cfg_done AND en_conf); FDCPE_crc19: FDCPE port map (crc(19),crc_D(19),cclk,'0',crc_PRE(19),crc_CE(19)); crc_D(19) <= crc(22) XOR crc_D(19) <= ((crc(4).EXP) OR (crc(17) AND crc(21) AND NOT crc(11)) OR (crc(17) AND NOT crc(21) AND crc(11))); crc_PRE(19) <= (NOT init_b AND NOT powerup); crc_CE(19) <= (NOT cfg_done AND en_conf); FDCPE_crc20: FDCPE port map (crc(20),crc_D(20),cclk,'0',crc_PRE(20),crc_CE(20)); crc_D(20) <= crc(22) XOR crc_D(20) <= loc_add_out_3_OBUF$BUF0.EXP; crc_PRE(20) <= (NOT init_b AND NOT powerup); crc_CE(20) <= (NOT cfg_done AND en_conf); FDCPE_crc21: FDCPE port map (crc(21),crc_D(21),cclk,'0',crc_PRE(21),crc_CE(21)); crc_D(21) <= crc(19) XOR crc_D(21) <= ((crc(23) AND crc(13)) OR (NOT crc(23) AND NOT crc(13))); crc_PRE(21) <= (NOT init_b AND NOT powerup); crc_CE(21) <= (NOT cfg_done AND en_conf); FDCPE_crc22: FDCPE port map (crc(22),crc_D(22),cclk,'0',crc_PRE(22),crc_CE(22)); crc_D(22) <= crc(20) XOR crc_D(22) <= crc(14); crc_PRE(22) <= (NOT init_b AND NOT powerup); crc_CE(22) <= (NOT cfg_done AND en_conf); FDCPE_crc23: FDCPE port map (crc(23),crc_D(23),cclk,'0',crc_PRE(23),crc_CE(23)); crc_D(23) <= crc(16) XOR crc_D(23) <= ((crc(20).EXP) OR (crc(17) AND crc(18) AND NOT Mxor_crc_23_xor0000__xor0000/Mxor_crc_23_xor0000__xor0000_D) OR (crc(17) AND NOT crc(18) AND Mxor_crc_23_xor0000__xor0000/Mxor_crc_23_xor0000__xor0000_D)); crc_PRE(23) <= (NOT init_b AND NOT powerup); crc_CE(23) <= (NOT cfg_done AND en_conf); crc_0_xor0001/crc_0_xor0001_D <= NOT (crc(19) XOR crc_0_xor0001/crc_0_xor0001_D <= NOT (((crc(16) AND crc(20)) OR (NOT crc(16) AND NOT crc(20)))); crc_13_xor0001/crc_13_xor0001_D <= crc(22) XOR crc_13_xor0001/crc_13_xor0001_D <= crc(18); crc_14_xor0001/crc_14_xor0001_D <= NOT (crc(16) XOR crc_14_xor0001/crc_14_xor0001_D <= NOT (((crc(20) AND crc(21)) OR (NOT crc(20) AND NOT crc(21)))); crc_20_xor0001/crc_20_xor0001_D <= NOT (crc(22) XOR crc_20_xor0001/crc_20_xor0001_D <= NOT (((crc(18) AND crc(23)) OR (NOT crc(18) AND NOT crc(23)))); crc_7_xor0001/crc_7_xor0001_D <= crc(22) XOR crc_7_xor0001/crc_7_xor0001_D <= crc(21); crc_7_xor0002/crc_7_xor0002_D <= NOT (crc(18) XOR crc_7_xor0002/crc_7_xor0002_D <= NOT (((crc(20) AND crc(23)) OR (NOT crc(20) AND NOT crc(23)))); cs_b <= NOT (((NOT loc_cs AND cfg_done) OR (NOT cfg_done AND init_b AND en_conf))); FTCPE_div0: FTCPE port map (div(0),'1',cclk_fb,div_CLR(0),'0'); div_CLR(0) <= (NOT init_b AND NOT powerup); FTCPE_div1: FTCPE port map (div(1),'1',NOT div(0),div_CLR(1),'0'); div_CLR(1) <= (NOT init_b AND NOT powerup); FTCPE_div2: FTCPE port map (div(2),'1',NOT div(1),div_CLR(2),'0'); div_CLR(2) <= (NOT init_b AND NOT powerup); FTCPE_div3: FTCPE port map (div(3),'1',NOT div(2),div_CLR(3),'0'); div_CLR(3) <= (NOT init_b AND NOT powerup); FTCPE_div4: FTCPE port map (div(4),'1',NOT div(3),div_CLR(4),'0'); div_CLR(4) <= (NOT init_b AND NOT powerup); FTCPE_en_conf: FTCPE port map (en_conf,en_conf_T,cclk,'0','0'); en_conf_T <= (maddr(0) AND maddr(15) AND maddr(16) AND maddr(17) AND maddr(1) AND maddr(2) AND maddr(3) AND maddr(4) AND maddr(5) AND maddr(6) AND maddr(8) AND maddr(10) AND maddr(11) AND maddr(12) AND maddr(13) AND maddr(14) AND maddr(7) AND maddr(9) AND NOT en_conf); FTCPE_en_loc_bus: FTCPE port map (en_loc_bus,en_loc_bus_T,cclk,'0','0'); en_loc_bus_T <= ((cfg_done AND NOT en_loc_bus) OR (maddr(15) AND maddr(16) AND maddr(17) AND en_conf AND NOT en_loc_bus)); loc_add_out(0) <= loc_add(0); loc_add_out(1) <= loc_add(1); loc_add_out(2) <= loc_add(2); loc_add_out(3) <= loc_add(3); loc_add_out(4) <= loc_add(4); loc_add_out(5) <= loc_add(5); loc_add_out(6) <= loc_add(6); loc_bus_I(0) <= NOT (((EXP26_.EXP) OR (NOT loc_add(6) AND NOT mdata(0).PIN) OR (NOT maddr(8) AND loc_add(6) AND loc_add(5) AND NOT loc_add(1) AND loc_add(0)) OR (NOT crc(8) AND loc_add(6) AND NOT loc_add(5) AND NOT loc_add(1) AND loc_add(0)))); loc_bus(0) <= loc_bus_I(0) when loc_bus_OE(0) = '1' else 'Z'; loc_bus_OE(0) <= (loc_rw AND NOT loc_cs AND en_loc_bus); loc_bus_I(1) <= ((EXP27_.EXP) OR (mdata(1).PIN AND NOT loc_add(6)) OR (maddr(1) AND loc_add(6) AND loc_add(5) AND NOT loc_add(1) AND NOT loc_add(0)) OR (crc(17) AND loc_add(6) AND NOT loc_add(5) AND loc_add(1) AND NOT loc_add(0)) OR (crc(1) AND loc_add(6) AND NOT loc_add(5) AND NOT loc_add(1) AND NOT loc_add(0))); loc_bus(1) <= loc_bus_I(1) when loc_bus_OE(1) = '1' else 'Z'; loc_bus_OE(1) <= (loc_rw AND NOT loc_cs AND en_loc_bus); loc_bus_I(2) <= ((EXP35_.EXP) OR (EXP36_.EXP) OR (mdata(2).PIN AND NOT loc_add(6)) OR (maddr(2) AND loc_add(6) AND loc_add(5) AND NOT loc_add(1) AND NOT loc_add(0)) OR (crc(10) AND loc_add(6) AND NOT loc_add(5) AND NOT loc_add(1) AND loc_add(0)) OR (crc(2) AND loc_add(6) AND NOT loc_add(5) AND NOT loc_add(1) AND NOT loc_add(0))); loc_bus(2) <= loc_bus_I(2) when loc_bus_OE(2) = '1' else 'Z'; loc_bus_OE(2) <= (loc_rw AND NOT loc_cs AND en_loc_bus); loc_bus_I(3) <= ((EXP37_.EXP) OR (EXP38_.EXP) OR (NOT loc_add(6) AND mdata(3).PIN) OR (maddr(3) AND loc_add(6) AND loc_add(5) AND NOT loc_add(1) AND NOT loc_add(0)) OR (crc(11) AND loc_add(6) AND NOT loc_add(5) AND NOT loc_add(1) AND loc_add(0)) OR (crc(3) AND loc_add(6) AND NOT loc_add(5) AND NOT loc_add(1) AND NOT loc_add(0))); loc_bus(3) <= loc_bus_I(3) when loc_bus_OE(3) = '1' else 'Z'; loc_bus_OE(3) <= (loc_rw AND NOT loc_cs AND en_loc_bus); loc_bus_I(4) <= ((EXP39_.EXP) OR (EXP40_.EXP) OR (NOT loc_add(6) AND mdata(4).PIN) OR (maddr(4) AND loc_add(6) AND loc_add(5) AND NOT loc_add(1) AND NOT loc_add(0)) OR (crc(12) AND loc_add(6) AND NOT loc_add(5) AND NOT loc_add(1) AND loc_add(0)) OR (crc(4) AND loc_add(6) AND NOT loc_add(5) AND NOT loc_add(1) AND NOT loc_add(0))); loc_bus(4) <= loc_bus_I(4) when loc_bus_OE(4) = '1' else 'Z'; loc_bus_OE(4) <= (loc_rw AND NOT loc_cs AND en_loc_bus); loc_bus_I(5) <= ((EXP41_.EXP) OR (spare5_OBUF.EXP) OR (NOT loc_add(6) AND mdata(5).PIN) OR (maddr(5) AND loc_add(6) AND loc_add(5) AND NOT loc_add(1) AND NOT loc_add(0)) OR (crc(13) AND loc_add(6) AND NOT loc_add(5) AND NOT loc_add(1) AND loc_add(0)) OR (crc(5) AND loc_add(6) AND NOT loc_add(5) AND NOT loc_add(1) AND NOT loc_add(0))); loc_bus(5) <= loc_bus_I(5) when loc_bus_OE(5) = '1' else 'Z'; loc_bus_OE(5) <= (loc_rw AND NOT loc_cs AND en_loc_bus); loc_bus_I(6) <= ((EXP42_.EXP) OR (EXP43_.EXP) OR (NOT loc_add(6) AND mdata(6).PIN) OR (maddr(6) AND loc_add(6) AND loc_add(5) AND NOT loc_add(1) AND NOT loc_add(0)) OR (crc(14) AND loc_add(6) AND NOT loc_add(5) AND NOT loc_add(1) AND loc_add(0)) OR (crc(6) AND loc_add(6) AND NOT loc_add(5) AND NOT loc_add(1) AND NOT loc_add(0))); loc_bus(6) <= loc_bus_I(6) when loc_bus_OE(6) = '1' else 'Z'; loc_bus_OE(6) <= (loc_rw AND NOT loc_cs AND en_loc_bus); loc_bus_I(7) <= ((EXP44_.EXP) OR (EXP45_.EXP) OR (NOT loc_add(6) AND mdata(7).PIN) OR (maddr(7) AND loc_add(6) AND loc_add(5) AND NOT loc_add(1) AND NOT loc_add(0)) OR (crc(15) AND loc_add(6) AND NOT loc_add(5) AND NOT loc_add(1) AND loc_add(0)) OR (crc(7) AND loc_add(6) AND NOT loc_add(5) AND NOT loc_add(1) AND NOT loc_add(0))); loc_bus(7) <= loc_bus_I(7) when loc_bus_OE(7) = '1' else 'Z'; loc_bus_OE(7) <= (loc_rw AND NOT loc_cs AND en_loc_bus); FDCPE_loc_mode: FDCPE port map (loc_mode,loc_bus(0).PIN,NOT loc_cs,'0','0',loc_mode_CE); loc_mode_CE <= (NOT loc_rw AND loc_add(6) AND NOT loc_add(5) AND NOT loc_add(4) AND NOT loc_add(3) AND NOT loc_add(2) AND loc_add(1) AND loc_add(0) AND en_loc_bus); FTCPE_maddr0: FTCPE port map (maddr(0),maddr_T(0),cclk,maddr_CLR(0),'0'); maddr_T(0) <= ((NOT cfg_done) OR (crc(14).EXP) OR (NOT ctrl_in(1) AND NOT wr_maddr) OR (maddr(0) AND NOT mdata(0) AND wr_maddr AND NOT sel_byte(0) AND NOT sel_byte(1)) OR (NOT maddr(0) AND mdata(0) AND wr_maddr AND NOT sel_byte(0) AND NOT sel_byte(1))); maddr_CLR(0) <= (NOT init_b AND NOT powerup); FTCPE_maddr1: FTCPE port map (maddr(1),maddr_T(1),cclk,maddr_CLR(1),'0'); maddr_T(1) <= ((EXP34_.EXP) OR (maddr(0) AND NOT cfg_done)); maddr_CLR(1) <= (NOT init_b AND NOT powerup); FTCPE_maddr2: FTCPE port map (maddr(2),maddr_T(2),cclk,maddr_CLR(2),'0'); maddr_T(2) <= ((maddr_cntr(1).EXP) OR (maddr(0) AND maddr(1) AND NOT cfg_done) OR (maddr(0) AND maddr(1) AND NOT ctrl_in(1) AND NOT wr_maddr)); maddr_CLR(2) <= (NOT init_b AND NOT powerup); FTCPE_maddr3: FTCPE port map (maddr(3),EXP33_.EXP,cclk,maddr_CLR(3),'0'); maddr_CLR(3) <= (NOT init_b AND NOT powerup); FTCPE_maddr4: FTCPE port map (maddr(4),maddr_T(4),cclk,maddr_CLR(4),'0'); maddr_T(4) <= ((EXP15_.EXP) OR (maddr(0) AND maddr(1) AND maddr(2) AND maddr(3) AND NOT cfg_done) OR (maddr(0) AND maddr(1) AND maddr(2) AND maddr(3) AND NOT ctrl_in(1) AND NOT wr_maddr) OR (maddr(4) AND NOT mdata(4) AND cfg_done AND wr_maddr AND NOT sel_byte(0) AND NOT sel_byte(1)) OR (NOT maddr(4) AND mdata(4) AND cfg_done AND wr_maddr AND NOT sel_byte(0) AND NOT sel_byte(1))); maddr_CLR(4) <= (NOT init_b AND NOT powerup); FTCPE_maddr5: FTCPE port map (maddr(5),maddr_T(5),cclk,maddr_CLR(5),'0'); maddr_T(5) <= ((EXP16_.EXP) OR (maddr(0) AND maddr(1) AND maddr(2) AND maddr(3) AND maddr(4) AND NOT cfg_done) OR (NOT maddr(5) AND mdata(5) AND cfg_done AND wr_maddr AND NOT sel_byte(0) AND NOT sel_byte(1)) OR (maddr(0) AND maddr(1) AND maddr(2) AND maddr(3) AND maddr(4) AND NOT ctrl_in(1) AND NOT wr_maddr)); maddr_CLR(5) <= (NOT init_b AND NOT powerup); FTCPE_maddr6: FTCPE port map (maddr(6),maddr_T(6),cclk,maddr_CLR(6),'0'); maddr_T(6) <= ((maddr_cntr(5).EXP) OR (maddr(6) AND NOT mdata(6) AND cfg_done AND wr_maddr AND NOT sel_byte(0) AND NOT sel_byte(1)) OR (NOT maddr(6) AND mdata(6) AND cfg_done AND wr_maddr AND NOT sel_byte(0) AND NOT sel_byte(1)) OR (maddr(0) AND maddr(1) AND maddr(2) AND maddr(3) AND maddr(4) AND maddr(5) AND NOT cfg_done) OR (maddr(0) AND maddr(1) AND maddr(2) AND maddr(3) AND maddr(4) AND maddr(5) AND NOT ctrl_in(1) AND NOT wr_maddr)); maddr_CLR(6) <= (NOT init_b AND NOT powerup); FTCPE_maddr7: FTCPE port map (maddr(7),maddr_T(7),cclk,maddr_CLR(7),'0'); maddr_T(7) <= ((EXP17_.EXP) OR (maddr(7) AND NOT mdata(7) AND cfg_done AND wr_maddr AND NOT sel_byte(0) AND NOT sel_byte(1)) OR (NOT maddr(7) AND mdata(7) AND cfg_done AND wr_maddr AND NOT sel_byte(0) AND NOT sel_byte(1)) OR (maddr(0) AND maddr(1) AND maddr(2) AND maddr(3) AND maddr(4) AND maddr(5) AND maddr(6) AND NOT cfg_done) OR (maddr(0) AND maddr(1) AND maddr(2) AND maddr(3) AND maddr(4) AND maddr(5) AND maddr(6) AND NOT ctrl_in(1) AND NOT wr_maddr)); maddr_CLR(7) <= (NOT init_b AND NOT powerup); FTCPE_maddr8: FTCPE port map (maddr(8),maddr_T(8),cclk,maddr_CLR(8),'0'); maddr_T(8) <= ((maddr_cntr(13).EXP) OR (maddr(8) AND NOT mdata(0) AND cfg_done AND wr_maddr AND sel_byte(0)) OR (NOT maddr(8) AND mdata(0) AND cfg_done AND wr_maddr AND sel_byte(0) AND NOT sel_byte(1)) OR (maddr(0) AND maddr(1) AND maddr(2) AND maddr(3) AND maddr(4) AND maddr(5) AND maddr(6) AND maddr(7) AND NOT cfg_done) OR (maddr(0) AND maddr(1) AND maddr(2) AND maddr(3) AND maddr(4) AND maddr(5) AND maddr(6) AND maddr(7) AND NOT ctrl_in(1) AND NOT wr_maddr)); maddr_CLR(8) <= (NOT init_b AND NOT powerup); FTCPE_maddr9: FTCPE port map (maddr(9),maddr_T(9),cclk,maddr_CLR(9),'0'); maddr_T(9) <= ((powerup.EXP) OR (maddr(9) AND NOT mdata(1) AND cfg_done AND wr_maddr AND sel_byte(0)) OR (NOT maddr(9) AND mdata(1) AND cfg_done AND wr_maddr AND sel_byte(0) AND NOT sel_byte(1)) OR (maddr(0) AND maddr(1) AND maddr(2) AND maddr(3) AND maddr(4) AND maddr(5) AND maddr(6) AND maddr(8) AND maddr(7) AND NOT cfg_done) OR (maddr(0) AND maddr(1) AND maddr(2) AND maddr(3) AND maddr(4) AND maddr(5) AND maddr(6) AND maddr(8) AND maddr(7) AND NOT ctrl_in(1) AND NOT wr_maddr)); maddr_CLR(9) <= (NOT init_b AND NOT powerup); FTCPE_maddr10: FTCPE port map (maddr(10),maddr_T(10),cclk,maddr_CLR(10),'0'); maddr_T(10) <= ((mce_b_OBUF.EXP) OR (maddr(10) AND NOT mdata(2) AND cfg_done AND wr_maddr AND sel_byte(0)) OR (NOT maddr(10) AND mdata(2) AND cfg_done AND wr_maddr AND sel_byte(0) AND NOT sel_byte(1)) OR (maddr(0) AND maddr(1) AND maddr(2) AND maddr(3) AND maddr(4) AND maddr(5) AND maddr(6) AND maddr(8) AND maddr(7) AND maddr(9) AND NOT cfg_done) OR (maddr(0) AND maddr(1) AND maddr(2) AND maddr(3) AND maddr(4) AND maddr(5) AND maddr(6) AND maddr(8) AND maddr(7) AND maddr(9) AND NOT ctrl_in(1) AND NOT wr_maddr)); maddr_CLR(10) <= (NOT init_b AND NOT powerup); FTCPE_maddr11: FTCPE port map (maddr(11),maddr_T(11),cclk,maddr_CLR(11),'0'); maddr_T(11) <= ((en_conf.EXP) OR (maddr(11) AND NOT mdata(3) AND cfg_done AND wr_maddr AND sel_byte(0)) OR (NOT maddr(11) AND mdata(3) AND cfg_done AND wr_maddr AND sel_byte(0) AND NOT sel_byte(1)) OR (maddr(0) AND maddr(1) AND maddr(2) AND maddr(3) AND maddr(4) AND maddr(5) AND maddr(6) AND maddr(8) AND maddr(10) AND maddr(7) AND maddr(9) AND NOT cfg_done) OR (maddr(0) AND maddr(1) AND maddr(2) AND maddr(3) AND maddr(4) AND maddr(5) AND maddr(6) AND maddr(8) AND maddr(10) AND maddr(7) AND maddr(9) AND NOT ctrl_in(1) AND NOT wr_maddr)); maddr_CLR(11) <= (NOT init_b AND NOT powerup); FTCPE_maddr12: FTCPE port map (maddr(12),maddr_T(12),cclk,maddr_CLR(12),'0'); maddr_T(12) <= ((EXP18_.EXP) OR (maddr(12) AND NOT mdata(4) AND cfg_done AND wr_maddr AND sel_byte(0)) OR (NOT maddr(12) AND mdata(4) AND cfg_done AND wr_maddr AND sel_byte(0) AND NOT sel_byte(1)) OR (maddr(0) AND maddr(1) AND maddr(2) AND maddr(3) AND maddr(4) AND maddr(5) AND maddr(6) AND maddr(8) AND maddr(10) AND maddr(11) AND maddr(7) AND maddr(9) AND NOT cfg_done) OR (maddr(0) AND maddr(1) AND maddr(2) AND maddr(3) AND maddr(4) AND maddr(5) AND maddr(6) AND maddr(8) AND maddr(10) AND maddr(11) AND maddr(7) AND maddr(9) AND NOT ctrl_in(1) AND NOT wr_maddr)); maddr_CLR(12) <= (NOT init_b AND NOT powerup); FTCPE_maddr13: FTCPE port map (maddr(13),maddr_T(13),cclk,maddr_CLR(13),'0'); maddr_T(13) <= ((EXP11_.EXP) OR (NOT maddr(13) AND mdata(5) AND cfg_done AND wr_maddr AND sel_byte(0) AND NOT sel_byte(1)) OR (maddr(0) AND maddr(1) AND maddr(2) AND maddr(3) AND maddr(4) AND maddr(5) AND maddr(6) AND maddr(8) AND maddr(10) AND maddr(11) AND maddr(12) AND maddr(7) AND maddr(9) AND NOT cfg_done) OR (maddr(0) AND maddr(1) AND maddr(2) AND maddr(3) AND maddr(4) AND maddr(5) AND maddr(6) AND maddr(8) AND maddr(10) AND maddr(11) AND maddr(12) AND maddr(7) AND maddr(9) AND NOT ctrl_in(1) AND NOT wr_maddr)); maddr_CLR(13) <= (NOT init_b AND NOT powerup); FTCPE_maddr14: FTCPE port map (maddr(14),maddr_T(14),cclk,maddr_CLR(14),'0'); maddr_T(14) <= ((EXP10_.EXP) OR (maddr(14) AND NOT mdata(6) AND cfg_done AND wr_maddr AND sel_byte(0)) OR (NOT maddr(14) AND mdata(6) AND cfg_done AND wr_maddr AND sel_byte(0) AND NOT sel_byte(1)) OR (maddr(0) AND maddr(1) AND maddr(2) AND maddr(3) AND maddr(4) AND maddr(5) AND maddr(6) AND maddr(8) AND maddr(10) AND maddr(11) AND maddr(12) AND maddr(13) AND maddr(7) AND maddr(9) AND NOT cfg_done) OR (maddr(0) AND maddr(1) AND maddr(2) AND maddr(3) AND maddr(4) AND maddr(5) AND maddr(6) AND maddr(8) AND maddr(10) AND maddr(11) AND maddr(12) AND maddr(13) AND maddr(7) AND maddr(9) AND NOT ctrl_in(1) AND NOT wr_maddr)); maddr_CLR(14) <= (NOT init_b AND NOT powerup); FTCPE_maddr15: FTCPE port map (maddr(15),maddr_T(15),cclk,maddr_CLR(15),'0'); maddr_T(15) <= ((maddr_cntr(16).EXP) OR (maddr(15) AND NOT mdata(7) AND cfg_done AND wr_maddr AND sel_byte(0)) OR (NOT maddr(15) AND mdata(7) AND cfg_done AND wr_maddr AND sel_byte(0) AND NOT sel_byte(1)) OR (maddr(0) AND maddr(1) AND maddr(2) AND maddr(3) AND maddr(4) AND maddr(5) AND maddr(6) AND maddr(8) AND maddr(10) AND maddr(11) AND maddr(12) AND maddr(13) AND maddr(14) AND maddr(7) AND maddr(9) AND NOT cfg_done) OR (maddr(0) AND maddr(1) AND maddr(2) AND maddr(3) AND maddr(4) AND maddr(5) AND maddr(6) AND maddr(8) AND maddr(10) AND maddr(11) AND maddr(12) AND maddr(13) AND maddr(14) AND maddr(7) AND maddr(9) AND NOT ctrl_in(1) AND NOT wr_maddr)); maddr_CLR(15) <= (NOT init_b AND NOT powerup); FTCPE_maddr16: FTCPE port map (maddr(16),maddr_T(16),cclk,maddr_CLR(16),'0'); maddr_T(16) <= ((EXP19_.EXP) OR (NOT maddr(16) AND mdata(0) AND cfg_done AND wr_maddr AND NOT sel_byte(0) AND sel_byte(1)) OR (maddr(0) AND maddr(15) AND maddr(1) AND maddr(2) AND maddr(3) AND maddr(4) AND maddr(5) AND maddr(6) AND maddr(8) AND maddr(10) AND maddr(11) AND maddr(12) AND maddr(13) AND maddr(14) AND maddr(7) AND maddr(9) AND NOT cfg_done) OR (maddr(0) AND maddr(15) AND maddr(1) AND maddr(2) AND maddr(3) AND maddr(4) AND maddr(5) AND maddr(6) AND maddr(8) AND maddr(10) AND maddr(11) AND maddr(12) AND maddr(13) AND maddr(14) AND maddr(7) AND maddr(9) AND NOT ctrl_in(1) AND NOT wr_maddr)); maddr_CLR(16) <= (NOT init_b AND NOT powerup); FTCPE_maddr17: FTCPE port map (maddr(17),maddr_T(17),cclk,maddr_CLR(17),'0'); maddr_T(17) <= ((EXP20_.EXP) OR (maddr(17) AND NOT mdata(1) AND cfg_done AND wr_maddr AND sel_byte(1)) OR (NOT maddr(17) AND mdata(1) AND cfg_done AND wr_maddr AND NOT sel_byte(0) AND sel_byte(1)) OR (maddr(0) AND maddr(15) AND maddr(16) AND maddr(1) AND maddr(2) AND maddr(3) AND maddr(4) AND maddr(5) AND maddr(6) AND maddr(8) AND maddr(10) AND maddr(11) AND maddr(12) AND maddr(13) AND maddr(14) AND maddr(7) AND maddr(9) AND NOT cfg_done) OR (maddr(0) AND maddr(15) AND maddr(16) AND maddr(1) AND maddr(2) AND maddr(3) AND maddr(4) AND maddr(5) AND maddr(6) AND maddr(8) AND maddr(10) AND maddr(11) AND maddr(12) AND maddr(13) AND maddr(14) AND maddr(7) AND maddr(9) AND NOT ctrl_in(1) AND NOT wr_maddr)); maddr_CLR(17) <= (NOT init_b AND NOT powerup); maddr(18) <= '0'; mce_b <= NOT (((NOT ctrl_in(0)) OR (NOT cfg_done AND NOT loc_mode) OR (NOT loc_cs AND NOT loc_add(6) AND loc_add(5) AND NOT loc_add(4) AND NOT loc_add(3) AND NOT loc_add(2) AND NOT loc_add(1) AND NOT loc_add(0) AND ctrl_in(1)))); FDCPE_mdata0: FDCPE port map (mdata_I(0),loc_bus(0).PIN,NOT loc_cs,'0','0'); mdata(0) <= mdata_I(0) when mdata_OE(0) = '1' else 'Z'; mdata_OE(0) <= w_data(6)/w_data(6)_TRST; FDCPE_mdata1: FDCPE port map (mdata_I(1),loc_bus(1).PIN,NOT loc_cs,'0','0'); mdata(1) <= mdata_I(1) when mdata_OE(1) = '1' else 'Z'; mdata_OE(1) <= w_data(6)/w_data(6)_TRST; FDCPE_mdata2: FDCPE port map (mdata_I(2),loc_bus(2).PIN,NOT loc_cs,'0','0'); mdata(2) <= mdata_I(2) when mdata_OE(2) = '1' else 'Z'; mdata_OE(2) <= w_data(6)/w_data(6)_TRST; FDCPE_mdata3: FDCPE port map (mdata_I(3),loc_bus(3).PIN,NOT loc_cs,'0','0'); mdata(3) <= mdata_I(3) when mdata_OE(3) = '1' else 'Z'; mdata_OE(3) <= w_data(6)/w_data(6)_TRST; FDCPE_mdata4: FDCPE port map (mdata_I(4),loc_bus(4).PIN,NOT loc_cs,'0','0'); mdata(4) <= mdata_I(4) when mdata_OE(4) = '1' else 'Z'; mdata_OE(4) <= w_data(6)/w_data(6)_TRST; FDCPE_mdata5: FDCPE port map (mdata_I(5),loc_bus(5).PIN,NOT loc_cs,'0','0'); mdata(5) <= mdata_I(5) when mdata_OE(5) = '1' else 'Z'; mdata_OE(5) <= w_data(6)/w_data(6)_TRST; FDCPE_mdata6: FDCPE port map (mdata_I(6),loc_bus(6).PIN,NOT loc_cs,'0','0'); mdata(6) <= mdata_I(6) when mdata_OE(6) = '1' else 'Z'; mdata_OE(6) <= w_data(6)/w_data(6)_TRST; FDCPE_mdata7: FDCPE port map (mdata_I(7),loc_bus(7).PIN,NOT loc_cs,'0','0'); mdata(7) <= mdata_I(7) when mdata_OE(7) = '1' else 'Z'; mdata_OE(7) <= w_data(6)/w_data(6)_TRST; moe_b <= ((NOT loc_rw AND cfg_done) OR (cfg_done AND NOT ctrl_in(1))); mwe_b <= ((NOT cfg_done) OR (loc_rw AND ctrl_in(1))); FDCPE_powerup: FDCPE port map (powerup,powerup_D,cclk,'0','0'); powerup_D <= (NOT maddr(17) AND powerup); FDCPE_prog: FDCPE port map (prog,loc_bus(1).PIN,NOT loc_cs,'0','0',prog_CE); prog_CE <= (NOT loc_rw AND loc_add(6) AND NOT loc_add(5) AND NOT loc_add(4) AND NOT loc_add(3) AND NOT loc_add(2) AND loc_add(1) AND loc_add(0) AND en_loc_bus); prog_b_I <= '0'; prog_b <= prog_b_I when prog_b_OE = '1' else 'Z'; prog_b_OE <= NOT ((NOT prog AND NOT powerup)); rdwr_b <= (loc_rw AND cfg_done); ring_os(0) <= ((cfg_done) OR (loc_mode) OR (NOT cclk_fb) OR (NOT init_b AND NOT powerup)); ring_os(1) <= ring_os(0); ring_os(2) <= ring_os(1); FDCPE_sel_byte0: FDCPE port map (sel_byte(0),loc_add(0),NOT loc_cs,'0','0'); FDCPE_sel_byte1: FDCPE port map (sel_byte(1),loc_add(1),NOT loc_cs,'0','0'); spare5 <= (loc_cs AND cfg_done); w_data(6)/w_data(6)_TRST <= ((done AND NOT loc_rw AND ctrl_in(1)) OR (NOT done AND NOT loc_rw AND loc_mode)); FDCPE_wr_maddr: FDCPE port map (wr_maddr,wr_maddr_D,NOT loc_cs,NOT ctrl_in(1),'0'); wr_maddr_D <= (NOT loc_rw AND loc_add(6) AND loc_add(5) AND NOT loc_add(4) AND NOT loc_add(3) AND NOT loc_add(2) AND cfg_done); Register Legend: FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); ****************************** Device Pin Out ***************************** Device : XC95144XL-10-TQ100 -------------------------------------------------- /100 98 96 94 92 90 88 86 84 82 80 78 76 \ | 99 97 95 93 91 89 87 85 83 81 79 77 | | 1 75 | | 2 74 | | 3 73 | | 4 72 | | 5 71 | | 6 70 | | 7 69 | | 8 68 | | 9 67 | | 10 66 | | 11 65 | | 12 64 | | 13 XC95144XL-10-TQ100 63 | | 14 62 | | 15 61 | | 16 60 | | 17 59 | | 18 58 | | 19 57 | | 20 56 | | 21 55 | | 22 54 | | 23 53 | | 24 52 | | 25 51 | | 27 29 31 33 35 37 39 41 43 45 47 49 | \26 28 30 32 34 36 38 40 42 44 46 48 50 / -------------------------------------------------- Pin Signal Pin Signal No. Name No. Name 1 maddr<13> 51 VCC 2 maddr<8> 52 loc_bus<3> 3 maddr<9> 53 PGND 4 maddr<11> 54 loc_bus<4> 5 VCC 55 PGND 6 mdata<0> 56 loc_bus<5> 7 PGND 57 VCC 8 mdata<1> 58 spare5 9 mdata<2> 59 loc_bus<6> 10 mdata<3> 60 PGND 11 mdata<4> 61 loc_bus<7> 12 mdata<5> 62 GND 13 mdata<6> 63 prog_b 14 mdata<7> 64 PGND 15 mce_b 65 init_b 16 maddr<10> 66 done 17 moe_b 67 ctrl_in<2> 18 rdwr_b 68 ctrl_in<0> 19 PGND 69 GND 20 cs_b 70 ctrl_in<1> 21 GND 71 loc_add_out<6> 22 cclk 72 loc_add_out<5> 23 cclkp 73 PGND 24 cclk_fb 74 loc_add_out<4> 25 cclk_fbp 75 GND 26 VCC 76 loc_add_out<3> 27 loc_cs 77 loc_add_out<2> 28 loc_rw 78 loc_add_out<1> 29 loc_add<0> 79 loc_add_out<0> 30 loc_add<1> 80 PGND 31 GND 81 maddr<3> 32 loc_add<2> 82 maddr<2> 33 loc_add<3> 83 TDO 34 PGND 84 GND 35 loc_add<4> 85 maddr<1> 36 loc_add<5> 86 maddr<0> 37 loc_add<6> 87 maddr<4> 38 VCC 88 VCC 39 PGND 89 maddr<5> 40 loc_bus<0> 90 maddr<6> 41 PGND 91 maddr<7> 42 loc_bus<1> 92 maddr<12> 43 PGND 93 maddr<15> 44 GND 94 maddr<16> 45 TDI 95 maddr<18> 46 PGND 96 mwe_b 47 TMS 97 maddr<17> 48 TCK 98 VCC 49 PGND 99 maddr<14> 50 loc_bus<2> 100 GND Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin TIE = Unused I/O floating -- must tie to VCC, GND or other signal KPR = Unused I/O with weak keeper (leave unconnected) VCC = Dedicated Power Pin GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc95144xl-10-TQ100 Optimization Method : SPEED Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : OFF Slew Rate : SLOW Power Mode : LOW Ground on Unused IOs : ON Set I/O Pin Termination : KEEPER Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON Input Limit : 54 Pterm Limit : 25