FB1
FB2
FB3
FB4
FB5
FB6
FB7
FB8
Signal Name
Total Product Terms
Product Terms
Location
Power Mode
Pin Number
PinType
Pin Use
sel_byte<1>
1
2_5
MC1
LOW
(b)
(b)
cclkp
5
2_1
2_2
2_3
2_4
3_2
MC2
LOW
23
I/O/GCK2
O
div<0>
1
3_1
MC3
LOW
(b)
(b)
crc_10_or0000/crc_10_or0000_D2__$INT
1
4_1
MC4
LOW
(b)
(b)
$OpTx$crc_7_xor0001/crc_7_xor0001_D2_INV$33
2
5_1
5_2
MC5
LOW
24
I/O
I
cclk_fbp
1
6_1
MC6
LOW
25
I/O
O
$OpTx$crc_13_xor0001/crc_13_xor0001_D2_INV$30
2
7_1
7_2
MC7
LOW
(b)
(b)
$OpTx$crc_12_xor0001/crc_12_xor0001_D2_INV$29
2
8_1
8_2
MC8
LOW
27
I/O/GCK3
GCK/I
$OpTx$crc_10_xor0003/crc_10_xor0003_D2_INV$28
2
9_1
9_2
MC9
LOW
28
I/O
I
$OpTx$crc_10_xor0003/crc_10_xor0003_D210__INV$35
2
10_1
10_2
MC10
LOW
(b)
(b)
$OpTx$crc_10_xor0001/crc_10_xor0001_D214__INV$38
2
11_1
11_2
MC11
LOW
29
I/O
I
$OpTx$crc_10_xor0001/crc_10_xor0001_D211__INV$36
2
12_1
12_2
MC12
LOW
30
I/O
I
ring_os<0>
4
13_1
13_2
13_3
13_4
MC13
LOW
(b)
(b)
crc<22>
4
14_1
14_2
14_3
14_4
MC14
LOW
32
I/O
I
crc<2>
5
14_5
15_1
15_2
15_3
15_4
MC15
LOW
33
I/O
I
crc<21>
5
15_5
16_1
16_2
16_3
16_4
MC16
LOW
(b)
(b)
crc<1>
5
16_5
17_1
17_2
17_3
17_4
MC17
LOW
34
I/O
(b)
crc<7>
11
17_5
18_1
18_2
18_3
18_4
18_5
1_1
1_2
1_3
1_4
1_5
MC18
LOW
(b)
(b)
Signals Used By Logic in Function Block
$OpTx$crc_10_xor0003/crc_10_xor0003_D2_INV$28
$OpTx$crc_7_xor0001/crc_7_xor0001_D2_INV$33
mdata<7>.PIN
mdata<2>.PIN
mdata<1>.PIN
cclk_fb
cfg_done
cfg_fail
crc<13>
crc<14>
crc<16>
crc<17>
crc<18>
crc<19>
crc<20>
crc<21>
crc<22>
crc<23>
crc_10_or0000/crc_10_or0000_D2__$INT
ctrl_in<0>
ctrl_in<1>
div<4>
en_conf
loc_add<1>
loc_add<5>
loc_add<6>
loc_cs
loc_mode
loc_rw
powerup
prog
ring_os<2>