Xilinx Design Summary

Device Utilization Summary
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	414	7,168	5%
Number of 4 input LUTs	2,688	7,168	37%
Logic Distribution
Number of occupied Slices	1,693	3,584	47%
Number of Slices containing only related logic	1,693	1,693	100%
Number of Slices containing unrelated logic	0	1,693	0%
Total Number 4 input LUTs	2,713	7,168	37%
Number used as logic	2,688
Number used as a route-thru	23
Number used as Shift registers	2
Number of bonded IOBs	240	264	90%
IOB Flip Flops	111
IOB Master Pads	1
IOB Slave Pads	1
IOB Dual-Data Rate Flops	1
Number of Block RAMs	10	16	62%
Number of GCLKs	4	8	50%
Number of DCMs	2	4	50%
Total equivalent gate count for design	695,988
Additional JTAG gate count for IOBs	11,520

Performance Summary
Final Timing Score:	0	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met