address 0x0 Tp_x to GOLx_data mapping scheme number (r/w) 0 => GOL0_data(23:0) = TP_a(23:0),GOL1_data(23:0) = TP_b(23:0),GOL2_data(23:0) = TP_a(23:0), 1 => GOL0_data(23:0) = TP_b(23:0),GOL1_data(23:0) = TP_a(23:0),GOL2_data(23:0) = TP_b(23:0), 2-239 => unused 0xf0 => GOL0_data(23:0) = TP_a(23:0),GOL1_data(11:0) = TP_a(35:24), GOL1_data(23:12) = TP_b(11:0),GOL2_data(23:0) = TP_b(35:12) 0xf1 => GOL0_data(23:0) = x"111111",GOL1_data(23:0) = x"111111",GOL2_data(23:0) = x"111111" 0xf2 => GOL0_data(23:0) = x"222222",GOL1_data(23:0) = x"222222",GOL2_data(23:0) = x"222222" 0xf3 => GOL0_data(23:0) = GOL1_data(23:0) = GOL2_data(23:0) = 24-bit LFSR 0xf4 => GOL0_data(23:0) = GOL1_data(23:0) = GOL2_data(23:0) = a single '1' left rotating shifter 0xf5 => GOL0_data(23:0) = GOL1_data(23:0) = GOL2_data(23:0) = x"555555" and x"aaaaaa" toggling 0xf6 => GOL0_data(23:0) = GOL1_data(23:0) = GOL2_data(23:0) = 24-bit counter 0xf7 => GOL0_data(23:0) = GOL1_data(23:0) = GOL2_data(23:0) = 24-bit left shifter with bit0 = bit23 inverted 0xf8 => GOL0_data(23:0) = 24 LSBs of a 32-bit LFSR GOL1_data(7:0) = 8 MSBs of a 32-bit LFSR GOL1_data(11:8) = x"5" GOL1_data(23:12) = 12 LSBs of a 32-bit LFSR GOL2_data(19:0) = 20 MSBs of a 32-bit LFSR GOL1_data(23:20) = x"a" 0xf9 => GOL0_data(7:0) = a single '1' left rotating shifter GOL0_data(15:8) = same as GOL0_data(7:0) GOL0_data(23:16) = same as GOL0_data(7:0) GOL1_data(23:0) same as GOL0_data(23:0) GOL2_data(23:0) same as GOL0_data(23:0) 0xfa => GOL0_data(7:0) = 8bit counter GOL0_data(15:8) = same as GOL0_data(7:0) GOL0_data(23:16) = same as GOL0_data(7:0) GOL1_data(23:0) same as GOL0_data(23:0) GOL2_data(23:0) same as GOL0_data(23:0) 0xfb => GOL0_data(23:0) = GOL1_data(23:0) = GOL2_data(23:0) = x"555555" 0xfc => GOL0_data(23:0) = GOL1_data(23:0) = GOL2_data(23:0) = x"aaaaaa" 0xfd => GOL0_data(23:0) = GOL1_data(23:0) = GOL2_data(23:0) = x"a5a5a5" 0xfe => GOL0_data(23:0) = GOL1_data(23:0) = GOL2_data(23:0) = x"ffffff" 0xff => GOL0_data(23:0) = GOL1_data(23:0) = GOL2_data(23:0) = x"000000" address 0x4 csr (r/w) bit 0 GOL0 clock disble (default enable) bit 1 GOL1 clock disble (default enable) bit 2 GOL2 clock disble (default enable) bit 3 Bypass QPLL (default use QPLL) bit 4 If set to '1', all GOLs output x"12345678" bit 5-6 unused bit 7 force GOLs to send data instead of idle address 0x8 status1 (read only) bit 0 run bit 1 GOL's neg_edge setting bit 2 bc_err bit 3 QPLL_err bit 4 QPLL_locked bit 5 GOL0 ready bit 6 GOL1 ready bit 7 GOL2 ready address 0xc status2 (read) bit 0 rx clock stopped bit 1 ttc clock stopped bit 2 ttc clock dcm locked bit 3 rx clock dcm locked bit 4 always '0' bit 5 always '0' bit 6 i2c_fail bit 7 i2c_busy address 0xc i2c address register (write) bit 2-0 GOL register address bit 4-3 GOL selection: "00" -> GOL0, "01" -> GOL1, "10" -> GOL2 bit 6 unused bit 7 if '1', starts an i2c read operation address 0x10 GOL0 spy data (read only) one byte at a time, LSB byte first address 0x14 GOL1 spy data (read only) one byte at a time, LSB byte first address 0x18 GOL2 spy data (read only) one byte at a time, LSB byte first address 0x1c i2c_data (r/w) address 0x20 ps counter should always be 0x30 (read only) address 0x24 ps state low 7 bits (read only) address 0x28 ps state high 7 bits (read only) address 0x2c FPGA version (read only) address 0x30 GOL0 32-bit spy data address counter (r/w) when write, loc_data written to 8 MSBs and two SLBs reset to '0' this counter increments every four byte readings. when read, 8 LSBs are read out address 0x34 GOL1 32-bit spy data address counter (r/w) when write, loc_data written to 8 MSBs and two SLBs reset to '0' this counter increments every four byte readings. when read, 8 LSBs are read out address 0x38 GOL2 32-bit spy data address counter (r/w) when write, loc_data written to 8 MSBs and two SLBs reset to '0' this counter increments every four byte readings. when read, 8 LSBs are read out address 0x3c GOLx spy data address counter 2 MSBs (read only) bit 1-0 GOL0 MSBs bit 3-2 GOL1 MSBs bit 5-4 GOL2 MSBs bit 7-6 always '0' address 0x40 commands (write only) bit 0 clears FLASH buffer address counter bit 1 takes a snapshot of GOLx_data bit 2-7 unused address 0x44 FLASH buffer data register (write only) used to buffer 256 bytes of data for FLASH programming address 0x48 resets (write only, returns '0' by itself) bit 0 resets all (equivalent to write 0x7e) bit 1 resets DCM and sets GOL's neg_edge signal bit 2 resets QPLL bit 3 resets GOL0 bit 4 resets GOL1 bit 5 resets GOL2 bit 6 loads clock fanout control register address 0x80 FLASH data (r/w) write is only used to write commands to FLASH address 0x100 low byte of configuration data checksum (read only) address 0x104 mid byte of configuration data checksum (read only) address 0x108 high byte of configuration data checksum (read only) address 0x10c CPLD csr (r/w) bit 0 local bus mode ( configure FPGA via local bus) FPGA configuration data are written to address 0x0 bit 1 reprogram FPGA It does not return to '0' by itself bit 2 FPGA init_b pin status (read only) bit 3 FPGA done pin status (read only) bit 4 FPGA to CPLD control bit 0 (read only) bit 5 FPGA to CPLD control bit 1 (read only) bit 6 always '1' (read only) bit 7 always '0' (read only) address 0x180 low byte of FLASH address register (r/w) address 0x184 mid byte of FLASH address register (r/w) address 0x188 two MSBs of FLASH address register (r/w) for FLASH programming, these two bits of the address must be written last. address 0x18c resets FLASH address register to all '0' (write) CPLD version(read) It is possible to program the FPGA directly using slave parellel mode. To do that, first write 0x3 to address 0x10c, then write 0x1 to the same address. read data from address 0x100 until bit2(FPGA init_b status) is '1' writing configuration byte data to address 0x0 until all data done The FLASH memory is programmed in blocks of 256 bytes. To program a FLASH block, first write 0x1 to address 0x40 to reset the buffer address counter. Next write 256 bytes of data to address 0x44. FLASH address is set by writing to addresses 0x180(LSB byte), 0x184(middle byte) and 0x188(two MSB bits) To start FLASH programming, First set FLASH address to 0x5555, then write 0xaa to address 0x80 Next set FLASH address to 0x2aaa, then write 0x55 to address 0x80 Next set FLASH address to 0x5555, then write 0xa0 to address 0x80 Finally set FLASH address to the starting address of the block, When FPGA sees that FLASH address has been wriiten, it starts sending data to the FLASH. Wait until bit5 at address 0x10c is '1'. Checking bit 6 at address 0x80 until it stops toggling to start next page of FLASH programming. I2C access access of I2C registers of GOLs uses registers 0xc and 0x1C: to write to GOL, first write to register 0xc: bits 4-3 specifies GOL and bits 2-0 specifies register number. then write the data to register 0x1c. Read from register 0xc, when bit 7 is '0', I2C write has finished. Make sure bit 6 is '0', if bit 6 is set, operation has failed. to read from GOL, first write to register 0xc: bits 4-3 specifies GOL and bits 2-0 specifies register number. bit 7 must be set to indicate a read operation. Read from register 0xc until bit 7 is '0', Make sure bit 6 is '0', if bit 6 is set, operation has failed. If bit 6 is '0', register 0x1c has the read out data. related software on cms2 in ~wusx/my_dcc cfgFPGA.cc usage: ./cfgFPGA.exe htr_slb.mcs function: configure FPGA with htr_slb.mcs writeFLASH.cc usage: ./writeFLASH.exe htr_slb.mcs [v] function: program FLASH with file htr_slb.mcs if option v is used, only performs verification oslb.cc usage: ./oslb.exe function: multiple read/write, multiple 32-bit GOL spy buffer read, 32/24-bit LFSR tests. type 'h' for help oslb_rom.c usage: ./oslb_rom.exe function: convert TP input mapping file "rom.txt" to RAMB init file "oslb_init.txt". Patch "oslb_init.txt" to the bottom section of file "htr_slb.ucf". rd_HTR.cc usage: ./rd_HTR.exe function: reads HTR spy buffer and check for 24-bit LFSR How to send pattern from HTR FPGA using HTR_osl_27.mcs write 6 to HTR FPGA local address 0xc to enable test pattern and select ttc clock write N to HTR FPGA local address 0x2a0 N TPx(31:0) pattern 0x8000 evenly spaced four '1' bits left shifting 0x8001 32-bit counter 0x8002 0xaaaaaaaa and 0x55555555 toggling 0x8003 32-bit LFSR 0x8004 32-bit left shifter with bit0 change to bit31 inverted 0x8005 MSB byte always 0, 24 LSBs as 24-bit LFSR 0x8006 bit31-27 all '0', bit26-24 3-bit counter, bit23-0 24-bit counter 0x8007 0xffffffff GOL output format bit 31 odd parity of bits 27-21 bit 30 odd parity of bits 20-14 bit 29 odd parity of bits 13-7 bit 28 odd parity of bits 6-0 bit 27 BC0 bit 26-24 BCN[2:0] bit 23-0 hits