new version oslbRPCv0x9b -- 3/27/2017 fixed a bug in negedge logic. Otherwise no change from 0x99 new version oslbRPCv0x99 -- 3/27/2017 added bit 6 to reg 0x4. If bit 4 and 6 are both 1, bcn(TP_A(33)=1 when bcn = 0) and bcnoslb are sent as data. new version oslbRPCv0x98 -- 3/24/2017 modified according to the request from Richard and Drew registers 0x24 and 0x28 used to store setSLBbcnInOrbit GOL data bit 31-29 TP_A(26:24), bit 28 TP_A(33) GOL data bit 27-25 lower three bits of oSLBbcn, bit 24 set when oSLBbcn = 0 new version oslbRPCv0x97 -- 3/6/2017 Fixed a bug with the transition from IDLE to data new version oslbRPCv0x96 -- 3/3/2017 registers 0x24 and 0x28 used to set offset of front end BC0 to HTR BC0 GOL data bit 31-29 lower three bcnt of HTR, bit 28 HTR BC0 GOL data bit 27-25 lower three bcnt of HTR with offset, bit 24 BC0 with offset GOL conf_negedge logic improved new version oslbRPCv0x94 -- 1/20/2017 Corrected an error in BC0 checking introduced in version 0x92 new version oslbRPCv0x93 -- 1/17/2017 This version is based on v0x92, if bit 3 of register 0x4c is set to 1, instead of TP_A/TP_B, RPC_sender data inputs will be a 28bit test data. The 4 MSBs of the test data will always be all zero, and the 24 LSBs will be either test_data set by reg 0x50 through 0x58 if bit 4 of reg 0x4C is zero and a 24bit pseudo-random number when that bit is 1 new version oslbRPCv0x86 -- 11/20/2016 Fixed some errors in TP mapping new version oslbRPCv0x85 -- 7/29/2016 New generation algorithm for GOL neg_edge signal new version oslbRPCv0x84 -- 6/7/2016 fixed a bug in ram256x8.vhd which caused FLASH write errors new version oslbRPCv0x82 -- 2/15/2016 Found a typo in mapping file romRPC.txt new version oslbRPCv0x81 -- 2/14/2016 implemented new mappings 3, 16, 17 and 18 new version oslbRPCv0x80 -- 10/10/2015 RPC_sender.vhd replaces H0_sender.vhd fiber 0 data inputs are TP_a[23:0] fiber 1 data inputs are {0x00,TP_b[15:0]} fiber 2 data inputs are {0x0000,TP_b[23:16]} new version oslbve -- 1/10/2008 changes: start and stop run by TTC command removed. run is equivalent to bit 7 of register 0x4 bugs in resync fixed new version oslbvd -- 1/9/2008 changes: added bit 4 to register 0x4C to enable GOLs output 32-bit pseudo-random sequence data new version oslbvc -- 11/5/2007 changes: histogram and synchronization added. Major resguffle of register assignments. Detail refer to the register address map below. new version oslbvb -- 10/17/2007 changes: ttc command register added at 0x20 new version oslbva -- 9/17/2007 changes: parameter INPUT_REGISTERED in module H0_sender changed to FALSE, this reduced the latency by one clock cycle. new version oslbv9 -- 9/12/2007 changes: test_ena moved to register 0x4c bit 3 test_data is now implemented as read/write registers 0x50 - 0x5c old test vectors removed new version oslbv8 -- 9/11/2007 changes: Output format changed using vhdl module H0_sender provided by the trigger group new register csr1 at 0x4c added. Its bits 0 thru 2 are mapped to H0_sender's check_ena, check_data_ena and test_rand_ena H0_sender's resetN signal is mapped to bit 7 of address 0x48 (bit 0 also generates resetN) address 0x0 Tp_x to GOLx_data mapping scheme number (r/w) 3, 16, 17 and 18 implemented others => unused, output all zero address 0x4 csr (r/w) bit 0 GOL0 clock disble (default enable) bit 1 GOL1 clock disble (default enable) bit 2 GOL2 clock disble (default enable) bit 3 Bypass QPLL (default use QPLL) bit 4 if '1', test_data bits 23-0 replaces TP_a and TP_b bits 23-0 bit 5 enables TTC broadcast synchronization bit 6 if '1', test_data bits 23-12 is bcn and 11-0 is oSLBbcn bit 7 force GOLs to send data instead of idle note: any change in clock setting (bit 0-3) must be followed by a write of 0x40 or 0x1 to register 0x48 to take effect address 0x8 status1 (read only) bit 0 run bit 1 GOL's neg_edge setting bit 2 bc_err bit 3 QPLL_err bit 4 QPLL_locked bit 5 GOL0 ready bit 6 GOL1 ready bit 7 GOL2 ready address 0xc status2 (read) bit 0 rx clock stopped bit 1 ttc clock stopped bit 2 ttc clock dcm locked bit 3 rx clock dcm locked bit 4 always '0' bit 5 always '0' bit 6 i2c_fail bit 7 i2c_busy address 0xc i2c address register (write) bit 2-0 GOL register address bit 4-3 GOL selection: "00" -> GOL0, "01" -> GOL1, "10" -> GOL2 bit 6 unused bit 7 if '1', starts an i2c read operation address 0x10 GOL spy data (read only) one byte at a time, LSB byte first address 0x14 GOL spy data read address low(r/w/autoincrement) bit 7-0 GOL spy data address bits 7-0 address 0x18 GOL spy data read address high(r/w/autoincrement) bit 1-0 GOL spy data address bits 9-8 bit 3-2 00 selects GOL0, 01 GOL1 and 10 GOL2 bit 7-4 unused GOL spy data read address wraps around back to 0 at 0xbff address 0x1c i2c_data (r/w) address 0x20 sync counts address 0x24 low 8 bits of setSLBbcnInOrbit(r/w) address 0x28 high 4 bits of setSLBbcnInOrbit(r/w) bit 3-0 high 4 bits of setSLBbcnInOrbit bit 7-4 unused address 0x2c FPGA version (read only) address 0x30 sync idle count low(bits 7-0) (r/w) address 0x34 sync idle count high(bits 15-8) (r/w) address 0x38 sync test pattern count low(bits 7-0) (r/w) address 0x3c sync test pattern count high(bits 15-8) (r/w) address 0x40 commands (write only) bit 0 clears FLASH buffer address counter bit 1 takes a snapshot of GOLx_data bit 2 clears histogram bit 3 if bits 3-2 of register 0x74 are both '1', fills histogram memory for 16 orbits bit 4 triggers synchronzation bit 5 resets sync counter 0x20 bit 6-7 unused address 0x44 FLASH buffer data register (write only) used to buffer 256 bytes of data for FLASH programming address 0x48 resets (write only, returns '0' by itself) bit 0 resets error counters bit 1 resets DCM and sets GOL's neg_edge signal bit 2 resets QPLL bit 3 resets GOL0 bit 4 resets GOL1 bit 5 resets GOL2 bit 6 loads clock fanout control register bit 7 not used address 0x4c csr1 (r/w) bit 0-2 not used bit 4 if set to '1', test_data is 24-bit pseudo-random sequence data The VHDL code for the generator is as following: lfsr <= lfsr(22 downto 0) & not(lfsr(23) xor lfsr(22) xor lfsr(21) xor lfs(16)); bit 5-7 unused address 0x50 test_data bit7-0 (r/w) address 0x54 test_data bit15-8 (r/w) address 0x58 test_data bit23-16 (r/w) address 0x60 error counters (read only) address 0x64 error counter selection (r/W/autoincrement) bit 2-0 000 DCM lost lock 001 GOL0 went not ready 010 GOL1 went not ready 011 GOL2 went not ready 100 QPLL lost lock 101 QPLL error 110 BC0 error 111 BCNs from TP_a and TP_b disagree bit 7-3 unused address 0x68 sync command (r/w) address 0x6c sync mask (r/w) a bit set to '1' makes corresponding bit in the broadcasted command being ignored address 0x70 histogram data (read only) address 0x74 histogram source selection (r/w) bit 3-0 0000 TP_a 0-3 0001 TP_a 4-7 0010 TP_a 8-11 0011 TP_a 12-15 0100 TP_a 16-19 0101 TP_a 20-23 0110 TP_b 0-3 0111 TP_b 4-7 1000 TP_b 8-11 1001 TP_b 12-15 1010 TP_b 16-19 1011 TP_b 20-23 11xx simulated hits for testing histogramming bit 7-4 if bit 3-2 set to 11, these bits enables corresponding channels address 0x78 histogram address low (r/w) bit 7-0 bits 7-0 of BCN address 0x7c histogram address high (r/w/auto increment) bit 3-0 bits 11-8 of BCN bit 5-4 selects one out of four TP_x pins bit 7-6 unused histogram address bits 11-0 wraps around back to 0 at 0xdeb and increments bits 13-12 address 0x80 FLASH data (r/w) write is only used to write commands to FLASH address 0x100 low byte of configuration data checksum (read only) address 0x104 mid byte of configuration data checksum (read only) address 0x108 high byte of configuration data checksum (read only) address 0x10c CPLD csr (r/w) bit 0 local bus mode ( configure FPGA via local bus) FPGA configuration data are written to address 0x0 bit 1 reprogram FPGA It does not return to '0' by itself bit 2 FPGA init_b pin status (read only) bit 3 FPGA done pin status (read only) bit 4 FPGA to CPLD control bit 0 (read only) bit 5 FPGA to CPLD control bit 1 (read only) bit 6 always '1' (read only) bit 7 always '0' (read only) address 0x180 low byte of FLASH address register (r/w) address 0x184 mid byte of FLASH address register (r/w) address 0x188 bit 1-0 two MSBs of FLASH address register (r/w) for FLASH programming, these two bits of the address must be written last. bit 7-2 debug info, should all be '0' when FPGA is configured address 0x18c resets FLASH address register to all '0' (write) CPLD version(read) It is possible to program the FPGA directly using slave parellel mode. To do that, first write 0x3 to address 0x10c, then write 0x1 to the same address. read data from address 0x100 until bit2(FPGA init_b status) is '1' writing configuration byte data to address 0x0 until all data done The FLASH memory is programmed in blocks of 256 bytes. To program a FLASH block, first write 0x1 to address 0x40 to reset the buffer address counter. Next write 256 bytes of data to address 0x44. FLASH address is set by writing to addresses 0x180(LSB byte), 0x184(middle byte) and 0x188(two MSB bits) To start FLASH programming, First set FLASH address to 0x5555, then write 0xaa to address 0x80 Next set FLASH address to 0x2aaa, then write 0x55 to address 0x80 Next set FLASH address to 0x5555, then write 0xa0 to address 0x80 Finally set FLASH address to the starting address of the block, When FPGA sees that FLASH address has been wriiten, it starts sending data to the FLASH. Wait until bit5 at address 0x10c is '1'. Checking bit 6 at address 0x80 until it stops toggling to start next page of FLASH programming. I2C access access of I2C registers of GOLs uses registers 0xc and 0x1C: to write to GOL, first write to register 0xc: bits 4-3 specifies GOL and bits 2-0 specifies register number. then write the data to register 0x1c. Read from register 0xc, when bit 7 is '0', I2C write has finished. Make sure bit 6 is '0', if bit 6 is set, operation has failed. to read from GOL, first write to register 0xc: bits 4-3 specifies GOL and bits 2-0 specifies register number. bit 7 must be set to indicate a read operation. Read from register 0xc until bit 7 is '0', Make sure bit 6 is '0', if bit 6 is set, operation has failed. If bit 6 is '0', register 0x1c has the read out data. related software on cms2 in ~wusx/my_dcc cfgFPGA.cc usage: ./cfgFPGA.exe htr_slb.mcs function: configure FPGA with htr_slb.mcs writeFLASH.cc usage: ./writeFLASH.exe htr_slb.mcs [v] function: program FLASH with file htr_slb.mcs if option v is used, only performs verification oslb.cc usage: ./oslb.exe function: multiple read/write, multiple 32-bit GOL spy buffer read, 32/24-bit LFSR tests. type 'h' for help oslb_rom.c usage: ./oslbRPC_rom.exe function: convert TP input mapping file "romRPC.txt" to RAMB init file "oslb_initRPC.txt". Patch "oslb_initRPC.txt" to the bottom section of file "oslbRPC.ucf". rd_HTR.cc usage: ./rd_HTR.exe function: reads HTR spy buffer and check for 24-bit LFSR How to send pattern from HTR FPGA using HTR_osl_27.mcs write 6 to HTR FPGA local address 0xc to enable test pattern and select ttc clock write N to HTR FPGA local address 0x2a0 N TPx(31:0) pattern 0x8000 evenly spaced four '1' bits left shifting 0x8001 32-bit counter 0x8002 0xaaaaaaaa and 0x55555555 toggling 0x8003 32-bit LFSR 0x8004 32-bit left shifter with bit0 change to bit31 inverted 0x8005 MSB byte always 0, 24 LSBs as 24-bit LFSR 0x8006 bit31-27 all '0', bit26-24 3-bit counter, bit23-0 24-bit counter 0x8007 0xffffffff